B. Clocking > P_CLK Programming
500
Tsi578 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
B.2.3.5
I2C_SCLK High and Low Timing Register
The I2C_SCLK High and Low Timing Register programs the nominal high and low periods of the
I2C_SCLK signal when generated by the master interface.
It is shadowed during boot loading, and can be reprogrammed prior to a chain operation without
affecting the bus timing for the current EEPROM.
SCL_HIGH Count for I2C_SCLK High Period
The SCL_HIGH field defines the nominal high period of the clock, from rising edge to falling edge of
I2C_SCLK. This is a master-only parameter.
The actual observed period may be shorter if other devices pull the clock low.
•
Period(SCL_HIGH) = (SCL_HIGH * Period(P_CLK))
— P_CLK is 10 ns
— Reset time is 5.00 microseconds (100 kHz)
— Tsi578 reset value is 0x01F4
SCL_LOW Count for I2C_SCLK Low Period
The SCL_LOW field defines the nominal low period of the clock, from falling edge to rising edge of
I2C_SCLK. This is a master-only parameter.
The actual observed period may be longer if other devices pull the clock low.
•
Period(SCL_LOW) = (SCL_LOW * Period(P_CLK))
— P_CLK is 10 ns
— Reset time is 5.00 microseconds (100 kHz)
— Tsi578 reset value is 0x01F4
B.2.3.6
I2C_SCLK Minimum High and Low Timing Register
The I2C_SCLK Minimum High and Low Timing Register programs the minimum high and low
periods of the I2C_SCLK signal when generated by the master interface. It is shadowed during boot
loading, and can be reprogrammed prior to a chain operation without affecting the bus timing for the
current EEPROM.
SCL_MINH Count for I2C_SCLK High Minimum Period
The SCL_MINH field defines the minimum high period of the clock, from rising edge seen high to
falling edge of I2C_SCLK. This is a master-only parameter.
The actual observed period may be shorter if other devices pull the clock low.
•
Period(SCL_MINH) = (SCL_MINH * Period(P_CLK))
— P_CLK is 10 ns
— Reset time is 4.01 microseconds
— Tsi578 reset value is 0x0191
