B. Clocking > Line Rate Support
490
Tsi578 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
All bit and register settings that are documented for operation with S_CLK = 156.25 .MHz also apply
to the use of 153.6 MHz and 125 MHz. For more clocking information, see “Clocks” in the
Tsi578
User Manual
.
B.1.1
Register Requirements Using 125 MHz S_CLK for a 3.125 Gbps Link Rate
In order to use S_CLK at 125 MHz to create a 3.125 Gbps link baud rate, the default values in the
SerDes PLL Control Register must be modified from a x20 multiplier to a x25 multiplier. On
power-up, the default PLL multipliers of x20 causes the 125 MHz source to create a 2.5 Gbps link rate.
Changing this link rate to 3.125 Gbps requires either intervention by the I
2
C boot EEPROM during
boot loading to reconfigure the SerDes, or the intervention of an external host to modify the SerDes
registers through the use of maintenance transactions. However, modifying by EEPROM is the
recommended method.
B.1.1.1
Modification by EEPROM Boot Load
Modifying the EEPROM is the recommended method for using the S_CLK at 125 MHz to create a
3.125 Gbps link baud rate because the EEPROM boot load accesses the required configuration
registers before the SerDes are released from reset. This can be performed by modifying the EEPROM
loading script (for more information, see “EEPROM Scripts” in the
Tsi578 User Manual
).
Once the boot load is complete, the modified switch ports operate at 3.125 Gbps, while the remaining
ports operate at 2.5 Gbps.
125.00
1.2500
Standard RapidIO Line Rate
0,1
-
125.00
2.5000
Standard RapidIO Line Rate
1,0
-
125.00
3.1250
Standard RapidIO Line Rate
1,0
Using 125 MHz S_CLK for a
3.125 Gbps Link Rate” on
page 490
a.
This information assumes a +/- 100 ppm clock tolerance that must be obeyed between link partners.
The SerDes PLL Control Registers are volatile. Applying HARD_RST_b or asserting
PWRDN_x4 results in the SerDes PLL Control Register default value being re-applied.
Table 53: Tsi578 Supported Line Rates (Continued)
a
S_CLK_p/n (MHz)
Baud Rate (Gbaud)
SP_IO_SPEED[1,0] Bit
Settings
Register Settings
