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IDT Tsi578, User Manual

The IDT Tsi578 is a high-performance networking switch, and to help you make the most out of its features, we provide a comprehensive User Manual. This manual is available for free download from our website, ensuring effortless access to valuable product information and instructions for optimal usage.

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7. I

2

C Interface > Tsi578 as I

2

C Slave

157

Tsi578 User Manual

June 6, 2016

Integrated Device Technology

www.idt.com

7.5.6

Slave Read Data Transactions

An external master is not required to set the peripheral address as part of a read transaction, but can do 
so by first writing the peripheral address and then issuing a Restart before writing any data. If not set, 
the read data starts wherever the peripheral address pointer was left by the previous transaction. 
Because it is possible that another master changed the pointer, it is recommended that the peripheral 
address be set at the start of a transaction. Data is returned to the external master from consecutive 
bytes within the peripheral address space, with certain exceptions indicated in 

Table 17

. 

There also can be side effects to reading some bytes (see 

Table 17

 and the EXI2C register descriptions). 

For example, a read that hits the LSB of the 

“Externally Visible I

2

C Internal Read Address Register”

 

(peripheral address 0x14), also triggers a read from a register on the Tsi578 internal register bus. 

7.5.7

Slave Internal Register Accesses

The Tsi578 allows external masters to access all of its internal registers through the externally visible 
I

2

C registers. 

The 

“Externally Visible I

2

C Internal Read Data Register”

 is a special register in that a read operation to 

the first (least significant) byte of this register through the peripheral address space (0x14) triggers the 
Tsi578 to perform an internal register read operation using the address in the 

“Externally Visible I

2

C 

Internal Read Address Register”

. When the internal register read operation is completed, the data is 

first loaded into the 

“Externally Visible I

2

C Internal Read Data Register”

, then returned to the external 

I

2

C master byte by byte. The 

“Externally Visible I

2

C Internal Access Control Register”

 controls the 

internal register read operations and allows the user to specify when and how the register read is 
performed. 

Likewise, the 

“Externally Visible I

2

C Internal Write Data Register”

 triggers the Tsi578 to perform an 

internal register write operation using the address in the 

“Externally Visible I

2

C Internal Write Address 

Register”

. The external device writes data to the 

“Externally Visible I

2

C Internal Write Data Register”

 

through the peripheral space, and when the last (most significant) byte is written (0x07), the register 
contents is written through the internal register bus to the address in the 

“Externally Visible I

2

C 

Internal Write Address Register”

. The 

“Externally Visible I

2

C Internal Access Control Register”

 

controls the internal register write operation and allows the user to specify when and how the register 
write is performed. 

Internal register accesses can be prohibited by the processor/host through the RD_EN and WR_EN 
fields in the 

“I

2

C Slave Configuration Register”

. 

At the completion of a slave transaction that includes a successful read or write to an internal register, a 
SA_WRITE or SA_READ interrupt status is updated in the I2C_INT_STAT register. An optional 
interrupt can also be sent to the Interrupt Controller if enabled in SA_WRITE and SA_READ of 

“I

2

C 

Interrupt Enable Register”

. This allows the processor/host to be aware that an external device is 

accessing the internal registers of the Tsi578. 

The address in the register definitions refers to an offset only. The offset must be prefixed 
with the block address. 

Summary of Contents for Tsi578

Page 1: ...IDT Tsi578 Serial RapidIO Switch User Manual June 6 2016 Titl ...

Page 2: ...on request Items identified herein as reserved or undefined are reserved for future definition IDT does not assume responsibility for conflicts or incompatibilities arising from the future definition of such items IDT products have not been designed tested or manufactured for use in and thus are not warranted for applications where the failure malfunction or any inaccuracy in the application carri...

Page 3: ...abric ISF 30 1 6 Internal Register Bus AHB 30 1 7 I2 C Interface 30 1 8 JTAG Interface 32 2 Serial RapidIO Interface 35 2 1 Overview 35 2 1 1 Features 35 2 1 2 Transaction Flow Overview 36 2 1 3 Maintenance Requests 36 2 1 4 Control Symbols 36 2 2 Transaction Flow 37 2 3 Lookup Tables 37 2 3 1 Filling the Lookup Tables 38 2 3 2 LUT Modes 40 2 3 3 Flat Mode 40 2 3 4 Hierarchical Mode 45 2 3 5 Mixed...

Page 4: ...0 3 4 1 Changing the Clock Speed 71 3 4 2 Changing the Clock Speed Through I2C 71 3 5 Port Power Down 72 3 5 1 Default Configurations on Power Down 72 3 5 2 Special Conditions for Port 0 Power Down 73 3 5 3 Power Down Options 73 3 5 4 Configuration and Operation Through Power down 73 3 6 Port Lanes 74 3 6 1 Lane Synchronization and Alignment 75 3 6 2 Lane Swapping 75 3 7 Programmable Transmit and ...

Page 5: ... Overview 106 5 1 6 Multicast Work Queue 107 5 1 7 Broadcast Buffers 107 5 2 Multicast Group Tables 110 5 2 1 Configuring Basic Associations 112 5 2 2 Configuring Multicast Masks 113 5 2 3 Configuring Multicast Masks Using the IDT Specific Registers 116 5 3 Arbitration for Multicast Engine Ingress Port 117 5 4 Error Management of Multicast Packets 118 5 4 1 Packet TEA 118 5 4 2 Multicast Packet St...

Page 6: ...Master Data Transactions 151 7 5 Tsi578 as I2C Slave 151 7 5 1 Slave Clock Stretching 153 7 5 2 Slave Device Addressing 154 7 5 3 Slave Peripheral Addressing 154 7 5 4 External I2 C Register Map 155 7 5 5 Slave Write Data Transactions 156 7 5 6 Slave Read Data Transactions 157 7 5 7 Slave Internal Register Accesses 157 7 5 8 Slave Access Examples 158 7 5 9 Resetting the I2C Slave Interface 161 7 6...

Page 7: ...ements 192 8 3 1 Clock Speeds 192 8 3 2 Tsi578 ISF Arbitration Settings 192 8 3 3 Tsi578 RapidIO Transmission Scheduler Settings 193 8 3 4 Tsi578 RapidIO Buffer Watermark Selection Settings 193 8 4 Port to Port Performance Characteristics 193 8 4 1 Port to Port Packet Latency Performance 193 8 4 2 Packet Throughput Performance 194 8 4 3 Multicast Performance 195 8 5 Congestion Detection and Manage...

Page 8: ...246 12 5 2 RapidIO Device Information CAR 247 12 5 3 RapidIO Assembly Identity CAR 248 12 5 4 RapidIO Assembly Information CAR 249 12 5 5 RapidIO Processing Element Features CAR 250 12 5 6 RapidIO Switch Port Information CAR 252 12 5 7 RapidIO Source Operation CAR 253 12 5 8 RapidIO Switch Multicast Support CAR 255 12 5 9 RapidIO Route LUT Size CAR 256 12 5 10 RapidIO Switch Multicast Information ...

Page 9: ... and Debug 2 302 12 7 14 RapidIO Port x Packet Error Capture CSR 2 and Debug 3 302 12 7 15 RapidIO Port x Packet Error Capture CSR 3 and Debug 4 303 12 7 16 RapidIO Port x Error Rate CSR 304 12 7 17 RapidIO Port x Error Rate Threshold CSR 306 12 8 IDT Specific RapidIO Registers 307 12 8 1 RapidIO Port x Discovery Timer 309 12 8 2 RapidIO Port x Mode CSR 310 12 8 3 RapidIO Port x Multicast Event Co...

Page 10: ...AC x SerDes Configuration Global 372 12 10 7 SRIO MAC x SerDes Configuration GlobalB 376 12 10 8 SRIO MAC x Digital Loopback and Clock Selection Register 377 12 11 Internal Switching Fabric ISF Registers 380 12 11 1 Fabric Control Register 380 12 11 2 Fabric Interrupt Status Register 382 12 11 3 RapidIO Broadcast Buffer Maximum Latency Expired Error Register 384 12 11 4 RapidIO Broadcast Buffer Ma...

Page 11: ...nfiguration Register 437 13 2 12 I2C Boot Control Register 440 13 2 13 Externally Visible I2C Internal Write Address Register 444 13 2 14 Externally Visible I2C Internal Write Data Register 445 13 2 15 Externally Visible I2C Internal Read Address Register 446 13 2 16 Externally Visible I2C Internal Read Data Register 447 13 2 17 Externally Visible I2C Slave Access Status Register 448 13 2 18 Exter...

Page 12: ...al Protocol 484 B Clocking 489 B 1 Line Rate Support 489 B 1 1 Register Requirements Using 125 MHz S_CLK for a 3 125 Gbps Link Rate 490 B 2 P_CLK Programming 493 B 2 1 RapidIO Specifications Directly Affected by Changes in the P_CLK Frequency 493 B 2 2 IDT Specific Timers 496 B 2 3 I2C interface and Timers 497 B 2 4 Other Performance Factors 503 C PRBS Scripts 505 C 1 Tsi578_start_prbs_all txt Scr...

Page 13: ... Queues in Tsi578 91 Figure 20 Multicast Operation Option 1 104 Figure 21 Multicast Operation Option 2 105 Figure 22 Multicast Packet Flow in the Tsi578 108 Figure 23 Relationship Representation 112 Figure 24 Completed Tables at the End of Configuration 114 Figure 25 IDT specific Multicast Mask Configuration 117 Figure 26 Arbitration Algorithm for Multicast Port 118 Figure 27 Control Symbol Format...

Page 14: ...ted Device Technology www idt com Figure 43 Congestion Example 200 Figure 44 Register Access From JTAG Serial Data In 202 Figure 45 Register Access From JTAG Serial Data Out 202 Figure 46 Tsi578 Clocking Architecture 206 Figure 47 Signal Groupings 218 ...

Page 15: ...Visible I2C Register Map 155 Table 18 Format for Boot Loadable EEPROM 171 Table 19 Sample EEPROM Loading Two Registers 171 Table 20 Sample EEPROM With Chaining 172 Table 21 I2C Error Handling 174 Table 22 I2C Interrupt to Events Mapping 178 Table 23 Performance Monitoring Parameters 189 Table 24 4x 1x Latency Numbers Under No Congestion 194 Table 25 4x 1x Multicast Latency Numbers Under No Congest...

Page 16: ...le 47 AC JTAG level programmed by ACJT_LVL 4 0 374 Table 48 SerDes Register Map 402 Table 49 I2C Register Map 415 Table 50 Master Operation Sequence 424 Table 51 Special Characters and Encoding 485 Table 52 Control Symbol Construction 486 Table 53 Tsi578 Supported Line Rates 489 Table 54 Timer Values with P_CLK and TVAL Variations 494 Table 55 Timer Values with DISCOVERY_TIMER and P_CLK Variations...

Page 17: ...active state of logic 0 or the lower voltage level and is denoted by a lowercase _b An active high signal has an active state of logic 1 or the higher voltage level and is not denoted by a special character The following table illustrates the non differential signal naming convention Differential Signal Notation Differential signals consist of pairs of complement positive and negative signals that...

Page 18: ...y and is revised as required Formal Contains information about a final customer ready product and is available once the product is released to production Revision History June 6 2016 Formal Updated Reserved Register Addresses and Fields Updated the second caution in RapidIO Error Management Extension Registers Updated the description of bit 31 Reserved in the following registers SRIO MAC x SerDes ...

Page 19: ...s_all txt Script May 25 2012 Formal Updated the second step in Removing a Destination ID to Multicast Mask Association Updated the second paragraph in Payload Updated Port writes and Multicast Updated the registers listed in Global Registers to Program after Port Power Down Added a note about how SW_RST_b is the only external indicator that a reset request has been received to System Control of Re...

Page 20: ...About this Document 20 Tsi578 User Manual June 6 2016 Integrated Device Technology www idt com ...

Page 21: ...porting 80 Gbits s aggregate bandwidth The Tsi578 is part of a family of switches that enable customers to develop systems with robust features and high performance at low cost The Tsi578 provides designers and architects with maximum scalability to design the device into a wide range of applications Flexible port configurations can be selected through multiple port width and frequency options Bui...

Page 22: ...ations The Tsi578 can be used in many embedded communication applications It provides chip to chip interconnect between I O devices and can replace existing proprietary backplane fabrics for board to board interconnect which improves system cost and product time to market 80B803A_BK001_03 SP0 4x or 1x SP1 1x only SP4 4x or 1x SP5 1x only SP8 4x or 1x SP9 1x only SP12 4x or 1x SP13 1x only SP2 4x o...

Page 23: ...cket prioritization when it is used with RapidIO enabled I O devices When it is in a system with multiple RapidIO enabled processors it provides high performance peer to peer communication through its non blocking switch fabric Figure 3 Switch Carrier Blade 80B803A_TA001_01 Dual Serial RapidIO DSP DSP T si578 80B803A_TA002_01 Serial RapidIO Mesh AMC Slot AMC Slot AMC Slot AMC Slot T si578 T si578 ...

Page 24: ...r consumption Ability to reverse the bit ordering of a 4x port to simplify PCB layout Transport Layer RapidIO Features Dedicated destination ID lookup table per port used to direct packets through the switch Supports both hierarchical lookup tables and flat mode lookup tables 512 destination IDs per lookup table Supports an optional unique hierarchical destination ID lookup table covering all 64K ...

Page 25: ... system operation IEEE 1149 1 and 1149 6 boundary scan with register access Internal switching fabric ISF Full duplex 80 Gbps line rate non blocking switching fabric Prevents head of line blocking on each port Eight packet buffers per ingress port Eight packet buffers per egress port Register Access Registers can be accessed from any RapidIO interface and both the JTAG interface and I2C Optionally...

Page 26: ... Debug packet generation and capture Multicast functionality described in RapidIO Interconnect Specification Revision 1 3 Part 11 Head of line blocking avoidance 1 2 2 Transaction Flow Overview Packets and control symbols are received by the Serial RapidIO Electrical Interface Serial MAC and forwarded to the RapidIO Interface for more information on the Serial MAC refer to Serial RapidIO Electrica...

Page 27: ...ast functionality is compliant to the RapidIO Version 1 3 Part 11 Multicast Specification 1 3 1 Multicast Operation In a multicast operation packets are received at the speed of any ingress port up to 10 Gbits s and broadcast at the speed of the egress ports up to 10 Gbits s for a 4x mode port operating at 3 125 Gbits s to multiple ports capable of accepting packets for transmission The maximum am...

Page 28: ...testing features including multiple loopback modes and bit error rate testing Each pair of ports share four differential transmit lanes and four differential receive lanes Even and odd number ports have different capabilities Even numbered ports can operate in either 4x or 1x mode while odd numbered ports can only operate in 1x mode When the even numbered port is operating in 4x mode it has contro...

Page 29: ... a port configured for 4x mode 3 125 Gbit s inbound and 3 125 Gbit s outbound bandwidth at 3 125 Gbps for a port configured for 1x mode Adjustable receive equalization that is programmable per lane Serial loopback with a built in testability Bit error rate testing BERT Scope function of eye signals Hot insertion capable I Os and hardware support Serial Rapid IO Registers and Buffers Even numbered ...

Page 30: ...us AHB allows any RapidIO port to configure and maintain the entire device When the Tsi578 receives a RapidIO maintenance packet destined for itself it translates the packet into register read or write request on the AHB The device registers can also be accessed through the JTAG interface or the I2C interface 1 7 I2C Interface The I2C Interface provides a master and slave serial interface that can...

Page 31: ...PROM or by software configuration Provides mailbox registers for communicating between maintenance software operating on RapidIO based processors and external I2 C masters Supports I2 C operations up to 100 kHz Provides boot time register initialization Supports 1 and 2 byte addressing of the EEPROM selected by power up signal Verifies the number of registers to be loaded is legal before loading r...

Page 32: ...o its device address without consideration for any other meaning General Call The general call address will be NACK d and the remainder of the transaction ignored up to a subsequent Restart or Stop 1 8 JTAG Interface The JTAG interface in Tsi578 is fully compliant with IEEE 1149 6 Boundary Scan Testing of Advanced Digital Networks as well as IEEE 1149 1 Standard Test Access Port and Boundary Scan ...

Page 33: ...1 Functional Overview JTAG Interface 33 Tsi578 User Manual June 6 2016 Integrated Device Technology www idt com Bypass Hi Z IDCODE Clamp User data select ...

Page 34: ...1 Functional Overview JTAG Interface 34 Tsi578 User Manual June 6 2016 Integrated Device Technology www idt com ...

Page 35: ...iant with the RapidIO Interconnect Specification Revision 1 3 This section describes the transport layer features common to all Tsi578 RapidIO interfaces The RapidIO interface has the following capabilities RapidIO packet and control symbol transmission RapidIO packet and control symbol reception Register access through RapidIO maintenance requests 2 1 1 Features The following features are support...

Page 36: ...ckets to be transmitted from the ISF The integrity of packets forwarded through the ISF is retained by sending the CRC code received with the packet For more information on the input and ouput queues refer to Packet Queuing on page 95 The packet transmitter and the packet receiver cooperate to ensure that packets are never dropped lost A transmitter must retain a packet in its buffers until the po...

Page 37: ...ived However in both modes the egress port always operates in cut through mode the packet is immediately forwarded A copy of the packet is saved at the egress port so that it can be retransmitted should an error occur Packets delivered to a Multicast Engine MCE are replicated based on user configured multicast groups The MCE sends copies of the original packet to the egress ports in a parallel fas...

Page 38: ...IO Route Configuration DestID CSR on page 260 using the LRG_CFG_DESTID and CFG_DESTID fields the upper seven bits of the destination ID in the LRG_CFG_DESTID field is truncated The LUT of all the ports can be loaded simultaneously if it is desired to have the same routing entries in all of the ports required The loading process is similar to loading an individual port s LUT however alternative reg...

Page 39: ...stID 15 8 BASE field in SPx_ROUTE_BASE Yes No Obtain egress port from GLOBAL LUT using DestID 15 8 Obtain egress port from LOCAL LUT using DestID 7 0 LUT entry mapped and egress port Port_Total Yes No Route to egress port defined in LUT DestID 256 Yes Obtain egress port from LOCAL LUT using DestID 7 0 No DestID 512 No Flat Yes Obtain egress port from GLOBAL LUT using DestID 8 0 Default egress port...

Page 40: ...ort x Mode CSR on page 310 2 3 3 Flat Mode A flat mode LUT is a table that maps destination IDs 0 to 511 to user selectable egress ports Destination IDs that fall outside this range are sent to the egress port identified in the RIO Route LUT Attributes CSR see RapidIO Route LUT Attributes Default Port CSR Figure 6 shows the configuration of the Local and Global Lookup tables LUT in Flat mode Flat ...

Page 41: ...T Attributes Default Port CSR on page 262 If the default port is unmapped the packet is discarded and the Tsi578 raises the IMP_SPEC_ERR bit in the RapidIO Port x Error Detect CSR on page 294 100 1FF 00 FF DestID Port DestID Port Local LUT Global LUT DestID MSB is loaded into Global LUT through the LRG_CFG_DEST_ID and CFG_DEST_ID fields in the RIO_ROUTE_CFG_DESTID register Egress Port is loaded in...

Page 42: ...into Global LUT through the PORT field in the RIO_ROUTE_CFG_PORT register Tsi57x Tsi57x Tsi57x DSP DSP DSP DSP DestID 0x13 DestID 0x11 DestID 0x12 DestID 0x10 DestIDs accessible through this link 0x02xx to 0xFFxx DestIDs accessible through this link 0x01xx DestID 0xFE33 Ingress Packets A B C 8 14 9 0 1 2 3 DestID 0x0137 DestID 0x12 Example packets Default Port 14 137 9 10 11 12 13 3 2 1 0 DestID M...

Page 43: ... 0x0002 or 0x02 is routed by the switch to output port 1 A destination ID of 0x0003 or 0x03 is routed out port 0 and destination IDs greater than 0x1FF are routed out port 4 Figure 8 Flat Mode LUT Configuration Example Registers Used in Lookup Table Configuration The Tsi578 s RapidIO interfaces are compliant with the RapidIO Interconnect Specification Revision 1 3 The following standard RapidIO re...

Page 44: ...or write this register to change the configuration of the destination ID Example One Adding a Lookup Table Entry In the following example routing is added for all ports to route destination ID 0x98 to output port 0x4 To add a lookup table perform the following steps 1 Write to the RapidIO Port x Route Config DestID CSR on page 314 using the broadcast offset 0x10070 with a value of 0x00000098 This ...

Page 45: ... 0x54 2 3 4 Hierarchical Mode The hierarchical mode of operation of the LUT allows the full range of 65536 16 bit destination IDs to be mapped This mode is enabled by setting RIO_SP_MODE LUT_512 0 The hierarchical mode of operation uses two LUTs each containing 256 entries For packets with 8 bit destination IDs the ingress port uses the ID as an index into the local LUT see Flat Mode For packets w...

Page 46: ...nly advertises the switch can map 512 destination IDs This is due to the fact that RIO_LUT_SIZE is a register with global scope but the ports can be independently configured for either flat mode or hierarchical mode lookup 00 FF 00 FF MSB of DestID Port LSB of DestID Port xx DestID LSB is loaded into the Local LUT through the CFG_DEST_ID field of the RIO_ROUTE_CFG_DESTID register Egress Port is lo...

Page 47: ...kets A B C 00 FF 00 FF MSB of DestID Port LSB of DestID Port xx DestID LSB is loaded into Local LUT through the CFG_DESTID field in the RIO_ROUTE_CFG_DESTID register DestID MSB is loaded into Global LUT through the BASE field in the SPx_ROUTE_BASE register DestID MSB is loaded into Global LUT through the LRG_CFG_DESTID field in the RIO_ROUTE_CFG_DESTID register Global LUT Local LUT Default Port 28...

Page 48: ...y time before packet traffic starts w 0078 0x0A 3 Program the Global LUT with the MSB of the DEST_IDs to be routed using the following write operations W 11870 0x0 SP8_ROUTE_CFG_DESTID W 11874 0x9 SP8_ROUTE_CFG_PORT W 11870 0x0100 W 11874 0x9 W 11870 0x0200 W 11874 0x9 W 11870 0xFE00 W 11874 0xE W 11870 0xFF00 W 11874 0xE 4 Program the MSB of the DEST_ID that will be used to index into the Local L...

Page 49: ...ured mode of operation 2 3 6 Lookup Table Parity Each entry in the lookup table is parity protected A LUT parity error is detected in an entry when an incoming packet causes the ingress port to read that table entry If the ingress port detects an error it discards the packet and reports the error see Table 1 Because the packet is discarded on the ingress port the packet is never forwarded to the e...

Page 50: ...m the request queue The TEA error is reported through a port write and or an interrupt Programmable in the Fabric Control Register and the interrupt status can be checked in the Fabric Interrupt Status Register Packet routed to unconnected portc c It s the same as a powered on port except that the Link Partner was behaving as disconnected to the port The port is healthy and when the link partner i...

Page 51: ... table entries must be programmed to a known value after reset to achieve predictable operation When a lookup table entry s parity is incorrect the lookup table entry is in a parity error state Table 2 shows the possible lookup table states Table 2 Lookup Table States Lookup Table Entry State How to get into States Action on Packet Arrival Mapped A lookup table entry that routes packets to a port ...

Page 52: ...t is to be sent parity errors are still detected and flagged if they occur Since the LUTs power up in a random state the occurrence of a LUT_PAR_ERR will be a random occurrence until all LUT entries are programmed with values to support all destIDs that the switch encounters Parity Error When a lookup table entry s parity is incorrect the lookup table entry is in a parity error state Packet Header...

Page 53: ...ny data associated with the request The maintenance response packet is generated by the Tsi578 using the success or failure of the access and data from a read operation CRC is computed and the packet is enqueued for transmission on the port that received the maintenance request Each port can have only one outstanding maintenance request at a time A maintenance request received while another mainte...

Page 54: ... count is 0 Do not care Send port write and set interrupt if enabled Bit 8 in RapidIO Logical and Transport Layer Error Detect CSR Tsi578 is not an endpoint device Port Write Hop count is 0 Do not care Send port write and set interrupt if enabled Bit 9 in RapidIO Logical and Transport Layer Error Detect CSR Tsi578 is not an endpoint device Reserved Transaction Type Hop count is 0 Do not care Send ...

Page 55: ...bol and Reset Control Symbol Interrupt CSR on page 312 Additionally the logical OR of all per port Multicast Event interrupt status is available in both the MCS field in the RapidIO Port x Multicast Event Control Symbol and Reset Control Symbol Interrupt CSR on page 312 and the MCS field in the Global Interrupt Status Register on page 388 Interrupts can be cleared either per port or for all ports ...

Page 56: ...ports enabled to forward multicast control symbols then transmit an MCS see RapidIO Serial Port x Control CSR on page 281 The minimum time between two transitions on the MCES pin is 1 s For example when the host needs to create a heartbeat for the entire system at 125kHz it should use a 62 5kHz clock to generate the pulse driving the MCES pin 2 5 3 Restrictions Only one port on the Tsi578 should b...

Page 57: ...des With the exception of maintenance packets the Tsi578 does not re compute CRC codes for packets The CRC code is forwarded with the packet across the ISF and the packet is transmitted with the same CRC code it was received with This ensures that packet corruption within the Tsi578 is detected The exception to the rule for CRC codes is the handling of maintenance packets Maintenance packets have ...

Page 58: ... of the inbound outbound and outstanding ACK_IDs 4 The system host instructs the Tsi578 to generate a link request to its link partner using the RapidIO Serial Port x Link Maintenance Request CSR on page 273 5 The system host reads the link partner s response in the Tsi578 s RapidIO Serial Port x Link Maintenance Response CSR on page 275 6 The system host sets the switch s outbound ACK_ID value to...

Page 59: ...her packets other than maintenance requests responses may be sent by the Tsi578 INPUT_EN Controls whether packets other than maintenance requests responses may be received by the Tsi578 In RapidIO Port x Interrupt Status Register LINK_INIT_NOTIFICATION This is an interrupt bit When the PORT_LOCKOUT bit is set this bit indicates that the link has been successfully initialized This is an interrupt b...

Page 60: ...ependent Register to assert an interrupt or send port write transactions see RapidIO Port x Control Independent Register Once the system host is notified that a new component is inserted the LINK_INIT_NOTIFICATION bit should be cleared in the RapidIO Port x Interrupt Status Register to stop the assertion of interrupts The PORT_LOCKOUT bit must be cleared to allow the system host to access the new ...

Page 61: ...ll packets arriving from the ISF for transmission to flush any existing packets in the transmit and receive queues of the port and to prevent new packets from being received from the device about to be extracted At this point the component can be safely extracted The LUT entries for all ports in the Tsi578 can be configured to not route any packets to the port on which the hot extraction occurs Wh...

Page 62: ...e LINK_INIT_NOTIFICATION_EN in the RapidIO Port x Control Independent Register continues to be enabled When the component is removed lane synchronization and or lane alignment is lost The errors detected cause a port write and or interrupt to be sent to the system host indicating that a component may have been extracted 2 10 Loss of Lane Synchronization A loss of lane synchronization LOLS can occu...

Page 63: ...ctual duration of the LOLS condition has no impact on the process once the link is re acquired Any packets transmitted to the Tsi578 are not acknowledged because the port is in input error stopped state The link partner times out waiting for a packet acknowledge control symbol and enters the output error stopped state To recover the link partner sends a link request input status control symbol to ...

Page 64: ...is reported in the PORT_ERR bit in the RapidIO Port x Error and Status CSR When the PORT_ERR bit is set and port writes are enabled a port write is generated If the dead link timer expires which the link is no longer able to transmit or receive then the port starts removing the impact of the dead link partner from the system The port drops all packets in its transmit buffers Any new packets that a...

Page 65: ... port and one odd numbered port Each port has flexible testing features including multiple loopback modes and bit error rate testing Each pair of ports share four differential transmit lanes and four differential receive lanes Even and odd number ports have different capabilities Even numbered ports can operate in either 4x or 1x mode while odd numbered ports can only operate in 1x mode When the e...

Page 66: ...rt configured for 4x mode 3 125 Gbit s inbound and 3 125 Gbit s outbound bandwidth at 3 125 Gbps for a port configured for 1x mode Adjustable receive equalization that is programmable per lane Serial loopback with a built in testability Bit error rate testing BERT Scope function of eye signals Hot insertion capable I Os and hardware support Serial Rapid IO Registers and Buffers Even numbered Ports...

Page 67: ...ther 4x or 1x mode can be configured as either one 4x mode port or dual 1x mode ports For example SP0 can be configured as either one 4x mode port or Port 0 and Port 1 can be dual 1x mode ports Table 4 Tsi578 Port Numbering Port Number RapidIO Port Mode 0 Serial Port 0 SP0 1x or 4x 1 Serial Port 1 SP1 1x 2 Serial Port 2 SP2 1x or 4x 3 Serial Port 3 SP3 1x 4 Serial Port 4 SP4 1x or 4x 5 Serial Port...

Page 68: ...r pulled low for 4x 0x mode see Signals on page 215 These pins are sampled after reset is de asserted To ensure that the pins are sampled correctly the pins must be stable at the release of reset and held at a stable level for 10 clock cycles after reset is de asserted The sampled state of the pins is reflected in the PORT_WIDTH field in the RapidIO Serial Port x Control CSR on page 281 After rese...

Page 69: ...s that share the same MAC also share the same transmit clock which means the two ports must have the same bit rate To select the bit rate write the IO_SPEED field see SRIO MAC x Digital Loopback and Clock Selection Register on page 377 as described in Clocking on page 70 The initial clock rate is selected by the global power up option for all ports 3 3 2 4x Configuration When the even numbered por...

Page 70: ...te all internal clocks for processing the data When the frequency of the reference clock is set at 156 25 MHz Tsi578 can support three different RapidIO standard signaling rates 3 125 Gbps 2 5 Gbps and 1 25 Gbps Table 5 shows the port speeds and bandwidths supported by the Tsi578 For more information on clocking refer to Clocks Resets and Power up Options on page 205 and Clocking on page 489 It is...

Page 71: ... Power Down on page 72 3 4 2 Changing the Clock Speed Through I2 C The Tsi578 can be configured to power up with ports at different link speeds by setting the SRIO MAC x Digital Loopback and Clock Selection Register on page 377 by an external I2C master access or by an EEPROM boot load The most effective way to configure the port link speed through the I2 C register load is to leave the port power...

Page 72: ...sters IDT Specific RapidIO Registers see IDT Specific RapidIO Registers The following register types can be read and written to when a port is powered down Serial Port Electrical Layer Registers on page 361 Internal Switching Fabric ISF Registers I2C Registers on page 415 Utility Unit Registers on page 388 3 5 1 Default Configurations on Power Down When a port is powered down the port loses config...

Page 73: ...written like any other port that has been powered down 3 5 3 Power Down Options The following power down options are available on a port A port s main logic can be powered down at boot up through the SP n _PWRDN pins The default configuration provided by the pins can be changed using the PWDN_X4 and PWDN_X1 bits in the SRIO MAC x Digital Loopback and Clock Selection Register This can occur during ...

Page 74: ...e in 1x mode When the even numbered port is operating in 4x mode it has control over all four differential pairs designated Lanes A B C and D 1x 1x De assert the SPn_PWRDN pin and or set the PWDN_X4 bit to 0 in the SRIO MAC x Digital Loopback and Clock Selection Register on page 377 De assert the SPn 1_PWRDN pin and or set the PWDN_X1 bit to 0 in the SRIO MAC x Digital Loopback and Clock Selection...

Page 75: ...ication Revision 1 3 idle sequence generation rules Reception of four A s without the intervening reception of a misaligned column is the condition for achieving lane alignment A misaligned column that is a column with at least one A but not all A s in a row causes the alignment process to restart Bit errors or receptions of rows without all A s result in sampling buffering adjustments in an attem...

Page 76: ...ablished with the changed lane configuration 3 6 2 2 Lanes and Channels The terms lanes and channels identify input and output signals Lanes are enumerated using alphabetic characters A B C D The pin associated with a lane changes depending on the lane swap settings Channels are numbered 0 through 3 Channels are never reordered When lanes are not swapped the following mapping between channels and ...

Page 77: ... lane The Tsi578 also has the ability to internally boost the received signal This functionality is described in the following sections 3 7 1 Transmit Drive Level and Equalization The Tsi578 has programmable drive strengths and de emphasis of a transmit lane This ability adjusts for the electrical characteristics that can degrade the signal quality of a link which connects a device to the Tsi578 D...

Page 78: ...ister RX_EQ_VAL field in the SRIO MAC x SerDes Configuration Channel 0 on page 363 The equation involving the 3 bit values of the register field are described by Receiver boost RX_EQ_VAL 1 0 5 dB For example setting RX_EQ_VAL 2 0 3 b100 results in a 2 5dB boost of the received signal This boost is internal to the device and is useful in improving the signal at the slicer when the signal arriving a...

Page 79: ...where each loopback is implemented in the Tsi578 Figure 15 Tsi578 Loopbacks Internal Switching Fabric Serial RapidIO Physical and Transport Layers Even numbered Ports 4x mode or 1x mode Odd Numbered Ports 1x mode only More RapidIO Ports Digital Equipment Loopback Logical Line Loopback SerDes Lane A PRBS Gen 8B 10B Enc 8B 10B Dec SerDes Lane B PRBS Gen 8B 10B Enc 8B 10B Dec PRBS Chk SerDes Lane C P...

Page 80: ...To cause packets to loop back in this fashion configure the lookup tables LUTs so the destination IDs are destined for the incoming port For more information on LUT programming refer to Lookup Tables 3 9 Bit Error Rate Testing BERT The RapidIO ports on the Tsi578 have a built in bit error rate test BERT This test is based either on fixed symbols or on a pseudo random bit sequence PRBS Each lane wi...

Page 81: ...Des Framing Depending on the type of testing required in the system the SerDes framing function might need to be disabled in the Tsi578 For example framing must be disabled if a BERT test is performed To disable the framer write to the RX_ALIGN_EN bit in the SMACx_CFG_CHy register see SRIO MAC x SerDes Configuration Channel 0 Disabling this feature makes sure that data passes through the loopback ...

Page 82: ...Fixed Pattern based BERT Fixed pattern based BERT uses data in software configurable registers to send an alternating pattern of 10 bit 8B10B code groups Fixed pattern based BERT does not produce error count results Fixed patterns are programmed in the PAT0 field and selected by setting the appropriate MODE field in the SerDes Lane 0 Pattern Generator Control Register on page 403 The following thr...

Page 83: ...RX_ALIGN_EN bit in the SMACx_CFG_CH 0 3 register 3 9 4 Using PRBS Scripts for the Transmitters and Receivers IDT provides PRBS scripts in PRBS Scripts All of the PRBS scripts affect all of the ports therefore editing the files to comment out the respective transmitting and receiving ports where testing is not desired is required The following sequence must be followed when using the PRBS scripts T...

Page 84: ...3 Serial RapidIO Electrical Interface Bit Error Rate Testing BERT 84 Tsi578 User Manual June 6 2016 Integrated Device Technology www idt com ...

Page 85: ...age 88 4 1 Overview The Internal Switching Fabric ISF is the crossbar switching matrix at the core of the Tsi578 It transfers packets from ingress ports to egress ports and prioritizes traffic based on the RapidIO priority associated with a packet and port congestion The ISF has the following features Full duplex non blocking crossbar based switch fabric 10 Gbits s fabric ports allow up to 10x int...

Page 86: ... attempt to send a packet to the same egress port queuing is required at the ingress ports Special arbitration algorithms at both the ingress and egress sides of the fabric ensure that head of line blocking is avoided in these queues Queuing is also required at the egress ports Packets can accumulate when an egress port has to re transmit a packet for example due to a CRC error or when a high band...

Page 87: ...mation appears near the front of a RapidIO packet Congestion Configuring a port for cut through mode does not guarantee that the packet is sent to the ISF immediately after the destination ID arrives for the packet Congestion in the ISF can mean that some or all of the packet is received before the switching operation begins Cut through mode generally provides better system performance However in ...

Page 88: ... Figure 17 Only HOL packets at the ingress queues or broadcast buffers are considered for arbitration Figure 17 Egress Arbitration Weighted Round Robin and Strict Priority 4 3 1 Strict Priority Arbitration The ISF always considers packet priority with a strict priority SP service algorithm The output arbiters ensure that all traffic with RapidIO priority N is sent before any traffic with RapidIO p...

Page 89: ...he same arbiter exists for each Priority Group Depending on the setting of WRR_EN the Multicast Traffic can participate in the Round Robin arbiter The WRR arbiter consists of a Round Robin arbiter which services its inputs sequentially starting at Port 0 on reset The Chosen Packet Counter is only used for weighted operation between multicast and unicast transactions Otherwise the RR arbiter output...

Page 90: ...is not reached Once the WEIGHT value is reached a non chosen packet is selected instead and the Chose Packet Counter is reset In the case when no chosen packet is available when its opportunity arises the WRR arbiter automatically selects the non chosen packets Similar behaviour applies to non chosen packet When the opportunity to transmit non chosen packets arises and there is none available a pa...

Page 91: ...o store the incoming packets when the egress port has a slower baud rate than the ingress port The depth of the buffer queue dictates the switch fabric flow control This flow control determines how many packets of a certain priority an egress port can receive In the event that the output queue is full the ingress port is notified and must begin queuing packets If the ingress port runs out of buffe...

Page 92: ... free buffers is greater than the programmed watermark of the associated priority For example when the PRIO1WM field is programmed to three a priority 1 packet is accepted only when there are four or more free buffers The three programmed watermarks PRIO0WM PRIO1WM and PRIO2WM must contain values where PRIO0WM PRIO1WM PRIO2WM 0 at all times The watermarks for the three priorities must allow for th...

Page 93: ...e while one packet in the burst is being transmitted and is awaiting acknowledgment another packet in the burst cannot be accepted or transmitted Watermarks can be used to guarantee that two buffers are available for these packets When two buffers are available while one packet is transmitted and awaits acknowledgement another packet can be accepted This leads to an increase in throughput for pack...

Page 94: ...fer to Loss of Lane Synchronization on page 62 4 4 2 Input Queue for the ISF Port Each ingress port has a queue that holds up to eight packets Buffering is required to deal with any congestion in the ISF Since the ISF is a crossbar switch each egress port can receive one packet from the ISF at a time If multiple ingress ports need to send to the same egress port all but one of the ingress ports mu...

Page 95: ...ne HOL blocking can result HOL occurs when the packet at the head of a queue is blocked and the packets must remain in the same order This means that no packet in the queue can be sent across the ISF even if all the packets save the first have an uncongested path to their respective destinations The ISF manages HOL blocking by reordering packets in a manner compliant with the RapidIO Interconnect ...

Page 96: ...biter selects a packet to compete in egress arbitration based on the following rules Select the priority 3 packet that can be accepted by its destination fabric port and is closest to the head of the queue Else if there are no such packets Select the priority 2 packet that can be accepted by its destination fabric port and is closest to the head of the queue Else if there are no such packets Selec...

Page 97: ...acket closest to the head of the queue Note that this packet cannot make progress Else if there are no such packets Select the priority 1 packet that can be accepted by its destination fabric port and is closest to the head of the queue Else if there are no such packets Select the priority 1 packet closest to the head of the queue Note that this packet cannot make progress Else if there are no suc...

Page 98: ...ter than Y that appear ahead of packet X in the queue must also be 0 Reorder limiting is disabled by default and can be enabled by setting the RDR_LIMIT_EN bit to 1 in the Fabric Control Register on page 380 Enabling this feature is recommended Note that reorder limiting applies to all ports and all packets in the Tsi578 The number of times a packet is permitted to be delayed by a lower or same pr...

Page 99: ...ort on page 117 Any priority N packet is accepted before packets of priority N 1 Within each priority the multicast work queue uses the round robin algorithm The multicast work queue operates in strict First In First Out FIFO order and has no watermarks associated with it The multicast work queue always allows packets to cut through to the broadcast buffer Refer to Cut through Mode on page 87 for ...

Page 100: ...pace for 8 more bytes of data to be received the multicast work queue is signalled that no more packet data can be accepted by the broadcast buffer If there is sufficient space for 8 more bytes of data to be received the multicast work queue is signalled that more packet data can be accepted by the broadcast buffer 4 4 6 Output Queuing Model for Multicast Both the multicast work queue and the broa...

Page 101: ...es idles whenever the ingress port has not yet received data for transmission However during the transfer the egress port cannot receive information from ports other than the egress port Therefore when transferring data between ports of different bandwidths it is recommended that the slower port not operate in cut through mode Refer to the TRANS_MODE bit in RapidIO Port x Control Independent Regis...

Page 102: ...4 Internal Switching Fabric Packet Queuing 102 Tsi578 User Manual June 6 2016 Integrated Device Technology www idt com ...

Page 103: ...t s based on the the number of ports on the Tsi578 Packets are routed to the multicast engine based on their destinationID and Transaction Type TT field value If no match is found for the destinationID and TT field then the ingress lookup tables are used to route the packet A maximum of eight different DestID TT field combinations can be routed to the multicast engine Each destinationID TT set can...

Page 104: ...Multiple Tsi57x Switches Tsi57x multicast support is designed to allow information from a single source to be multicast efficiently over a tree topology within a RapidIO fabric see Figure 20 When two or more Tsi57x switches are connected to each other however multicasting packets in both directions between the switches may create a dependency loop that causes a deadlock Figure 20 Multicast Operati...

Page 105: ... multicast group is associated with a unique destinationID and TT of a packet Note A packet is never multicast back out of the port that it is received on regardless of whether or not this port is included in the multicast group Multicast Mask The set of egress ports in a multicast group Multicast Vector The set of ports in a multicast group that will receive the multicast packets The vector is us...

Page 106: ...o the Broadcast Buffers associated with the ports in the vector Transmission between the multicast work queue and the Broadcast Buffers uses a dedicated ISF path that is separate from those used to route unicast traffic Once the packet copies have been completely received by all of the broadcast buffers in the multicast vector each broadcast buffer arbitrates with its associated egress ports to ac...

Page 107: ...y Timer on page 119 When the multicast work queue has computed the multicast vector it arbitrates to transmit packet copies to the broadcast buffers accordingly The work queue always operates in a cut through fashion A packet is not dropped if it is STOMPed when it is received in the multicast work queue The STOMPed packet is replicated to the broadcast buffers Similarly if a packet exceeds the ti...

Page 108: ...r a packet copy to the maximum value of seven For more information refer to Error Management of Multicast Packets on page 118 The following figure shows a step by step multicast operation through the Tsi578 with numbered descriptions of the events below the diagram Figure 22 Multicast Packet Flow in the Tsi578 1 When the ISF clock speed is set to 156 25 MHz Tip In RapidIO technology a datum means ...

Page 109: ...t work queue operates in cut through mode 5 By consulting the multicast group table Ports 0 1 2 and 15 are identified as members of the vector and as the receiving ports Because Port 1 is the ingress port which originates the multicast packet as shown in the ackID it is removed from the Multicast Mask The resulting Multicast Vector indicates that the packet should be transmitted to Ports 0 2 and 5...

Page 110: ...he 8 bit destination ID of five and the 16 bit destination ID of five requires two entries in the multicast group table If the destination ID contained in an incoming packet matches any of the eight entries the ingress port sends the packet to the multicast engine for replication The matching table entry contains a list of ports multicast mask to which the multicast engine sends a copy of the pack...

Page 111: ...IO Multicast DestID Configuration Register on page 265 and RapidIO Multicast DestID Association Register on page 266 To execute either of the previous two operations port removal or group deletion the system software must remember what port is associated to which multicast masks and to which multicast mask number the destination ID is bound If the software designer selects not to maintain a state ...

Page 112: ...e operation to associate destination ID 0x1234 with multicast mask 0 Write the value 0x1234_0000 to the RapidIO Multicast DestID Configuration Register on page 265 The individual association operations can be performed in any order Port Participating in Vector 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 4 3 5 6 7 DEST_ID Large Small Multicast Group Number AB CD xx EF 0 1 Operating Mode 4x 1x Power down ...

Page 113: ...his example the state of the multicast masks is unknown and therefore the masks must be cleared before being configured In order to clear the masks the following register accesses are made 1 Remove all egress ports from multicast mask 0 Write the value 0x0000_0040 to the Multicast Mask Configuration Register 2 Remove all ports from multicast mask 1 Write the value 0x0001_0040 to the Multicast Mask...

Page 114: ...igure shows the completed configuration Figure 24 Completed Tables at the End of Configuration Port Participating in Vector F E D C B A 9 8 7 6 5 4 3 2 1 0 0 1 2 4 3 5 6 7 DEST_ID Large Small Multicast Mask Number 12 34 xx 44 0 1 Operating Mode Switch Port Number 4x 1x 1x 0 No 1 Yes 1 0 4x 1x 1x 1 1 1 N A N A 0 4x N A 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Multicast Group Table Multicast ...

Page 115: ...2 Write the value 0x0002_0100 to the Multicast Mask Configuration Register Read the value 0x0002_0101 from the Multicast Mask Configuration Register 3 Verify that port 2 is included in mask 2 Write the value 0x0002_0200 to the Multicast Mask Configuration Register Read the value 0x0002_0201 from the Multicast Mask Configuration Register 4 Verify that port 3 is included in mask 2 Write the value 0x...

Page 116: ...IDT Specific Registers The Tsi578 also has a device specific implementation to configuring the multicast masks This implementation allows the direct writing of configuration information into the multicast group and vector tables a through the RapidIO Multicast Write Mask x Register on page 318 and the RapidIO Multicast Write ID x Register on page 317 The use of these two registers permits the dire...

Page 117: ...her to accept packets when available No one port can monopolize the RR arbiter When a port skips an opportunity to transmit because it carries no packet at the moment the RR arbiter does not compensate for the lost chance and moves to the next port in sequence for an available packet The packets from the RR arbiters are selected by the SP arbiter based solely on their priority Port Participating i...

Page 118: ...ers operate in cut through mode It is possible for the ingress port s link partner to stomp a packet or terminate it due to some other error condition It is also possible for the ingress port to detect a CRC or some other error with the packet To handle these situations the Tsi578 supports stomping of a packet while it is being transferred from ingress port to broadcast buffer When a packet arrive...

Page 119: ... the multicast latency timer expires are discarded A packet copy being transferred from the multicast work queue to the broadcast buffer when the multicast latency timer expires is also discarded Depending on the system latency restrictions on multicast and the frequency with which the maximum latency timer expires discarding packets within the broadcast buffer can be sufficient to allow the syste...

Page 120: ...s issued No other information is latched regarding the packet s that were dropped 5 4 5 Port writes and Multicast Port writes can be multicast to multiple output links depending on the destinationID of the port write Using the multicast feature improves the likelihood of delivery of port writes for link failures 5 5 Port Reset When a port is powered down the port looses configuration information t...

Page 121: ...Notifications on page 133 Interrupt Notifications on page 136 6 1 Overview The Tsi578 has the following ways to notify external devices about events occurring within the switch 1 Generate a RapidIO Port write maintenance message when enabled as described in the RapidIO Interconnect Specification Revision 1 3 2 Assert the INT_b interrupt pin when an enabled interrupt is generated Most events can ge...

Page 122: ...nd port receives a transaction with one of the following errors Unmapped entry in LUT Reserved TT field value for data packet or maintenance packet with a hop count not equal to zero The status of this event is contained in the IMP_SPEC_ERR bit in the RapidIO Port x Error Detect CSR and the ILL_TRANS_ERR bit in the RapidIO Port x Interrupt Status Register RapidIO Yes Yes LUT Parity Error Error Thi...

Page 123: ...n the RapidIO Port x Multicast Event Control Symbol and Reset Control Symbol Interrupt CSR on page 312 as well as the MCS bit in the Global Interrupt Status Register RapidIO Yes No Outbound Queue Threshold Reached Status This event is raised when the outbound queue threshold exceeded counter reaches the counter threshold configured for that port This is used to detect congestion on outbound queues...

Page 124: ...r for link response The Dead Link Timer for a port has expired The Lane Sync Timer for at least one lane of the port has expired The status of this event is contained in the PORT_ERR bit of the RapidIO Port x Error and Status CSR Link request retries with timeout errors also cause the LINK_TO bit in the RapidIO Port x Error Detect CSR to be asserted Link responses with no outstanding ackID cause t...

Page 125: ...no link request is outstanding The status of this event is contained in the PROT_ERR bit of the RapidIO Port x Error Detect CSR on page 294 RapidIO Yes Yes1 Delineation Error Error This event is raised when a RapidIO port receives an unaligned SC or PD symbol or an undefined code group The status of this event is contained in the DELIN_ERR bit of the RapidIO Port x Error Detect CSR on page 294 Rap...

Page 126: ...d in the CS_NOT_ACC bit of the RapidIO Port x Error Detect CSR on page 294 RapidIO Yes Yes1 Packet CRC Error Error This event is raised when a RapidIO port receives a packet with a CRC error The status of this event is contained in the PKT_CRC_ERR bit of the RapidIO Port x Error Detect CSR on page 294 RapidIO Yes Yes1 I2 C Event Status and Error This event is raised when the I2 C block has an inte...

Page 127: ...very tick of the Error Rate Bias Timer The counts do not decrement below 0 This field only tracks transmission errors that have been unmasked in the Port x Error Rate Enable CSR This counter does not monitor queue depths Error Rate recovery ERR_RR This field allows the user to define how far above the Error Rate Threshold Trigger the Error Rate Counter is allowed to count PEAK This field maintains...

Page 128: ...er the method described in this section uses IDT specific functionality and control symbols to clear the errors by forcing a hardware recovery situation through software 6 4 1 Error Stopped States An Input Error stopped state is entered when a RapidIO receiver detects a protocol error When in an Input Error stopped state a port processes control symbols but discards packets An output Error stopped...

Page 129: ...clear error conditions is to create a situation that forces the hardware recovery process to run again This situation is created by sending a control symbol to a link partner that the partner can respond to The control symbol means for software to start the recovery process on the near end of the link and simultaneously start the recovery process on the far end of the link 6 4 2 1 Control Symbol E...

Page 130: ...er sends a Packet not accepted General Error Link Request Input Status control symbol To cause the transmission of the required control symbol write the value 0x40FC8000 to the RapidIO Port x Control Symbol Transmit register 2 The far end link partner the link partner at the far end of the link responds with a Link Request Input Status control symbol The far end link partner also responds with a L...

Page 131: ... any of the illegal transaction maximum retry lookup table parity error or time to live events occur regardless of whether they are enabled or not When most of the errors listed in Table 14 occur they are logged in the RapidIO Port x Error Detect CSR on page 294 If the error is enabled in the RIO Port x Error Rate Enable CSR the error counter is incremented and information about the packet causing...

Page 132: ... received not the packet that was retried Yes Received corrupt control symbol Received a control symbol with a bad CRC value The status of this error is contained in the CS_CRC_ERR bit in the RapidIO Port x Error Detect CSR on page 294 Yes Received acknowledge control symbol with unexpected ackID Received an acknowledge control symbol with an unexpected ackID packet accepted or packet_retry The st...

Page 133: ...et does not have a guaranteed delivery and does not have an associated response see RapidIO Interconnect Specification Revision 1 3 Depending on system design a port write can be sent repeatedly until cleared A programmable timeout counter controls the frequency the port write packets are transmitted defined in the PW_TIMER field of the RapidIO Port Write Timeout Control Register on page 392 When ...

Page 134: ...ountered the error condition and implementation specific information The layout of the port write packet is shown in the Table 15 on page 135 Port writes are sent at the priority defined in the PW_PRIORITY field in the RapidIO Port x Discovery Timer The default value is priority 3 Port write packets are transmitted with a sourceID of 0x00 Port writes are issued with a hop count of 0xFF An image of...

Page 135: ...ts 6 7 and 29 RapidIO Port x Interrupt Status Register on page 326 Correct the error conditions and clear the error sources Clear the PORT_W_PEND bit in the RapidIO Port x Error and Status CSR on page 278 In the case when there are other errors from other ports that have generated a port write bits in the register RapidIO Port Write Outstanding Request Register on page 393 are set Table 15 Port Wr...

Page 136: ... destinationID of the port write packet that is contained in the RapidIO Port Write Target Device ID CSR is also contained in a multicast group the port write will be routed to the multicast engine The multicast engine does not distinguish between port write packets and other types of packets The multicast engine will multicast the port write packet to ports according to the mask associated with d...

Page 137: ...4 SP_CTL_INDEP OUTPUT_DEG bit 7 SP_ERR_STATUS OUTPUT_FAIL bit 6 SP_ERR_STATUS TEA bit 31 SP_INT_STATUS TEA_EN bit 31 SP_CTL_INDEP MCT_TEA bit 13 SP_INT_STATUS MCT_TEA_EN bit 13 SP_CTL_INDEP LINK_INIT_NOTIFICATION bit 14 SP_INT_STATUS LINK_INIT_NOTIFICATION_EN bit 14 SP_CTL_INDEP PORT_ERR bit 29 SP_ERR_STATUS PORT_ERR_EN bit 12 SP_CTL_INDEP LUT_PAR_ERR bit 15 SP_INT_STATUS LUT_PAR_ERR_EN bit 15 SP_...

Page 138: ...is not associated with any port Two functions that are port specific have separate indicator bits to allow for faster handling These functions are Multicast Event Control Symbol reception and reception of a valid reset control symbol sequence Both Multicast Event Control Symbol and Reset Control Symbol interrupts can be cleared with one register write to the status bit in the broadcast address of ...

Page 139: ...ror and Status Register Status Status Bit Further Information Interrupt Enable Interrupt Clearing OUTPUT_DROP RIO Serial Port x Control CSR RIO Port x Error Rate CSR RIO Port x Error Rate Threshold CSR RIO Port x Packet Time to Live CSR RIO Port x Interrupt Status CSR RIO Port x Control Independent CSR for the TEA interrupts There is no specific interrupt status bit for OUTPUT_DROP of packets when...

Page 140: ...Control Independent Register on page 319 controls whether any enabled interrupts are propagated to the Global Interrupt Status Register on page 388 to generate an interrupt If the IRQ_EN bit is disabled no interrupt propagates to the Global Interrupt Status Register on page 388 register from this port The IRQ_EN does not control port write generation Port write generation is controlled by the PW_D...

Page 141: ... slave serial interface that can be used for the following purposes Initializing device registers from an EEPROM after reset Reading and writing external devices on the I2 C bus Reading and writing Tsi578 s internal registers for management purposes by an external I2 C master The I2 C Interface has the following features Operates as a master or slave on the I2 C bus Multi master support Arbitrates...

Page 142: ...or by software configuration Provides mailbox registers for communicating between maintenance software operating on RapidIO based processors and external I2 C masters Supports I2 C operations up to 100 kHz Provides boot time register initialization Supports 1 and 2 byte addressing of the EEPROM selected by power up signal Verifies the number of registers to be loaded is legal before loading regist...

Page 143: ...ansmitted from one device to another across the I2C_SD bus with timing referenced to the I2C_SCLK bus With some exceptions each bus can be driven low to a logic 0 by any device but is pulled high to a logic 1 by an external resistor tied to VDD This creates a wired and configuration where any single device can drive a bus to a logic 0 but a bus rises to a logic 1 only if no devices are driving to ...

Page 144: ...r static signals from outside the block or connect to package pins for board level configuration The I2C_MA pin is a power up configuration pin that is latched during reset On the core side the I2C block connects to the internal device register bus as a slave and master As a slave it enables access to the I2C block registers by a host or processor As a master it enables access to other device regi...

Page 145: ...xternal I2C Device External I2C Device I2C_SD I2C_SCLK Master Interface Digital Filter Digital Filter Boot Load Sequencer Slave Interface Internal Register Bus Master Externally Visible Registers Event Interrupt Control I2 C Buses on Circuit Board External Pull ups BLOCK LOGIC I O BUFFERS Internal Register Bus Slave Internal Register Bus Arbiter chip SDA In SCL In SDA Out SCL Out SDA En SCL En sta...

Page 146: ...r Rd 1 Slave Address Data Read from Device ReadData P R Restart loops to start of slave address sequence Stop ends the transaction bus is idle A Byte A Byte A Byte K A A K A A A A A N I2 C Write Data Protocol I2 C Read Data Protocol Optional A Ack N Nack K Ack or Nack P Stop R Restart Note The I2 C read data protocol section of this figure implies that the peripheral addressing phase has already o...

Page 147: ...n protocol used by memory oriented devices such as EEPROMs involves the master sending one or more bytes of memory address to the slave to position the slave s memory address or peripheral address then the master writes reads data to from the slave Eventually the master ends the transaction with a stop condition at which point the bus is free for other masters to start transactions These I2C maste...

Page 148: ...From I2C_MST_WDATA P S PerAdrMsb PerAdrLsb ReadData 7 Bit SlvAdr Wr 0 Slave Address Peripheral Address Data Read from Device ReadData A A A A A ReadData ReadData N A Arbitration Loss pa_size 2 pa_size 1 size 4 size 3 size 2 size 1 From DEV_ADDR From PADDR To I2C_MST_RDATA Read Transaction WRITE 0 PA_SIZE 0 P S ReadData 7 Bit SlvAdr Rd 1 Slave Address Data Read from Device ReadData A A A ReadData R...

Page 149: ...PROM This example is configured in the context of register writes that must be made during a boot load of the EEPROM 7 4 1 1 Write Example Write 8 bytes to the EEPROM w 1d114 0x0042FFFF load the write data register with the write contents w 1d10c 0xc4000000 load the destination address in EEPROM and go w 1d114 0xFFFFFFFF load the next 4 bytes into the write data register w 1d10c 0xc4000004 load th...

Page 150: ... Enable Register In this case the transaction is not automatically retried and it is up to software to retry if needed 7 4 5 Master Peripheral Addressing Some devices such as EEPROMs require a peripheral address to be specified to set a starting position in their memory or address space for the read or write The Tsi578 supports transactions with 0 1 or 2 bytes of peripheral address Because this is...

Page 151: ...n MA_OK of the I2C Interrupt Enable Register 7 5 Tsi578 as I2 C Slave The Tsi578 can operate as a slave device on the I2C bus An external master device places a transaction on the bus with a device address that matches that programmed in the SLV_ADDR field of the I2 C Slave Configuration Register or matches the fixed SMBus Alert Response address The external master can then read or write to the Ts...

Page 152: ...dress space In addition either the SA_WRITE or SA_READ interrupt status is updated in the I2 C Interrupt Status Register if a read or write to the internal register space was triggered by the access An optional interrupt can also be sent to the Interrupt Controller if enabled in SA_WRITE or SA_READ of the I2 C Interrupt Enable Register The SA_FAIL interrupt indicates the slave transaction encounte...

Page 153: ...re bytes no defined limit Write Transaction Matched to SLV_ADDR Sets SLV_PA Data Written to Peripheral Space P R ReadData ReadData A A ReadData N Read Transaction Setting Peripheral Address Readdress for Read SLV_PA incremented after each byte Address Starting at New SLV_PA Data Read from Peripheral Space S R SLV_PA 7 Bit SlvAddr Wr 0 A A Slave Address Peripheral Matched to SLV_ADDR Address R 7 Bi...

Page 154: ...f 256 bytes from 0x00 to 0xFF that can be directly read and written by an external I2 C master device When an external master sets the peripheral address this sets a pointer viewable in the SLV_PA field of the I2 C Access Status Register maintained in the Tsi578 that determines where bytes read and written by the external master are within the peripheral address space This 256 byte space is mapped...

Page 155: ... R W EXI2C_REG_WDATA Specifies the data to write to the internal register address held in EXI2C_REG_WADDR Side effects When address 0x07 the MSB is written the data in this register is written to the internal register address held in EXI2C_REG_WADDR and the peripheral address is returned to 0x04 the LSB This allows consecutive internal registers to be written in one transaction without resetting t...

Page 156: ...ing mailboxes and on the state of the alert response flag 0x24 0x27 R W EXI2C_ACC_CNTRL Provides control information on how the Tsi578 handles internal register accesses through the EXI2C_REG_RDATA and EXI2C_REG_WDATA registers 0x28 0x7F Read Only Reserved This range does not map to any registers 0x80 0x83 Read Only EXI2C_STAT Returns a summary of the internal status of the Tsi578 0x84 0x87 R W EX...

Page 157: ...egister read operation is completed the data is first loaded into the Externally Visible I2C Internal Read Data Register then returned to the external I2C master byte by byte The Externally Visible I2C Internal Access Control Register controls the internal register read operations and allows the user to specify when and how the register read is performed Likewise the Externally Visible I2C Interna...

Page 158: ... transactions The following conditions pre exist ALERT_FLAG is set in the Externally Visible I2C Slave Access Status Register 1 External device reads Externally Visible I2C Slave Access Status Register LSB only The returned value of 0x01 is the ALERT_FLAG External device must NACK after the first read byte to stop the transfer I2C Sequence S SLVA W PA 0x20 A R SLVA W RD 0x01 N P Following the tran...

Page 159: ...I2 C Slave Access Status Register then does another Alert Response request The ALERT_FLAG is zero all enables were cleared so the alert response address is NACKed I2 C Sequence S SLVA W PA 0x84 A WD 0x00 A WD 0x00 A WD 0x00 A WD 0x00 A R SLVA W PA 0x20 A R SLVA W RD 0x00 N R 0001100 W N P Following the transaction SLV_PA is 0x21 Externally Visible I2 C Enable Register is 0x00000000 and interrupt s...

Page 160: ...stic Timer I2C_BOOT_DIAG_TIMER is 0x8000BBCC reserved fields stay zero and interrupt status SA_OK and SA_WRITE assert An optional interrupt can also be sent to the Interrupt Controller if enabled in the I2C Interrupt Enable Register 7 External device sets up I2C_SCLK Low and Arbitration Timeout Register address 0x1D354 in Externally Visible I2C Internal Read Address Register then reads 3 registers...

Page 161: ...ally Visible I2 C Internal Read Address Register is0x001D354 and interrupt status SA_OK and SA_READ assert An optional interrupt can also be sent to the Interrupt Controller if enabled in SA_OK and SA_READ of I2C Interrupt Enable Register 7 5 9 Resetting the I2 C Slave Interface The I2C slave interface is reset by two conditions chip reset or the detection of a START condition When a chip reset is...

Page 162: ...x registers are discussed further in the following sections EXI2C_MBOX_IN Writes to Mailbox 0100 000111 EXI2C_MBOX_IN EXTERNAL I2 C MASTER Flag Goes Up EXI2C_ACC_STAT IMB_FLAG Host is Interrupted IMB_FULL Host Reads Mailbox Flag Goes Down Polls Status Until Flag Down PROCESSOR HOST EXI2C_MBOX_IN INCOMING MAIL EXI2C_MBOX_OUT Writes to Mailbox 0100 000111 EXI2C_MBOX_OUT EXTERNAL I2 C MASTER Flag Goe...

Page 163: ...xternally Visible I2C Slave Access Status Register which the external I2C master can poll through the slave interface When the flag goes up 1 the external I2 C master reads the outgoing mailbox register through the slave interface Once the Stop condition is seen indicating the external master has completed reading the mailbox the slave interface clears the OMB_FLAG in the status register EXI2C_ACC...

Page 164: ...ocol as a SMBus host device in slave mode 7 7 2 SMBus Protocol Support The Tsi578 master interface functionality supports a subset of the SMBus Protocols see Figure 34 In all cases the Tsi578 masters a transaction to another SMBus device All register and register field references are to the following I2 C master interface registers I2 C Master Configuration Register I2 C Master Control Register I2...

Page 165: ...A_SIZE 0 SIZE 0 WRITE 0 SMBus Write Byte PA_SIZE 1 SIZE 1 DORDER 1 WRITE 1 SMBus Write Word PA_SIZE 1 SIZE 2 DORDER 1 WRITE 1 SMBus Read Byte PA_SIZE 1 SIZE 1 DORDER 1 WRITE 0 SMBus Read Word PA_SIZE 1 SIZE 2 DORDER 1 WRITE 0 SMBus Write Block NB 1 4 bytes PA_SIZE 2 SIZE NB DORDER 1 WRITE 1 SMBus Host Notify Protocol PA_SIZE 1 SIZE 2 DORDER 1 WRITE 1 SlaveAdr SMBus device address set in DEV_ADDR P...

Page 166: ...E see Power up Options in this document This data initializes the Tsi578 s internal registers The boot load sequence occurs only after a full chip reset and follows the steps shown in Figure 36 The boot load sequence is controlled by the contents of the I2C_BOOT_CNTRL register RD0 DevAdr P S ARA A Rd N SMBus Alert Response master interface DEV_ADDR 0001100 PA_SIZE 0 SIZE 1 DORDER 1 WRITE 0 S Start...

Page 167: ...g Info Per Address Select next device Boot Init and Device Detect Set Register Count Peripheral Address Read Register Count from the first 2 bytes of the EEPROM after reset Set Register Info Peripheral Address Read Register Info Write Data into internal register Select Chained Device Read eight 8 byte register count field Chain Check If last register load was to I2C_BOOT_CNTRL and CHAIN bit set go...

Page 168: ...nal low preventing the generation of a STOP or START condition To try to force these devices out of their hung state the Tsi578 allows the I2C_SD signal to stay high and generate 9 clock pulses on the I2C_SCLK signal If no device was hung this should not cause any problems because all devices are looking for a START condition If a device was in the middle of a receiving a byte the remainder of the...

Page 169: ...upt status is updated in the I2C Interrupt Status Register On these boot load status bits the optional interrupt can be forwarded to the Interrupt Controller if enabled in the I2C Interrupt Enable Register If the register count was 0 the boot load is ended successfully and the BL_OK interrupt status is updated An optional interrupt can also be forwarded to the Interrupt Controller if enabled in th...

Page 170: ...egister It may also be necessary to use the BOOT_UNLK field to change the lower 2 bits of the EEPROM address By default the BOOT_UNLK field is not set so if the BOOT_ADDR field is changed the lower 2 bits remain at their previous value This way the power up reset value is not inadvertently lost If as part of the chaining process it is necessary to change those bits such as if the boot load is bein...

Page 171: ...ter Transmit Data Register at internal address 0x1D114 loaded with data value 0x0506_0708 Table 18 Format for Boot Loadable EEPROM PerAdr PerAdr 0 PerAdr 1 PerAdr 2 PerAdr 3 0x0 RegCnt MSB RegCnt LSB 0xFF 0xFF 0x4 0xFF 0xFF 0xFF 0xFF 0x8 RegAdr MSB RegAdr RegAdr RegAdr LSB 0xC RegData MSB RegData RegData RegData LSB 0x10 RegAdr MSB RegAdr RegAdr RegAdr LSB 0x14 RegData MSB RegData RegData RegData ...

Page 172: ...chaining operations The clocking speeds of the master devices Because many of these parameters are outside the control of the Tsi578 the boot time cannot be predicted with complete accuracy Table 20 Sample EEPROM With Chaining PerAdr PerAdr 0 PerAdr 1 PerAdr 2 PerAdr 3 Description 0x0 0x00 0x02 0xFF 0xFF RegCnt 2 must have 0xFFFF at end 0x4 0xFF 0xFF 0xFF 0xFF Must be 0xFFFF_FFFF 0x8 0x00 0x01 0xD...

Page 173: ...time is a design concern the following techniques may accelerate the boot load sequence 1 If the EEPROM supports reading of a large block of data sequentially change PAGE_MODE in I2C Boot Control Register as the first register load Depending on the page size this reduces the number of times the boot load re addresses the device and resets the peripheral address At the limit if the infinite setting...

Page 174: ...ad or write access during slave address phase or peripheral address phase or any write access during the data phase Access aborted STOP generated The I2C_ACC_STAT register indicates where transaction was on error MA_NACK Timeout expired I2C_SCLK Low Byte or Transaction Target device was too slow or some device was interfering with the I2C_SCLK signal Any transfer to or from the Tsi578 Access abort...

Page 175: ... and another device holds the signal to 0 Slave releases I2C_SD and I2C_SCLK goes into wait state SA_FAIL SCOL Register Initialization Loader Errors Failed to find EEPROM Initialization read Read operation retried up to 6 times before aborting If not Ack ed by the 6th try status bits set BL_FAIL BLNOD Size field specifies more than 255 registers to load in 1 byte addressing mode or 8 KB 1 register...

Page 176: ...pt Generation The interrupt status bits are cleared by a write one to clear operation to the Interrupt Status Register provided the interrupt status register has first been read For test purposes bits in the Interrupt Status Register can also be set by a write one to set operation to the I2 C Interrupt Set Register A bit that is set in the Interrupt Status Register is cleared by a write 1 to clear...

Page 177: ...status bit The combined event state becomes the interrupt status bit in the Interrupt Status Register and is then anded with the corresponding enable in the I2C Interrupt Enable Register All the enabled interrupt status bits are then ored together to become the single interrupt signal to the Interrupt Controller The new event and snapshot registers separate events that occurred prior to a read of ...

Page 178: ..._FULL Incoming Mailbox Full IMBW Incoming Mailbox Write Event BL_FAIL Boot Load Fail BLTO Boot Load Timeout Error BLERR Boot Load Error Event BLSZ Boot Load Size Error Event BLNOD Boot Load No Device Event Bit N I2C_INT_STAT Bit N I2C_INT_ENABLE Bit 0 Status Enable Write 1 to bit N in I2C_EVENT to CLEAR AND Read I2C_INT_STAT to copy all asserted OR OR Interrupt Signal to Interrupt Controller AND A...

Page 179: ...t to their monitor for bus idle phase It is up to software to decide how to handle this error Because any operation was aborted without correct termination no Stop it is possible that the external device is left in an invalid state BL_OK Boot Load OK BLOK Boot Load OK Event SA_FAIL Slave Access Failed SCOL Slave Collision Detect Event STRTO Slave Transaction Timeout Event SBTTO Slave Byte Timeout ...

Page 180: ...mplete If an ACK or NACK is successfully received the master continues as if the timeout had not expired If another I2 C master collides with Slave Address the timeout immediately takes effect following the Slave Address bit where the collision took place Byte timeout see I2C Byte Transaction Timeout Register This timeout is disabled on reset It detects a situation where one or more devices are st...

Page 181: ... has not completed in a reasonable time This could occur if the EEPROM was improperly programmed with an infinite chaining loop the bus ownership is held by some other device or some other anomalous situation resulting in any of the time outs above If the boot timeout expires before the normal end of the boot load sequence the master interface reads until the next data byte and drives a Stop condi...

Page 182: ...tion Timeout Master or Slave PerAdr or Data A N R P Wait for Bus Idle S Boot Adr A N W Boot Timeout Master Only Load Regs P Idle Detect EEPROM Reset Chain Load Regs START PerAdr P From SCL sampled low to SCL sampled high From start of master operation to slave address acknowledge From start restart to next Ack Nack From Ack Nack to next Ack Nack From Ack Nack to Stop Restart From Start Condition t...

Page 183: ...re not guaranteed to conform to the I2C Specification because of the absence of Schmitt triggers on the input of the I2C_SD and I2C_SCLK signals and the absence of slope controlled outputs for the I2C_SD and I2C_SCLK signals It is up to the board or system designer to decide on the applicability of operation at speeds above 100 kHz Bus timing does not normally change during a transaction even if t...

Page 184: ...rams I2C_SCLK START RESTART Condition Setup I2C_SD Hold I2C_SCLK STOP Condition Setup I2C_SD I2C_SCLK I2C_SD Data Bit or Ack Nack Setup I2C_SD Hold SCL Minimum Low I2C_SCLK High Low Minimum High Nominal Low Nominal High I2C_SCLK Idle Detect Idle Timeout RESET Idle Not Idle Master Only Master Only Master or Slave Master Only Post Reset ...

Page 185: ...ere is no separate Stop Hold parameter as the only valid condition following a Stop would be a Start therefore the Start Setup fulfills the same use as a Stop Hold or Stop to Start buffer time This parameter is used by the Tsi578 as a master when generating the Stop condition If the I2C_SCLK signal was prematurely pulled low 0 by an external master or slave this would be seen as a collision event ...

Page 186: ...n the low period than the nominal low period the high period nominal timer will likely expire early and the minimum high period timer will control the high period when the clock is finally released 7 13 5 Idle Detect Period This is a master only parameter that is used in two cases First upon exit from reset it is unknown if another master is active The Idle Detect timeout determines if the I2C_SCL...

Page 187: ...ified for a single switch Performance for larger systems can be computed from this data 8 1 1 Throughput Throughput for packets is a measurement of the amount of packet data that can be transferred in a given amount of time It can be presented in different forms Percentage of a link s bandwidth for example 56 of a 1x 3 125 Gbaud Number of packets of a given size per unit time for example 3000 44 b...

Page 188: ...tency figure that each packet experiences difficult because the amount of contention that a packet experiences can vary widely As such these scenarios are not covered in this manual Figure 41 Latency Illustration In the Tsi578 packets experience packet latency variations caused by the asynchronous ability of the device Packets can experience an extra one or two clock cycles of delay over the minim...

Page 189: ...erformance Statistics Counter 0 and 1 Control Register on page 332 RapidIO Port x Performance Statistics Counter 0 Register on page 344 Any of the performance statistics counter registers can be configured to count the number of packets sent or received by a RapidIO link Number of packets for each priority 0 1 2 and 3 RapidIO Port x Performance Statistics Counter 0 and 1 Control Register on page 3...

Page 190: ...cket size is COUNTER A divided by the value in COUNTER B 3 Utilization packet rate packet size max capacity Utilization is calculated using parameter 1 and parameter 2 above These values are derived from the number of packets and the number of 32 bit words on each interface The calculations of the packet rate packet size and utilization are completed externally 8 2 2 Throughput The count of packet...

Page 191: ... Register on page 352 RapidIO Port x Transmitter Output Queue Congestion Period Register on page 354 The registers in the inbound direction are RapidIO Port x Receiver Input Queue Depth Threshold Register on page 355 RapidIO Port x Receiver Input Queue Congestion Status Register on page 357 RapidIO Port x Receiver Input Queue Congestion Period Register on page 359 8 2 4 Congestion Detection A pack...

Page 192: ...rt the lower the throughput the higher the average latency and the greater the spread between minimum and maximum latency For ports operating in 1x mode performance measurements are specified for operation at 3 125 Gbaud For ports operating in 4x mode performance measurements are specified for operation at 3 125 Gbaud per lane All performance measurements assume that the ISF is operating at its ma...

Page 193: ...apidIO egress buffer management For high priority configurations watermark settings should be used which deliver maximal throughput for the highest priority packets For ingress and egress ports a maximum of 6 priority 2 packets can be accepted a maximum of 4 priority 1 packets can be accepted and a maximum of 2 priority 0 packets are accepted 8 4 Port to Port Performance Characteristics The most i...

Page 194: ...aintain the line rates This means there is no retry of packets at the ingress ports and no bubbles will appear in the egress packet stream except for the idle sequence insertion every 5000 code groups as required by the RapidIO Interconnect Specification Revision 1 3 This is true for any payload size and different priorities When the ingress line rate exceeds that of the egress port a retry occurs...

Page 195: ...mance Under a non congested one port to many ports packet traffic scenario when the ingress line rate is the same as the total egress line rates for example one 4x mode 3 125 Gbaud ingress port splitting to four 1x mode 3 125 Gbaud egress port the ingress and egress always maintain line rates This means there is no retry of packets in ingress and no bubble packet in the egress packet streams excep...

Page 196: ...ast engine retries occur at the ingress port In this situation the egress port maintains its line rate For example when an egress port is set to 4x mode 2 5 Gbaud while the multicast engine is receiving a single or aggregated input data at maximum 10Gbit s retries happen at the ingress port s However the egress port still maintains its line rate with no bubble inserted in that packet stream 8 5 Co...

Page 197: ...ter by 1 Yes No Leak Rate timer expire Congestion Period timer expire Yes Yes No No Increment Congestion Period Counter by 1 Yes No Clear Congestion Period Counter Congestion Period Counter read by software Decrement Congestion Counter by 1 Congestion Counter Congestion Threshold Yes No Set OUTB_DEPTH interrupt Yes No Yes No Reset Error Rate Bias timer Decrement Congestion Counter Congestion Count...

Page 198: ... CONG_PERIOD_CTR This is the Congestion Period Counter This counter is incremented at every tick whose period is set by the CONG_PERIOD field when the Congestion Counter is greater than zero This register is keeps a running count and is only cleared with a register read RapidIO Port x Transmitter Output Queue Congestion Status Register on page 352 This register contains two fields the Congestion C...

Page 199: ...e status Both interrupts are located in the RapidIO Port x Interrupt Status Register on page 326 for the port The Congestion Counter and Congestion Period Counter fields must be polled in order to determine the current congestion trend if waiting for the interrupts to occur is insufficient warning that the buffers in the switch have become congested Also by tracking the Congestion Counter value an...

Page 200: ...tion Period Count value see RapidIO Port x Transmitter Output Queue Depth Threshold Register on page 350 and the Congestion Counter value see RapidIO Port x Transmitter Output Queue Congestion Status Register on page 352 In this example the value of the Congestion Threshold has been set to eight see RapidIO Port x Transmitter Output Queue Congestion Status Register on page 352 When the Congestion ...

Page 201: ...ere are five standard pins associated with the interface TMS TCK TDI TDO and TRST_b which allow full control of the internal TAP Test Access Port controller The JTAG Interface has the following features Contains a 5 pin Test Access Port TAP controller with support for the following registers Instruction register IR Boundary scan register Bypass register Device ID register User test data register D...

Page 202: ...wing down the normal traffic in the device or during initialization A user defined command is used to enable the read and write capabilities of the interface The command is in the IEEE 1149 1 Instruction Register IR in the Tsi578 IEEE Register Access Command IRAC 9 3 1 Format The format used to access the registers is shown in Figure 44 and Figure 45 The address shown in the figure is the RapidIO ...

Page 203: ...hat are being shifted out as the first two bits shifted out 5 Go back to step two to perform another write 9 3 3 Read Access to Registers from the JTAG Interface The following steps are required in order to read a register through the JTAG interface 1 Move to the Tap controller Shift IR state and program the instruction register with IRAC instruction This step is optional if the instruction regist...

Page 204: ...9 JTAG Interface JTAG Register Access Details 204 Tsi578 User Manual June 6 2016 Integrated Device Technology www idt com ...

Page 205: ...mation Clocks on page 205 Resets on page 209 Power up Options on page 212 10 1 Clocks The Tsi578 has three input clocks S_CLK_p n P_CLK and I2C_SCLK that are used to produce the Tsi578 s internal clock domains In addition to these reference clocks each RapidIO ingress port contains independent receive clock domains one for each lane The receive clock is extracted from the 8B 10B encoding on each l...

Page 206: ... one RXCLKA or two RXCLKA B clocks are recovered On the transmit side the clock TX_CLK is derived from the SerDes An extra clock SYS_CLK is also sourced from the SerDes to the MAC The S_CLK_p n signal is also an input to the Switch Fabric and internal registers Figure 46 Tsi578 Clocking Architecture I 2 C_SCLK pin pin pin P_CLK S_CLK_P N I 2 C Internal registers and bus Serial Port 0 clk gen Seria...

Page 207: ... 1 3 Reference clocks The two reference clocks are described in Table 26 Tip For information on configuring the clock rate of RapidIO ports refer to Clocking on page 70 Table 26 Tsi578 Input Reference Clocks Clock Input Pin Type Frequencya a For more electrical characteristics of the clocks please refer to the Tsi578 Hardware Manual Clock Domains S_CLK_p n Differential 156 25MHzb b For more inform...

Page 208: ...o P_CLK Programming on page 493 100 MHz This clock domain includes all internal registers within each of the internal blocks as well as the bus that performs the register accesses The domain uses the input P_CLK directly Internal Switching Fabric ISF Domain S_CLK_p n 156 25 MHz This clock domain includes the switching matrix of the ISF the Multicast blocks and the portion of each block that commun...

Page 209: ...ible for performing automatic reads from an externally attached EEPROM device in order to load the initial configuration of the device For more details refer to I2C Interface on page 141 10 2 1 2 HARD_RST_b Reset The HARD_RST_b signal is an external system reset input signal and causes a general reset of the Tsi578 all blocks are reset within the device HARD_RST_b is an active low signal with asyn...

Page 210: ...ation of the self reset which is at least four P_CLK clock cycles If the SELF_RST field is not set an interrupt signal is asserted if RCS_INT_EN is also set in the RapidIO Port x Mode CSR on page 310 System Control of Resets Self reset of the Tsi578 may not be sufficient in systems which require other components to be reset at the same time as the Tsi578 The Tsi578 supports system control of reset...

Page 211: ... device is dropped and any traffic still in flight to the peer device is dropped 4 Use the RapidIO Serial Port x Link Maintenance Request CSR on page 273 to transmit four reset control symbols in a row 5 Write 0 to the OUTBOUND field of the RapidIO Serial Port x Local ackID Status CSR on page 276 10 2 4 JTAG Reset The JTAG TAP controller s reset is independent of the Tsi578 functional resets For b...

Page 212: ...ower down SPn_PWRDN mode selection SPn_MODESEL lane swap SP_RX_SWAP and SP_TX_SWAP and I2 C pins I2c_DISABLE I2C_MA I2C_SA 1 0 I2C_SEL 10 3 1 Power up Option Signals Power up options are latched at reset for initializing the Tsi578 The power up option pins are listed in Table 28 All power up option pins have to remain stable for 10 P_CLK cycles after HW_RST_b is de asserted in order to be sampled ...

Page 213: ...ut capability of this pin is only used in test mode SP n _PWRDN Port n Transmit and Receive Power Down Control This signal controls the state of Port n and Port n 1 The PWRDN controls the state of all four lanes A B C D of SerDes Macro 0 Port n Powered Up Port n 1 controlled by SP n 1 _PWRDN 1 Port n Powered Down Port n 1 Powered Down Override SP n _PWRDN using PWDN_X4 field in the SRIO MAC x Digi...

Page 214: ... when driven low single byte peripheral address is assumed I2C_SA 1 0 I2 C Slave Address pins The values on these two pins represent the values for the lower 2 bits of the 7 bit address of Tsi578 when acting as an I2 C slave I2C_SEL I2 C Pin Select Together with the I2C_SA 1 0 pins Tsi578 determines the lower 2 bits of the 7 bit address of the EEPROM address it boots from When asserted the I2C_SA ...

Page 215: ...ffix _p are the positive half of a differential pair Signals with the suffix _n are the negative half of a differential pair Signals with the suffix _b are active low Signals are classified according to the types defined in Table 29 Table 29 Signal Types Pin Type Definition I Input O Output I O Input Output OD Open Drain SRIO Differential driver receiver defined by RapidIO Interconnect Specificati...

Page 216: ...kup tables for ingress RapidIO ports and in numerous register configuration fields Core Power Core supply Core Ground Ground for core logic I O Power I O supply N C No connect These signals must be left unconnected Table 30 Tsi578 Port Numbering Port Number RapidIO Port Mode 0 Serial Port 0 SP0 1x or 4x 1 Serial Port 1 SP1 1x 2 Serial Port 2 SP2 1x or 4x 3 Serial Port 3 SP3 1x 4 Serial Port 4 SP4 ...

Page 217: ...ing 217 Tsi578 User Manual June 6 2016 Integrated Device Technology www idt com 13 Serial Port 13 SP13 1x 14 Serial Port 14 SP14 1x or 4x 15 Serial Port 15 SP15 1x Table 30 Tsi578 Port Numbering Port Number RapidIO Port Mode ...

Page 218: ...ST_b I2C_SCLK I2C_SD 1 1 HARD_RST_b SW_RST_b 1 INT_b Reset 2 RefClks S_CLK_ p n 1 P_CLK VSS VDD Logic Pwr Gnd VSS_IO Port Config 2 Interrupt VDD_IO IO Pwr Gnd SP0 2 4 14 VDD 1 I2C_DISABLE SP10 SP12 SP14_T A B C D _ p n 8 Ports 14 15 SP_VDD SP0_T A B C D _ p n SP0_R A B C D _ p n SP0_REXT 8 8 SP0_MODESEL 1 1 SP1_PWRDN 1 SP0_AVDD 1 SP14_R A B C D _ p n SP14_REXT 8 SP14_MODESEL SP14_PWRDN 1 1 1 SP15_...

Page 219: ...l Non inverting Transmit Data output 4x mode Port n 1 Lane B Differential Non inverting Transmit Data output 1x mode No termination required SP n _TB_n O SRIO Port n Lane B Differential Inverting Transmit Data output 4x mode Port n 1 Lane B Differential Inverting Transmit Data output 1x mode No termination required SP n _TC_p O SRIO Port n Lane C Differential Non inverting Transmit Data output 4x ...

Page 220: ...D_p I SRIO Port n Lane D Differential Non inverting Receive Data input 4x mode DC blocking capacitor of 0 1uF in series SP n _RD_n I SRIO Port n Lane D Differential Inverting Receive Data input 4x mode DC blocking capacitor of 0 1uF in series Serial Port Configuration SP n _REXT Analog Used to connect a resistor to VSS to provide a reference current for the driver and equalization circuits Must be...

Page 221: ... configuration Either a 10K pull up to VDD_IO or a 10K pull down to VSS_IO Internal pull up can be used for logic 1 SP n 1 _PWRDN I O LVTTL PU Port n 1 Transmit and Receive Power Down Control This signal controls the state of Port n 1 Note that Port n 1 is never used when 4x mode is selected for a Serial Rapid I O MAC and it must be powered down 0 Port n 1 Powered Up 1 Port n 1 Powered Down Overri...

Page 222: ...der to be sampled correctly These signals are ignored after reset and software is able to over ride the port frequency setting in the SRIO MAC x Digital Loopback and Clock Selection Register on page 377 The SP_IO_SPEED 1 0 setting is equal to the IO_SPEED field in the SRIO MAC x Clock Selection Register Output capability of this pin is only used in test mode Pin must be tied off according to the r...

Page 223: ..._SWAP I LVTTL PD Configures the order of 4x transmit lanes on serial ports 0 2 4 6 14 0 A B C D 1 D C B A Must remain stable for 10 P_CLK cycles after HARD_RST_b is de asserted in order to be sampled correctly This signal is ignored after reset Note Ports that require the use of lane swapping for ease of routing only function as 4x mode ports The re configuration of a swapped port to dual 1x mode ...

Page 224: ...a RapidIO link If self reset is not selected this pin remains asserted until the reset request is cleared from the status registers If self reset is selected this pin remains asserted until the self reset is complete If the Tsi578 is reset from the HARD_RST_b pin this pin is de asserted and remains de asserted after HARD_RST_b is released For more information see Resets Note SW_RST_b is the only e...

Page 225: ... signal does not control the slave accessibility of the interface This signal is ignored after reset No termination required Pull up to VDD_IO through a 10K resistor if I2 C loading is not required I2C_MA I LVTTL PU I2 C Multibyte Address When driven high I2 C module expects multi byte peripheral addressing otherwise when driven low single byte peripheral address is assumed Must remain stable for ...

Page 226: ...Output No connect if JTAG is not used Pull up to VDD_IO through a 10K resistor if used TMS I LVTTL PU IEEE 1149 1 1149 6 Test Access Port Test Mode Select Pull up to VDD_IO through a 10K resistor if not used TRST_b I LVTTL PU IEEE 1149 1 1149 6 Test Access Port TAP Reset Input This input must be asserted during the assertion of HARD RST_b Afterwards it can be left in either state Combine the HARD_...

Page 227: ... Manual for more information Common Supply VDD_IO Common 3 3V supply for LVTTL I O Refer to decoupling recommendations in the Tsi578 Hardware Manual for more information VSS Common ground returns for digital logic Refer to decoupling recommendations in the Tsi578 Hardware Manual for more information VDD Common 1 2V supply for digital logic Refer to decoupling recommendations in the Tsi578 Hardware...

Page 228: ...11 Signals Pinlist and Ballmap 228 Tsi578 User Manual June 6 2016 Integrated Device Technology www idt com ...

Page 229: ...Registers on page 380 Utility Unit Registers on page 388 Multicast Registers on page 395 SerDes Per Lane Register on page 402 12 1 Overview The application defined Tsi578 registers receive initial values during power on initialization through the I2 C Interface and external serial EEPROM all undefined registers read 0 and a write is ignored The Tsi578 registers use direct addressing of 32 bit regi...

Page 230: ...2 8 to 13 2 a read modify write operation must be performed for register reserved fields that have an undefined reset value Other reserved fields should always be written as 0 unless otherwise noted Table 33 shows the defined register access types Table 33 Register Access Types Abbreviation Description R Read Only Note R registers are not read write during the I2 C boot unless it specified in the ...

Page 231: ...ese registers In the first notation a lower case letter such as x is used as a wildcard character For example Sx_DESTID refers to S0_DESTID S1_DESTID S2_DESTID and so on The odd ports are unavailable when the even port is in 4x mode Table 34 Port Numbering Port Number RapidIO Port Mode 0 Serial Port 0 SP0 1x or 4x 1 Serial Port 1 SP1 1x 2 Serial Port 2 SP2 1x or 4x 3 Serial Port 3 SP3 1x 4 Serial ...

Page 232: ...ID refers to registers SBC_DESTID S0_DESTID S1_DESTID and S2_DESTID Generally the instance number refers to a RapidIO port number The special instance BC broadcast refers to a register that when written simultaneously affects all powered up ports and that when read returns a value from port number 0 Port 0 should not be powered down Refer to Special Conditions for Port 0 Power Down on page 73 for ...

Page 233: ... Extension Registers on page 285 0x01000 0x0143C Reserved 0x014C0 0x0FFFF IDT Specific RapidIO Registers on page 307 and Serial Port Electrical Layer Registers 0x10000 0x14FFC Reserved 0x15000 0x1A9FC Internal Switching Fabric ISF Registers on page 380 0x1AA00 0x1AAFC Reserved 0x1AB00 0x1ABFC Utility Unit Registers on page 388 0x1AC00 0x1ACFC Reserved 0x1AD00 0x1AFFC Fabric Arbitration Registers 0...

Page 234: ...tch Multicast Support CAR on page 255 00034 RIO_LUT_SIZE RapidIO Route LUT Size CAR on page 256 00038 RIO_SW_MC_INFO RapidIO Switch Multicast Information CAR on page 257 0003C 00064 Reserved 00068 RIO_HOST_BASE_ID_LOCK RapidIO Host Base Device ID Lock CSR on page 258 0006C RIO_COMP_TAG RapidIO Component Tag CSR on page 259 00070 RIO_ROUTE_CFG_DESTID RapidIO Route Configuration DestID CSR on page 2...

Page 235: ...L RapidIO Switch Port General Control CSR on page 272 Serial Port 0 Registers Offset 0x140 0x15C 00140 SP0_LM_REQ RapidIO Serial Port x Link Maintenance Request CSR on page 273 00144 SP0_LM_RESP RapidIO Serial Port x Link Maintenance Response CSR on page 275 00148 SP0_ACKID_STAT RapidIO Serial Port x Local ackID Status CSR on page 276 0014C 00154 Reserved 00158 SP0_ERR_STATUS RapidIO Port x Error ...

Page 236: ...ort 15 340 FFC Tsi578 Reserved RapidIO Error Management Extensions General Error Management Registers 01000 RIO_ERR_RPT_BH RapidIO Error Reporting Block Header on page 287 01004 Reserved 01008 RIO_LOG_ERR_DET RapidIO Logical and Transport Layer Error Detect CSR on page 288 0100C RIO_LOG_ERR_DET_EN RapidIO Logical and Transport Layer Error Enable CSR on page 289 01014 RIO_LOG_ERR_ADDR RapidIO Logic...

Page 237: ...CSR and Debug 0 on page 299 0104C SP0_ERR_ATTR_CAPT_0_DBG1 RapidIO Port x Packet and Control Symbol Error Capture CSR 0 and Debug 1 on page 301 01050 SP0_ERR_ATTR_CAPT_1_DBG2 RapidIO Port x Packet Error Capture CSR 1 and Debug 2 on page 302 01054 SP0_ERR_ATTR_CAPT_2_DBG3 RapidIO Port x Packet Error Capture CSR 2 and Debug 3 on page 302 01058 SP0_ERR_ATTR_CAPT_3_DBG4 RapidIO Port x Packet Error Cap...

Page 238: ... Tsi578 Reserved IDT Specific RapidIO Registers Broadcast Registers Offset 10000 10FFC Writing these registers affects all ports Read data comes from port SP0 10000 SPBC_DISCOVERY_ TIMER RapidIO Port x Discovery Timer on page 309 10004 SPBC_MODE RapidIO Port x Mode CSR on page 310 10008 SPBC_CS_INT_STATUS RapidIO Port x Multicast Event Control Symbol and Reset Control Symbol Interrupt CSR on page ...

Page 239: ... port specific operation 11000 110FC Serial Port 0 Same set of registers as Broadcast Registers offset 10000 100FC 11100 111FC Serial Port 1 11200 112FC Serial Port 2 11300 113FC Serial Port 3 11400 114FC Serial Port 4 11500 115FC Serial Port 5 11600 116FC Serial Port 6 11700 117FC Serial Port 7 11800 118FC Serial Port 8 11900 119FC Serial Port 9 11A00 11AFC Serial Port 10 11B00 11BFC Serial Port ...

Page 240: ...28 SP0_PSC4n5_CTRL RapidIO Port x Performance Statistics Counter 4 and 5 Control Register on page 340 1302C 1303C Reserved 13040 SP0_PSC0 RapidIO Port x Performance Statistics Counter 0 Register on page 344 13044 SP0_PSC1 RapidIO Port x Performance Statistics Counter 1 Register on page 345 13048 SP0_PSC2 RapidIO Port x Performance Statistics Counter 2 Register on page 346 1304C SP0_PSC3 RapidIO Po...

Page 241: ... x SerDes Configuration Global on page 372 130C8 SMAC0_DLOOP_CLK_SEL SRIO MAC x Digital Loopback and Clock Selection Register on page 377 130CC Reserved 130D0 MCES_PIN_CTRL MCES Pin Control Register on page 394 130D4 130FC Reserved 13100 131AC Serial Port 1 Same set of registers as for SP0 offsets 0x13000 0x130AC The registers at offsets 0x130B0 0x130FC are excluded 13200 132FC Serial Port 2 All r...

Page 242: ...00 13FAC Serial Port 15 Same set of registers as for SP0 offsets 0x13000 0x130AC The registers at offsets 0x130B0 0x130FC are excluded Fabric Global Interrupt Registers 1AA00 FAB_CTL Fabric Control Register on page 380 1AA04 FAB_INT_STAT Fabric Interrupt Status Register on page 382 1AA08 RIO_MC_LAT_ERR RapidIO Broadcast Buffer Maximum Latency Expired Error Register on page 384 1AA0C RIO_MC_LAT_ERR...

Page 243: ...icast Packet Prio 3 Register on page 401 1B020 1B0FC Reserved 1B100 1B1FC Serial Port 1 Same set of registers as Serial Port 0 offset 1B000 1B0FC 1B200 1B2FC Serial Port 2 1B300 1B3FC Serial Port 3 1B400 1B4FC Serial Port 4 1B500 1B5FC Serial Port 5 1B600 1B6FC Serial Port 6 1B700 1B7FC Serial Port 7 1B800 1B8FC Serial Port 8 1B900 1B9FC Serial Port 9 1BA00 1BAFC Serial Port 10 1BB00 1BBFC Serial ...

Page 244: ...064 1E06C Reserved 1E070 SMAC 0 2 4 6 8 10 12 14 _PM_CT L_1 SerDes Lane 1 Pattern Matcher Control Register on page 408 1E074 SMAC 0 2 4 6 8 10 12 14 _FP_VAL _1 SerDes Lane 1 Frequency and Phase Value Register on page 412 1E078 1E07C Reserved 1E0A0 SMAC 0 2 4 6 8 10 12 14 _PG_CT L_2 SerDes Lane 2 Pattern Generator Control Register on page 405 1E0A4 1E0AC Reserved 1E0B0 SMAC 0 2 4 6 8 10 12 14 _PM_C...

Page 245: ...this section are defined in the RapidIO Interconnect Specification Revision 1 3 These registers are reset by the HARD_RST_b reset input signal as well as when the Tsi578 performs a self reset The registers within a port are also reset by a Port Reset For more information on Tsi578 reset implementation and behavior see Clocks Resets and Power up Options on page 205 It is possible to override reset ...

Page 246: ...Register name RIO_DEV_ID Reset value 0x0578_000D Register offset 00000 Bits 0 1 2 3 4 5 6 7 00 7 DEV_ID 07 15 DEV_ID 16 23 DEV_VEN_ID 24 31 DEV_VEN_ID Bits Name Description Type Reset Value 0 15 DEV_ID Device Identifier This field contains the IDT assigned part number of the device R 0x0578 16 31 DEV_VEN_ID Device Vendor Identifier This field identifies IDT as the vendor that manufactured the devi...

Page 247: ...lue 0x0000_0010 Register offset 00004 Bits 0 1 2 3 4 5 6 7 00 07 Reserved 08 15 Reserved 16 23 Reserved 24 31 SILICON_REV METAL_REV Bits Name Description Type Reset Value 0 23 Reserved N A R 0 24 27 SILICON_REV Indicates the version of silicon used in the device This value may change with different silicon revisions of the device R 0b0001 28 31 METAL_REV Indicates the version of the metal layers f...

Page 248: ...IO_ASBLY_ID Reset value 0x0001_000D Register offset 00008 Bits 0 1 2 3 4 5 6 7 00 07 ASBLY_ID 08 15 ASBLY_ID 16 23 ASBLY_VEN_ID 24 31 ASBLY_VEN_ID Bits Name Description Type Reset Value 0 15 ASBLY_ID Assembly ID Identifies the type of assembly from the vendor specified by the ASBLY_VEN_ID field I2 C load from EEPROM R 0x0001 16 31 ASBLY_VEN_ID Assembly Vendor ID Identifies the vendor that manufact...

Page 249: ...ASBLY_INFO Reset value 0x0000_0100 Register offset 0000C Bits 0 1 2 3 4 5 6 7 00 07 ASBLY_REV 08 15 ASBLY_REV 16 23 EXT_FEAT_PTR 24 31 EXT_FEAT_PTR Bits Name Description Type Reset Value 0 15 ASBLY_REV Assembly Revision Level I2 C load from EEPROM R 0x0000 16 31 EXT_FEAT_PTR Extended Features Pointer This is the pointer to the first entry in the extended features list In the Tsi578 it points to th...

Page 250: ... reads and writes 1 The processing element has physically addressable local address space and can be accessed as an endpoint through non maintenance that is NREAD and NWRITE transactions R 0 2 PROC Processor 0 Not a processor 1 Physically contains a local processor or similar device that executes code A device that bridges to an interface that connects to a processor does not count see bit 0 R 0 3...

Page 251: ...iguration of the ingress port s lookup table This bit is not used in the control of any functionality in the Tsi578 0 Device supports 8 bit destination IDs only 1 Device supports 8 bit and 16 bit destination IDs R 1 28 EXT_FEA Extended Features Pointer is valid Pointer to the first entry in the extended features list In the Tsi578 this pointer points to the RapidIO Physical Layer Registers on page...

Page 252: ... Reserved 16 23 PORT_TOTAL 24 31 PORT_NUM Bits Name Description Type Reset Value 0 15 Reserved N A R 0x0000 16 23 PORT_TOTAL Port Total The total number of RapidIO ports on the device Note that the number of ports reported in this register assumes that all RapidIO ports are in 1x mode For example when a port is configured for 4x mode it consumes two ports from this reported number R 0x10 24 31 POR...

Page 253: ...8 15 Reserved IMPLEMENT_DEF 16 23 READ WRITE STRM_WR WR_RES D_MSG DBELL Reserved A_TSWAP 24 31 A_INC A_DEC A_SET A_CLEAR Reserved PORT_WR Reserved Bits Name Description Type Reset Value 0 13 Reserved N A R 0 14 15 IMPLEMENT_ DEF Implementation defined R 0 16 READ Read operation supported R 0 17 WRITE Write operation supported R 0 18 STRM_WR Streaming write operation supported R 0 19 WR_RES Write w...

Page 254: ...isters 254 Tsi578 User Manual June 6 2016 Integrated Device Technology www idt com 29 PORT_WR Port write operation The RapidIO ports support port write generation to report errors R 1 30 31 Reserved Implementation defined R 0 Continued Bits Name Description Type Reset Value ...

Page 255: ...does not support the simple programming model for more information see the RapidIO Multicast Mask Configuration Register on page 263 Register name RIO_PE_MC_FEAT Reset value 0x0000_0000 Register offset 00030 Bits 0 1 2 3 4 5 6 7 00 07 SIMP Reserved 08 15 Reserved 16 23 Reserved 24 31 Reserved Bits Name Description Type Reset Value 0 SIMP Simple Programming 0 Does not support simple block programmi...

Page 256: ...tination IDs with limited capabilities Register name RIO_LUT_SIZE Reset value 0x0000_01FF Register offset 0034 Bits 0 1 2 3 4 5 6 7 00 07 Reserved 08 15 Reserved 16 23 LUT_SIZE 0 7 24 31 LUT_SIZE 8 15 Bits Name Description Type Reset Value 0 15 Reserved Reserved R 0 16 31 LUT_SIZE Lookup Table Size Identifies the destination IDs that can be used to route packets through the switch Destination IDs ...

Page 257: ...sociation between a destinationID and a multicast mask 1 Block association is supported Not implemented in the Tsi578 R 0 1 ASSOC_SCOPE Defines the capabilities of a switch to associate a destination ID with a multicast mask on a per inbound port basis 0 A destination ID when associated with a multicast mask associates with the mask regardless of which switch inbound port received the packet 1 Per...

Page 258: ...FFFF Note that writing 0xFFFF to this register does not result in a lock being obtained After writing the HOST_BASE_ID field a processing element must read the Host Base Device ID Lock CSR to verify that it owns the lock before attempting to initialize this processing element Register name RIO_HOST_BASE_ID_LOCK Reset value 0x0000_FFFF Register offset 00068 Bits 0 1 2 3 4 5 6 7 00 07 Reserved 08 15...

Page 259: ...idIO Component Tag CSR This register is written by software It is used for labeling and identifying the port write transactions to the host Register name RIO_COMP_TAG Reset value 0x0000_0000 Register offset 0006C Bits 0 1 2 3 4 5 6 7 00 07 CTAG 0 7 08 15 CTAG 8 15 16 23 CTAG 16 23 24 31 CTAG 24 31 Bits Name Description Type Reset Value 00 31 CTAG Component Tag R W 0 ...

Page 260: ...e per port configuration registers and they include an auto increment bit to increment the contents of SPx_ROUTE_CFG_DESTID after a read or write operation For details on how to configure the LUTs using this register refer to Lookup Tables on page 37 Register name RIO_ROUTE_CFG_DESTID Reset value 0x0000_0000 Register offset 0070 Bits 0 1 2 3 4 5 6 7 00 07 Reserved 08 15 Reserved 16 23 LRG_CFG_DEST...

Page 261: ...tion registers and they include an auto increment bit to increment the contents of SPx_ROUTE_CFG_DESTID after a read or write operation For details on how to configure the LUTs using this register refer to Lookup Tables on page 37 Register name RIO_ROUTE_CFG_PORT Reset value Undefined Register offset 0074 Bits 0 1 2 3 4 5 6 7 00 07 Reserved 08 15 Reserved 16 23 Reserved 24 31 PORT Bits Name Descri...

Page 262: ...0078 Bits 0 1 2 3 4 5 6 7 00 07 Reserved 08 15 Reserved 16 23 Reserved 24 31 DEFAULT_PORT Bits Name Description Type Reset Value 0 23 Reserved Reserved R 0 24 31 DEFAULT_ PORT Default Output Port All transactions with destination IDs not defined in the LUT are routed to this pre defined default output port DEFAULT_PORT can be set to unmapped with a value greater than PORT_TOTAL in the RIO_SW_PORT ...

Page 263: ...NUM 7 0 24 31 Reserved MASK_CMD Reserved PORT_ PRESENT Bits Name Description Type Reset Value 0 15 MC_MASK_NUM Specifies the multicast mask 0 7 which is to be modified when this register is written with the MASK_CMD field set to Add or Delete 0x0000 to 0x0007 Specifies the Multicast mask which is to be queried for the presence of a port by a subsequent read of this register when this register is w...

Page 264: ... Multicast Mask 010 Delete the given Egress_Port_Number from the specified Multicast Mask 011 Reserved 100 Delete all egress ports from the specified Multicast Mask 101 Add all egress ports to the specified Multicast Mask 110 Reserved 111 Reserved When the register is read this field returns the contents that were previously written R W 0 28 30 Reserved N A R 0 31 PORT_ PRESENT Port Present 0 Port...

Page 265: ...n IDs to ranges of masks is not supported Register name RIO_MC_DESTID_CFG Reset value 0x0000_0000 Register offset 00084 Bits 0 1 2 3 4 5 6 7 00 07 DESTID_BASE_LT 7 0 08 15 DESTID_BASE 7 0 16 23 MASK_NUM_BASE 15 8 24 31 MASK_NUM_BASE 7 0 Bits Name Description Type Reset Value 0 7 DESTID_BASE_L T The most significant 8 bits of a 16 bit destination ID to be associated with the mask MASK_NUM_BASE This...

Page 266: ...multicast mask or which association must be removed Register name RIO_MC_DESTID_ASSOC Reset value 0x0000_0000 Register offset 00088 Bits 0 1 2 3 4 5 6 7 00 07 ASSOC_BLK_SIZE 08 15 ASSOC_BLK_SIZE 16 23 INGRESS_PORT 24 31 LARGE CMD RESERVED ASSOC_ PRESENT Bits Name Description Type Reset Value 0 15 ASSOC_BLK_ SIZE This field is ignored Set this field to 0 when writing the register for future softwar...

Page 267: ...ion Register 11 Add Associations This register write adds associations between a destination ID and multicast mask number The multicast mask number and destination ID are specified by a prior write to the RapidIO Multicast DestID Configuration Register This field returns the previously written value when this register is read R W 0 27 30 Reserved Reserved R 0000 31 ASSOC_ PRESENT Association Prese...

Page 268: ...s and some read only fields using the I2 C register loading capability on boot Refer to I2 C Interface on page 141 for more information on the use of I2 C controller register loading capability Reads to reserved register addresses return 0 writes to reserved register addresses complete without error The following table shows the register offsets of the physical layer of the Tsi578 When the even nu...

Page 269: ...ology www idt com 8 0x0240 1x 4x serial port 9 0x0260 1x serial port 10 0x0280 1x 4x serial port 11 0x02A0 1x serial port 12 0x02C0 1x 4x serial port 13 0x02E0 1xserial port 14 0x0300 1x 4x serial port 15 0x0320 1x serial port Table 37 Physical Interface Register Offsets RapidIO Port x Registers Port Offset Description ...

Page 270: ...e block header information Register name RIO_SW_MB_HEAD Reset value 0x1000_0009 Register offset 100 Bits 0 1 2 3 4 5 6 7 00 07 EF_PTR 08 15 EF_PTR 16 23 EF_ID 24 31 EF_ID Bits Name Description Type Reset Value 0 15 EF_PTR Extended Features Pointer Hard wired pointer to the next block in the features data structure R 0x1000 16 31 EF_ID Hard wired Extended Features ID 0x0009 Switch with software rec...

Page 271: ...of 100 MHz When Link Time Out is expired the port enters the Output Error state as outlined in the RapidIO Interconnect Specification Revision 1 3 Register name RIO_SW_LT_CTL Reset value 0xFFFF_FF00 Register offset 120 Bits 0 1 2 3 4 5 6 7 00 07 TVAL 08 15 TVAL 16 23 TVAL 24 31 Reserved Bits Name Description Type Reset Value 0 23 TVAL Timeout Interval Value Timeout 32 F TVAL where F is the registe...

Page 272: ...ble through the Port General Control CSR of any other physical layer implemented on a device Register name RIO_SW_GEN_CTL Reset value 0x0000_0000 Register offset 13C Bits 0 1 2 3 4 5 6 7 00 07 Reserved DISC Reserved 08 15 Reserved 16 23 Reserved 24 31 Reserved Bits Name Description Type Reset Value 0 1 Reserved N A R 0 2 DISC Discovered This device has been located by the processing element respon...

Page 273: ... request is outstanding and the CMD field is written to then the register write is ignored If this register is written twice in rapid succession it could cause a protocol violation If the RapidIO Serial Port x Link Maintenance Response CSR does not indicate that the link request is complete software must ensure that a period of time equal to the Port Link Timeout period controlled by the RapidIO S...

Page 274: ...ical Layer Registers 274 Tsi578 User Manual June 6 2016 Integrated Device Technology www idt com Writing to this register on a port in normal operation affects traffic on that port This register should only be used on ports in an error state ...

Page 275: ...AT LINK_STAT Bits Name Description Type Reset Value 0 RESP_VLD Response Valid 0 No link response control symbol received or no link request reset transmitted 1 If the link request was a link request input status this bit indicates that the link response control symbol has been received The LINK_STAT field contains information pertaining to that link response If link request was a link request rese...

Page 276: ...r to manually implement error recovery Note The INBOUND value can be initialized through the I2 C Interface Initializing the INBOUND value from I2 C is required for test purposes only Unless the INBOUND value is initialized to 0 the device state is not consistent with the state required by the RapidIO Specification It is not possible to exchange packets after a reset if the INBOUND value is other ...

Page 277: ...this register is being processed the OUTBOUND value is not used for the next packet transmitted The new OUTBOUND value is always used when the port is operating normally and when the port is in an error state The OUTBOUND field may only be written when there are no packets outstanding in the transmit queue and no packets are being exchanged with a link partner Caution Changing the OUTBOUND field w...

Page 278: ...RT_ ERR PORT_ OK PORT_ UNINIT Bits Name Description Type Reset Value 0 4 Reserved N A R 0 5 OUTPUT_DROP Output port has discarded a packet The packet is dropped when the Error Rate Threshold is reached when the time to live counter has expired or when a TEA or MAC_TEA error has occurred R W1C 0 6 OUTPUT_FAIL Output Failed Encountered Output port has encountered a failed condition meaning that the ...

Page 279: ...ssibly recovered from a transmission error This bit is set when the Output Error stopped bit bit 15 is set R W1C 0 15 OUTPUT_ERR_ STOP Output Error stopped Outbound port is in the output error stopped state R 0 16 20 Reserved N A R 0 21 INPUT_RS Input Retry stopped Inbound port is in the input retry stopped state R 0 22 INPUT_ERR Input Error encountered Inbound port has encountered and possibly re...

Page 280: ...nable to recover fatal error The following fatal errors cause a PORT_ERR Four link request tries with link response but no outstanding ackID Four link request tries with time out error for link response Dead link timer is enabled in the DLT_EN bit in the SRIO MAC x Digital Loopback and Clock Selection Register on page 377 and the timer expires Refer to Dead Link Timer on page 64 for more informati...

Page 281: ...DROP_EN PORT_LO CKOUT PORT_TYP E Bits Name Description Type Reset Value 0 1 PORT_WIDTH Port Width This field displays the port mode after reset 00 Single lane port the port is 1x mode only 01 Four lane port the port has 1x 4x mode and can operate in 1x or 4x mode PORT_WIDTH is defined by the SPx_MODESEL pin as follows If the SPx_MODESEL pin is high PORT_WIDTH for SPx is 0 and PORT_WIDTH for SPx 1 ...

Page 282: ...dependent Register on page 319 register Note Initial port width of the port is set by SPx_MODESEL pins at power up After reset release the SPx_MODESEL pins are ignored and configuration is controlled by this register R W 0 8 PORT_DIS Port Disable 0 Port receivers drivers are enabled 1 Port receivers drivers are disabled and are unable to receive transmit to any packets or control symbols When the ...

Page 283: ... control symbols out this port R W 0 13 Reserved N A R 0 14 ENUM_B Enumeration boundary bit used in system discovery algorithms This bit does not control any functionality within the Tsi578 The reset value of this bit is 1 for port 2 For all other ports the reset value of this bit is 0 R W Undefined 15 27 Reserved N A R 0 28 STOP_FAIL_EN Stop on Port Failed Encountered Enable This bit is used the ...

Page 284: ...force the sending device to signal an error condition The receipt of a packet by the locked out port causes the assertion of the INPUT_ERR and INPUT_ERR_STOP bits in its RapidIO Port x Error and Status CSR The link partner indicates packet rejection by asserting its OUTPUT_ERR and OUTPUT_ERR_STOP bits Setting the PORT_LOCKOUT bit also causes the port to drop all packets arriving from the ISF for t...

Page 285: ...rmation on the use of I2C controller register loading capability The Logical Transport Error Detect registers are not required for a switch However a switch s register bus access errors and transport errors are reported per port in bit 0 of the RapidIO Port x Error Detect CSR on page 294 The port s capture registers contain error information All registers are 32 bits and aligned to a 32 bit bounda...

Page 286: ...ts to the connected device if the Output Failed Encountered bit is set and or if the Error Rate Failed threshold has been met or exceeded 0 1 The port discards packets that receive a Packet not accepted control symbol when the Error Rate Failed Threshold has been met or exceeded Upon discarding a packet the port sets the Output Packet dropped bit in the Port x Error and Status CSR If the output po...

Page 287: ...agement Extensions registers in the Tsi578 Register name RIO_ERR_RPT_BH Reset value 0x0000_0007 Register offset 1000 Bits 0 1 2 3 4 5 6 7 00 07 EF_PTR 08 15 EF_PTR 16 23 EF_ID 24 31 EF_ID Bits Name Description Type Reset Value 0 15 EF_PTR Extended Features Pointer Hard wired pointer to the next block in the data structure 0000 Last extended feature block R 0x0000 16 31 EF_ID Hard wired Extended Fe...

Page 288: ... No other packets reach the logical layer of a switch Register name RIO_LOG_ERR_DET Reset value 0x0000_0000 Register offset 1008 Bits 0 1 2 3 4 5 6 7 00 07 Reserved L_ILL_TRA NS Reserved 08 15 L_ILL_RES P L_UNSUP_ TRANS Reserved 16 23 Reserved 24 31 Reserved Bits Name Description Type Reset Value 0 3 Reserved N A R 0 4 L_ILL_TRANS Illegal Transaction Bit is set when a terminating maintenance Type ...

Page 289: ...errupts can be generated for these sources No other packets reach the logical layer of a switch Register name RIO_LOG_ERR_DET_EN Reset value 0x0000_0000 Register offset 100C Bits 0 1 2 3 4 5 6 7 00 07 Reserved ILL_TRANS _EN Reserved 08 15 ILL_RESP_ EN UNSUP_T RANS_EN Reserved 16 23 Reserved 24 31 Reserved Bits Name Descriptiona a All bits in this register enable bits in RapidIO Logical and Transpo...

Page 290: ...ata can be captured in this register for erroneous port writes and maintenance responses as these transactions reserve the address field If the TT code for an erroneous maintenance request is invalid this register captures the address of the invalid data Refer to RapidIO Logical and Transport Layer Device ID Capture CSR on page 291 for the source ID where the error originated Note that this regist...

Page 291: ...et received For switches the errors detected are limited to maintenance packets maintenance requests maintenance responses and port writes with a hop count of 0 No other packets can reach the logical layer of a switch Note that this register is not updated when a correctly formatted maintenance request fails Register name RIO_LOG_ERR_DEVID Reset value 0x0000_0000 Register offset 1018 Bits 0 1 2 3 ...

Page 292: ...wing the FTYPE field in the packet Note that for switches the errors detected are limited to maintenance packets maintenance requests maintenance responses and port writes with a hop count of 0 No other packets reach the logical layer of a switch Note that this register is not updated when a correctly formatted maintenance request fails Register name RIO_LOG_ERR_CTRL_INFO Reset value 0x0000_0000 R...

Page 293: ...Bits 0 1 2 3 4 5 6 7 00 07 DESTID_MSB 08 15 DESTID_LSB 16 23 LARGE_ DESTID Reserved 24 31 Reserved Bits Name Description Type Reset Value 0 7 DESTID_MSB Most Significant Byte of port write Target Device ID This field is used only when LARGE_DESTID is 1 R W 0 8 15 DESTID_LSB If LARGE_DESTID is 0 the DESTID_LSB field is the 8 bit DESTID used in locally generated port write requests If LARGE_DESTID i...

Page 294: ...297 When the threshold is reached hardware informs the system software of the error using its standard error reporting function After the error has been reported the system software can read and clear registers as necessary to complete its error handling protocol testing Register name SP 0 15 _ERR_DET Reset value 0x0000_0000 Register offset 1040 1080 10C0 1100 1140 1180 11C0 1200 1240 1280 12C0 13...

Page 295: ... TEA MC_TEA LUT_PAR_ERR ILL_TRANS_ERR Caution The Error Capture register information is only valid for Reserved Transport Type Detected errors and Unmapped DestID errors For the Max Retry errors the information latched is the last packet received not the packet that was retried For more information on error capture see RapidIO Port x Error Capture Attributes CSR and Debug 0 on page 299 R W0C 0 1 8...

Page 296: ...d a packet accepted control symbol for it and has moved to the next ACK_ID value This value can be found in the RapidIO Serial Port x Local ackID Status CSR on page 276 Therefore an ACK_ID mismatch has occurred and until the ACK_IDs are re aligned no packet transfers take place R W0C 0 27 PROT_ERR Protocol Error Received control symbol is unexpected R W0C 0 28 Reserved N A R 0 29 DELIN_ERR Delinea...

Page 297: ... 1384 13C4 1404 Bits 0 1 2 3 4 5 6 7 00 07 IMP_SPEC _ERR Reserved 08 15 Reserved CS_CRC_E RR_EN CS_ILL_ID _EN CS_NOT_A CC_EN PKT_ILL_A CKID_EN PKT_CRC_ ERR_EN PKT_ILL_S IZE_EN Reserved 16 23 Reserved 24 31 Reserved LR_ ACKID_ ILL_EN PROT_ ERR_EN Reserved DELIN_ ERR_EN CS_ACK_ ILL_EN LINK_TO_E N Bits Name Description Type Reset Value 0 IMP_SPEC_ERR Logical Transport Error Enable Enable error rate c...

Page 298: ... bytes R W 0 15 25 Reserved N A R 0 26 LR_ACKID_ILL_ EN Enable error rate counting A received Link Response control symbol contains an ackID that is not outstanding R W 0 27 PROT_ERR_EN Enable error rate counting Protocol Error Received Control Symbol is unexpected R W 0 28 Reserved N A R 0 29 DELIN_ERR_EN Enable error rate counting Delineation Error Received unaligned SC or PD or undefined code g...

Page 299: ...d ERR_TYPE 08 15 Reserved 16 23 Reserved 24 31 Reserved VAL_CAPT Bits Name Description Type Reset Value 0 1 INFO_TYPE Type of information logged 00 Packet 01 Control Symbol and unaligned SC or PD or undefined code group 10 Implementation specific capture register contents are implementation specific to report implementation specific errors 11 Reserved for serial port R W 0 2 Reserved N A R 0 3 7 E...

Page 300: ...rt Error No 00001 to 00111 Bit 1 8 Reserved 01000 Bit 9 CS_CRC_ERR Control Symbol CRC Error Yes 01001 Bit 10 CS_ILL_ID Control Symbol Illegal ID Yes 01011 Bit 11 CS_NOT_ACC Control Symbol Not Accepted Yes 01011 Bit 12 PKT_ILL_ACKID Packet Illegal AckID Yes 01011 Bit 13 PKT_ILL_SIZE Packet Illegal Size Yes 0110 to 11001 Bit 14 25 Reserved 11010 Bit 26 LR_ACKID_IL Link Response Received with an Ille...

Page 301: ...rror recovery and threshold function the RapidIO Port x Error Detect CSR on page 294 and the Port x Error Capture registers are also writable Software must clear the Capture Valid Info VAL_CAPT bit in the RapidIO Port x Error Capture Attributes CSR and Debug 0 on page 299 then write the packet control symbol information to the other capture registers Register name SP 0 15 _ERR_CAPT_0_DBG1 Reset va...

Page 302: ...0 1150 1190 11D0 1210 1250 1290 12D0 1310 1350 1390 13D0 1410 Bits 0 1 2 3 4 5 6 7 00 7 CAPT_1 0 7 8 15 CAPT_1 8 15 16 23 CAPT_1 16 23 24 31 CAPT_1 24 31 Bits Name Description Type Reset Value 0 31 CAPT_1 Bytes 4 to 7 of the packet R W 0 Register name SP 0 15 _ERR_CAPT_2_DBG3 Reset value 0x0000_0000 Register offset 1054 1094 10D4 1114 1154 1194 11D4 1214 1254 1294 12D4 1314 1354 1394 13D4 1414 Bit...

Page 303: ...Packet Error Capture CSR 3 and Debug 4 Register name SP 0 15 _ERR_CAPT_3_DBG4 Reset value 0x0000_0000 Register offset 1058 1098 10D8 1118 1158 1198 11D8 1218 1258 1298 12D8 1318 1358 1398 13D8 1418 Bits 0 1 2 3 4 5 6 7 0 7 CAPT_3 0 7 8 15 CAPT_3 8 15 16 23 CAPT_3 16 23 24 31 CAPT_3 24 31 Bits Name Description Type Reset Value 0 31 CAPT_3 Byte 12 to 15 of the packet R W 0 ...

Page 304: ...0 7 ERR_RB The Error Rate Bias value Register bus frequency 100 MHz 00 Do not decrement error rate counter 01 Decrement every 1 31ms 02 Decrement every 10 48ms 04 Decrement every 83 88ms 08 Decrement every 1 342s 10 Decrement every 10 74s 20 Decrement every 86s 40 Decrement every 1374s 80 Decrement every 10995s FF Decrement every 1 28us Debug only Other values are reserved R W 0x80 8 13 Reserved N...

Page 305: ...ort This number is decremented by the Error Rate Bias function The counter cannot over or underflow and continue to increment or decrement as defined even if thresholds are met Software can reset this counter If the value of the counter equals the error rate threshold trigger register an error is reported For more information see the RapidIO Interconnect Specification Revision 1 3 Part 8 Error Man...

Page 306: ... 16 23 Reserved 24 31 Reserved Bits Name Description Type Reset Value 0 7 ERR_RFT Error Rate Failed Threshold These bits provide the threshold value for reporting an error condition due to a possibly broken link 00 Disable the error rate failed register 01 Set the error reporting threshold to 1 02 Set the error reporting threshold to 2 FF Set the error reporting threshold to 255 R W 0xFF 8 15 ERR_...

Page 307: ...ding capability on boot Refer to I2 C Interface on page 141 for more information on the use of I2 C controller register loading capability When a individual port is powered down the IDT Specific RapidIO Registers are read only and return 0 with the exception of RapidIO Port x Error and Status CSR on page 278 and RapidIO Serial Port x Control CSR on page 281 both of which return 0x00000001 when rea...

Page 308: ...Per Port Performance Registers Port Register Offset Description SP0 13000 1x 4x mode serial port SP1 13100 1x mode serial port SP2 13200 1x 4x mode serial port SP3 13300 1x mode serial port SP4 13400 1x 4x mode serial port SP5 13500 1x mode serial port SP6 13600 1x 4x mode serial port SP7 13700 1x mode serial port SP8 13800 1x 4x Serial port SP9 13900 1x Serial port SP10 13A00 1x 4x Serial port SP...

Page 309: ...ype Reset Value 0 3 DISCOVERY_ TIMER Discovery Timer This field is used by serial ports configured to operate in 4x mode The discovery timer allows time for the link partner to enter its discovery state and if the link partner supports 4x mode for all four lanes to be aligned The discovery timer has a value of 11 79 ms with the P_CLK set to 100 MHz 0 320 1 15 DISCOVERY_TIMER decimal 1179639 1 P_CL...

Page 310: ...S_ INT_EN Bits Name Description Type Reset Value 0 1 Reserved N A R 0 2 IDLE_ERR_DIS Idle Error Checking Disable 0 Error checking is enabled by default if one or more data characters are sent Dx y characters not delimited with start of packet end of packet control symbols in an idle sequence the device enters the Input Error stopped state 1 Ignore all not idle or invalid characters in the idle seq...

Page 311: ...of 256 destination IDs 1 One 512 entry local LUT R W 1 8 29 Reserved N A R 0 30 MCS_INT_EN Multicast Event Control Symbol Interrupt Enable 0 Disabled 1 Enabled The interrupt signal is high when the multicast event control symbol is received R W 0 31 RCS_INT_EN Reset Control Symbol Interrupt Enable 0 Disabled 1 Enabled The interrupt signal is High when four reset control symbols are received in a s...

Page 312: ... Interrupt Status Indicates whether a multicast event control symbol has been received on the port Reading the MCS field using the BC offset gives the value of Port 0 All MCS interrupts from ports are ORed together The Global Interrupt Status Register on page 388 shows the status of the combined MCS interrupts from all ports Write 1 to clear this bit Writing 1 to this bit clears the interrupt on a...

Page 313: ... 13 15 PRIO2WM Priority 2 packets are accepted if the number of free buffer is greater than this value This value must be smaller than PRIO1WM Note It is a programming error for this value to be either greater than or equal to PRIO1WM or PRIO0WM or greater than 7 R W 1 16 20 Reserved N A R 0 21 23 PRIO1WM Priority 1 packets are accepted if the number of free buffer is greater than this value This ...

Page 314: ...ST_ID 0 7 24 31 CFG_DEST_ID 8 15 Bits Name Description Type Reset Value 0 AUTO_INC Automatically post increment the destination ID when the destination ID is used to perform either a read or a write through the RapidIO Port x Route Config Output Port CSR on page 315 R W 0 1 PAR_INVERT Parity Invert This bit is for testing of interrupt and or demerit software systems 0 Normal operation 1 Invert the...

Page 315: ...ration Register name SP BC 0 15 _ROUTE_CFG_PORT Reset value Undefined Register offset 10074 11074 11174 11274 11374 11474 11574 11674 11774 11874 11974 11A74 11B74 11C74 11D74 11E74 11F74 Bits 0 1 2 3 4 5 6 7 00 07 Reserved 08 15 Reserved 16 23 Reserved 24 31 PORT Bits Name Description Type Reset Value 0 23 Reserved N A R 0 24 31 PORT This is the RapidIO output port through which all transactions ...

Page 316: ...Reset value 0x0000_0000 Register offset 10078 11078 11178 11278 11378 11478 11578 11678 11778 11878 11978 11A78 11B78 11C78 11D78 11E78 11F78 Bits 0 1 2 3 4 5 6 7 00 07 BASE 08 15 Reserved 16 23 Reserved 24 31 Reserved Bits Name Description Type Reset Value 0 7 BASE This value represents the most significant byte of a destination ID If the most significant upper 8 bits of an incoming 16 bit destin...

Page 317: ..._EN LARGE_ SYS Reserved 8 15 Reserved 16 23 MC_ID 15 8 24 31 MC_ID 7 0 Bits Name Description Type Reset Value 0 MC_EN Multicast can be disabled by setting this bit 0 Disabled 1 Enabled R W 0 1 LARGE_ SYS This field defines multicast destination ID MC_ID in the Large or Small system The MC_ID of Small system is not a subset of MC_ID of Large system but both systems can co exist together 0 Small sys...

Page 318: ...sent to all egress ports whose multicast select bit is set to 1 However the multicast packet is not sent to the port from which it was received regardless of the setting of that port s multicast select bit This registers is only located in the multicast engine Register name RIO_MC_MSK 0 7 Reset value 0x0000_0000 Register offset 10320 10324 10328 1032C 10330 10334 10338 1033C Bits 0 1 2 3 4 5 6 7 0...

Page 319: ...alue 0 1 Reserved N A R 0 2 SCRATCH Scratch Pad This bit controls no functionality It is a read write scratch pad bit for software use R W 0 3 4 Reserved N A R 0 5 FORCE_REINIT Force Link Re initialization Process This bit is active on write and automatically returns to 0 R W1S 0 6 Reserved N A R 0 7 TRANS_MODE Transfer mode for each port 0 Cut through mode In cut through mode the incoming packet ...

Page 320: ...W 0 14 LINK_INIT_NOTIF ICATION_EN Enables interrupts and port writes for LINK_INIT_NOTIFICATION events 0 Interrupt and or port write disabled 1 Interrupt and or port write enabled R W 0 15 LUT_PAR_ERR_ EN Enables interrupts for parity errors in the lookup table 0 Interrupt disabled 1 Interrupt enabled R W 0 16 23 MAX_RETRY_TH RESHOLD Maximum Retry Threshold These bits provide the threshold value f...

Page 321: ...epth Interrupt Enable An interrupt is generated when the OUTB_DEPTH bit is set in the RapidIO Port x Interrupt Status Register on page 326 R W 0 28 INB_DEPTH_EN Input Queue Depth Interrupt Enable An interrupt is generated when the INB_DEPTH bit is set in the RapidIO Port x Interrupt Status Register on page 326 R W 0 29 INB_RDR_EN Inbound Reorder Interrupt Enable An interrupt is generated when the ...

Page 322: ... only one outstanding request at a time Subsequent requests are ignored until the multicast control symbol is sent Register name SP 0 15 _SEND_MCS Reset value 0x0000_0002 Register offset 1300C 1310C 1320C 1330C 1340C 1350C 1360C 1370C 1380C 1390C 13A0C 13B0C 13C0C 13D0C 13E0C 13F0C Bits 0 1 2 3 4 5 6 7 00 07 Reserved 08 15 Reserved 16 23 Reserved 24 31 Reserved DONE SEND Bits Name Description Type...

Page 323: ... Reserved PORT_NUM Bits Name Description Type Reset Value 0 7 DESTID_MSB Most significant byte of a 16 bit destination ID used in the lookup operation which caused the error Only valid if the LG_DESTID field value is 1 and a LUT parity error is signalled in the Port x Interrupt Status CSR When the parity error is cleared in RapidIO Port x Interrupt Status Register on page 326 the information in th...

Page 324: ...he LUT entry is mapped The PORT_NUM field value is the port to which the packet could be routed 0x0 to 0xF Caution The value of this bit is unpredictable when there is a parity error in the LUT For more information see Lookup Table Parity on page 49 R W 0 26 27 Reserved N A R 0 28 31 PORT_NUM The Tsi578 port number where packets are routed If the port is unmapped LUT_VLD 0 then the field reads 0xF...

Page 325: ..._0 Encoding for control symbol This field uses the parameters PAR_0 and PAR_1 R W 0 3 7 PAR_0 Used in conjunction with stype0 encoding R W 0 8 12 PAR_1 Used in conjunction with stype0 encoding R W 0 13 15 STYPE_1 Encoding for the control symbol that uses the CMD parameter R W 0 16 18 CMD Used in conjunction with stype1 encoding to define the link maintenance commands R W 0 19 CS_EMB Embed the cont...

Page 326: ...er This bit is cleared by writing a 1 to it or by clearing all bits in the RapidIO Port x Error Detect CSR on page 294 R W1C 0 14 LINK_INIT_ NOTIFICATION Link Initialization Notification Once set the LINK_INIT_NOTIFICATION bit is cleared by writing 1 to it When the PORT_LOCKOUT bit is set in RapidIO Serial Port x Control CSR on page 281 and a link has initialized according to the PORT_OK bit in Ra...

Page 327: ...age 57 Once set the bit remains unchanged until all the error sources are cleared The setting of this bit generates an interrupt if the IRQ_EN bit in RapidIO Port x Control Independent Register on page 319 is set R 0 26 MAX_ RETRY Maximum Retry Error Set when number of retries has reached MAX_RETRY_THRESHOLD An interrupt is generated if MAX_RETRY_EN is set A port write request can also be generate...

Page 328: ...is set when Reordering Count reaches the maximum number defined in the Inbound Reordering Threshold field in the RapidIO Port x Reordering Counter Register on page 360 To get an interrupt in this status register the Inbound Interrupt Reordering Enable bit in the RapidIO Port x Control Independent Register on page 319 has to be set to 1 Writing a 1 to this bit clears the interrupt and clears INB_RD...

Page 329: ...3 Reserved 24 31 ILL_TRANS _GEN Reserved MAX_RET RY_GEN OUTB_DE PTH_GEN INB_DEPT H_GEN INB_RDR_ GEN Reserved TEA_GEN Bits Name Descriptiona Type Reset Value 0 12 Reserved N A R 0 13 MC_TEA_GEN Forces the MC_TEA bit to be set Bit always reads as zero R W1S 0 14 LINK_INIT_NOTIFIC ATION_GEN Forces the LINK_INIT_NOTIFICATION bit to be set This bit always reads as zero R W1S 0 15 LUT_PAR_ERR_GE N Force...

Page 330: ...s as zero R W1S 0 30 Reserved Reserved R W1S 0 31 TEA_GEN Forces the TEA bit to be set to 1 This bit always reads as zero R W1S 0 a All bits in this register set clear bits in the RapidIO Port x Interrupt Status Register on page 326 Writing 0 to any bit in this register clears the corresponding bit in the RapidIO Port x Interrupt Status Register on page 326 Continued Bits Name Descriptiona Type Re...

Page 331: ...on 1 3 It is not possible to broadcast to these registers Table 43 IDT Specific Per Port Performance Registers Port Register Offset Description SP0 13000 1x 4x Serial port SP1 13100 1x Serial port SP2 13200 1x 4x Serial port SP3 13300 1x Serial port SP4 13400 1x 4x Serial port SP5 13500 1x Serial port SP6 13600 1x 4x Serial port SP7 13700 1x Serial port SP8 13800 1x 4x Serial port SP9 13900 1x Ser...

Page 332: ...erformance Statistics Counter 0 Register on page 344 and RapidIO Port x Performance Statistics Counter 1 Register on page 345 The SPx_PSCy can be disabled by selecting PSy_PRIO 0 3 to be set to 0 Setting PSy_PRIO 0 3 to all ones allows for collecting performance statistics through the SPx_PSCy for all priority packets Register name SP 0 15 _PSC0n1_CTRL Reset value 0x0000_0000 Register offset 13020...

Page 333: ...s Counter 0 Register on page 344 0 If all PS0_PRIO 0 3 are set to zero the RapidIO Port x Performance Statistics Counter 0 Register on page 344 is disabled 1 Count priority 1 packets R W 0 3 PS0_PRIO0 Performance Stats Reg PS0 Priority 0 Selection This value represents the packet priority 0 is selected for which performance stats are accumulated for in the RapidIO Port x Performance Statistics Cou...

Page 334: ...ulticast packet including header R W 0 16 PS1_PRIO3 Performance Stats Reg PS1 Priority 3 Selection This value represents the packet priority 3 is selected for which performance stats are accumulated for in the RapidIO Port x Performance Statistics Counter 1 Register on page 345 0 If all PS1_PRIO 0 3 are set to zero the RapidIO Port x Performance Statistics Counter 1 Register on page 345 is disable...

Page 335: ...erved N A R 0 29 31 PS1_TYPE Performance Stats Reg PS1 Type Selection This value determines the type of performance statistics that is collected in the RapidIO Port x Performance Statistics Counter 1 Register on page 345 Retries are not counted as part of the data 000 Count all unicast request packets only The response packets maintenance packets and maintenance packets with hop count of 0 are exc...

Page 336: ...unter 2 Register on page 346 and RapidIO Port x Performance Statistics Counter 3 Register on page 347 The SPx_PSCy can be disabled by selecting PSy_PRIO 0 3 to be set to 0 Setting PSy_PRIO 0 3 to all ones allows for collecting performance statistics through the SPx_PSCy for all priority packets Register name SP 0 15 _PSC2n3_CTRL Reset value 0x0000_0000 Register offset 13024 13124 13224 13324 13424...

Page 337: ...trol Register on page 340 0 If all PS2_PRIO 0 3 are set to zero the RapidIO Port x Performance Statistics Counter 4 and 5 Control Register on page 340 is disabled 1 Count priority 1 packets R W 0 3 PS2_PRIO0 Performance Stats Reg PS2 Priority 0 Selection This value represents the packet priority 0 is selected for which performance stats are accumulated for in the RapidIO Port x Performance Statist...

Page 338: ...ntire multicast packet including header R W 0 16 PS3_PRIO3 Performance Stats Reg PS3 Priority 3 Selection This value represents the packet priority 3 is selected for which performance stats are accumulated for in the RapidIO Port x Performance Statistics Counter 3 Register on page 347 0 If all PS3_PRIO 0 3 are set to zero the RapidIO Port x Performance Statistics Counter 3 Register on page 347 is ...

Page 339: ...erved N A R 0 29 31 PS3_TYPE Performance Stats Reg PS3 Type Selection This value determines the type of performance statistics that is collected in the RapidIO Port x Performance Statistics Counter 3 Register on page 347 Retries are not counted as part of the data 000 Count all unicast request packets only The response packets maintenance packets and maintenance packets with hop count of 0 are exc...

Page 340: ...e Statistics Counter 4 Register on page 348 and RapidIO Port x Performance Statistics Counter 5 Register on page 349 The SPx_PSCy can be disabled by selecting PSy_PRIO 0 3 to be set to 0 Setting PSy_PRIO 0 3 to all ones allows for collecting performance statistics through the SPx_PSCy for all priority packets Register name SP 0 15 _PSC4n5_CTRL Reset value 0x0000_0000 Register offset 13028 13128 13...

Page 341: ...s Counter 4 Register on page 348 0 If all PS4_PRIO 0 3 are set to zero the RapidIO Port x Performance Statistics Counter 4 Register on page 348 is disabled 1 Count priority 1 packets R W 0 3 PS4_PRIO0 Performance Stats Reg PS4 Priority 0 Selection This value represents the packet priority 0 is selected for which performance stats are accumulated for in the RapidIO Port x Performance Statistics Cou...

Page 342: ... multicast packet including header R W 0 16 PS5_PRIO3 Performance Stats Reg PS5 Priority 3 Selection This value represents the packet priority 3 is selected for which performance stats are accumulated for in the RapidIO Port x Performance Statistics Counter 5 Register on page 349 0 If all PS5_PRIO 0 3 are set to zero the RapidIO Port x Performance Statistics Counter 5 Register on page 349 is disab...

Page 343: ...S5 Type Selection This value determines the type of performance statistics that is collected in the RapidIO Port x Performance Statistics Counter 5 Register on page 349 Retries are not counted as part of the data 000 Count all unicast request packets only The response packets maintenance packets and maintenance packets with hop count of 0 are excluded from this counter 001 Count all unicast packet...

Page 344: ...alue is writable for testing purposes This counter saturates when it reaches its maximum value 0xFFFFFFFF and is cleared on a read The PS0_CTR is enabled when PS0_PRIO 0 3 value in the RapidIO Port x Performance Statistics Counter 0 and 1 Control Register on page 332 is configured to a value other than 0 Register name SP 0 15 _PSC0 Reset value 0x0000_0000 Register offset 13040 13140 13240 13340 13...

Page 345: ...alue is writable for testing purposes This counter saturates when it reaches its maximum value 0xFFFFFFFF and is cleared on a read The PS1_CTR is enabled when PS1_PRIO 0 3 value in the RapidIO Port x Performance Statistics Counter 0 and 1 Control Register on page 332 is configured to a value other than 0 Register name SP 0 15 _PSC1 Reset value 0x0000_0000 Register offset 13044 13144 13244 13344 13...

Page 346: ...nter value is writable for testing purposes This counter saturates when it reaches its maximum value 0xFFFFFFFF and is cleared on a read The PS2_CTR is enabled when PS2_PRIO 0 3 value in the RapidIO Port x Performance Statistics Counter 2 and 3 Control Register on page 336 is configured to a value other than 0 Register name SP 0 15 _PSC2 Reset value 0x0000_0000 Register offset 13048 13148 13248 13...

Page 347: ...alue is writable for testing purposes This counter saturates when it reaches its maximum value 0xFFFFFFFF and is cleared on a read The PS3_CTR is enabled when PS3_PRIO 0 3 value in the RapidIO Port x Performance Statistics Counter 2 and 3 Control Register on page 336 is configured to a value other than 0 Register name SP 0 15 _PSC3 Reset value 0x0000_0000 Register offset 1304C 1314C 1324C 1334C 13...

Page 348: ... is writable for testing purposes This counter saturates when it reaches its maximum value 0xFFFFFFFF and is cleared on a read The PS4_CTR is enabled when PS4_PRIO 0 3 value in the RapidIO Port x Performance Statistics Counter 4 and 5 Control Register on page 340 register is configured to a value other than 0 Register name SP 0 15 _PSC4 Reset value 0x0000_0000 Register offset 13050 13150 13250 133...

Page 349: ...TR counter value is writable for testing purposes This counter saturates when it reaches its maximum value 0xFFFFFFFF and is cleared on a read The PS5_CTR is enabled when PS5_PRIO 0 3 value in the RapidIO Port x Performance Statistics Counter 4 and 5 Control Register is configured to a value other than 0 Register name SP 0 15 _PSC5 Reset value 0x0000_0000 Register offset 13054 13154 13254 13354 13...

Page 350: ...780 13880 13980 13A80 13B80 13C80 13D80 13E80 13F80 Bits 0 1 2 3 4 5 6 7 00 7 CONG_PERIOD 8 15 CONG_PERIOD 16 23 DEPTH Reserved LEAK_RT 24 31 LEAK_RT Bits Name Description Type Reset Value 0 15 CONG_PERIOD This value is programmed by software to indicate the maximum number of clock cycles that the output buffer can be in a continuous congestion state The congestion state is determined based on the...

Page 351: ...fill reaches or exceeds 3 7 the congestion counter increments when the buffer fill reaches 8 8 Reserved R W 0x0 20 Reserved N A R 0 21 31 LEAK_RT This value is the leak rate for both the receiver and transmitter congestion counters Whenever this time period expires the CONG_CTR values for both transmitter RapidIO Port x Transmitter Output Queue Congestion Status Register on page 352 and receiver R...

Page 352: ...frequency as specified by the ERR_RB field in the RapidIO Port x Error Rate CSR on page 304 If the CONG_CTR equals or exceeds the threshold CONG_THRESH the maskable OUTB_DEPTH interrupt is generated Register name SP 0 15 _TX_Q_STATUS Reset value 0x0000_0000 Register offset 13084 13184 13284 13384 13484 13584 13684 13784 13884 13984 13A84 13B84 13C84 13D84 13E84 13F84 Bits 0 1 2 3 4 5 6 7 00 7 CONG...

Page 353: ... CONG_THRESH Output Queue Depth Threshold If the CONG_CTR count is equal to the value in this field an interrupt is reported to the system through the OUTB_DEPTH status bit in the RapidIO Port x Interrupt Status Register on page 326 Setting the CONG_THRES to zero disables the CONG_CTR R W 0x0000 Continued Bits Name Description Type Reset Value ...

Page 354: ...ading the CONG_PERIOD_CTR clears the counter value The CONG_PERIOD_CTR can be disabled when the CONG_PERIOD field in the RapidIO Port x Transmitter Output Queue Depth Threshold Register is set to 0 Register name SP 0 15 _TX_Q_PERIOD Reset value 0x0000_0000 Register offset 13088 13188 13288 13388 13488 13588 13688 13788 13888 13988 13A88 13B88 13C88 13D88 13E88 13F88 Bits 0 1 2 3 4 5 6 7 00 7 CONG_...

Page 355: ...Reset value 0x0000_0000 Register offset 13090 13190 13290 13390 13490 13590 13690 13790 13890 13990 13A90 13B90 13C90 13D90 13E90 13F90 Bits 0 1 2 3 4 5 6 7 00 7 CONG_PERIOD 8 15 CONG_PERIOD 16 23 DEPTH Reserved 24 31 Reserved Bits Name Description Type Reset Value 0 15 CONG_PERIOD This value is programmed by SW to indicate the maximum number of clock cycles that the output buffer can be in a cont...

Page 356: ...f packets in the input queue meets or exceeds this number the congestion counter is incremented 0 Disables congestion monitoring 1 The congestion counter increments when the buffer fill reaches or exceeds 2 2 The congestion counter increments when the buffer fill reaches or exceeds 3 7 the congestion counter increments when the buffer fill reaches 8 8 Reserved R W 0 20 31 Reserved N A R 0 Continue...

Page 357: ...s frequency as specified by the ERR_RB field in the RapidIO Port x Error Rate CSR on page 304 If the CONG_CTR equals or exceeds the threshold CONG_THRESH the maskable INB_DEPTH interrupt is generated Register name SP 0 15 _RX_Q_STATUS Reset value 0x0000_0000 Register offset 13094 13194 13294 13394 13494 13594 13694 13794 13894 13994 13A94 13B94 13C94 13D94 13E94 13F94 Bits 0 1 2 3 4 5 6 7 00 7 CON...

Page 358: ...1 CONG_THRESH Input Queue Depth Threshold If the CONG_CTR count is equal to the value in this field an interrupt is reported to the system through the INB_DEPTH status bit in the RapidIO Port x Interrupt Status Register on page 326 Setting the CONG_THRESH to zero disables the CONG_CTR R W 0x0000 Continued Bits Name Description Type Reset Value ...

Page 359: ...NG_PRIOD_CTR clears the register The CONG_PERIOD_CTR can be disabled when the CONG_PERIOD field in the RapidIO Port x Receiver Input Queue Depth Threshold Register is set to 0 Register name SP 0 15 _RX_Q_PERIOD Reset value 0x0000_0000 Register offset 13098 13198 13298 13398 13498 13598 13698 13798 13898 13998 13A98 13B98 13C98 13D98 13E98 13F98 Bits 0 1 2 3 4 5 6 7 00 7 CONG_PERIOD_CTR 8 15 CONG_P...

Page 360: ...26 Register name SP 0 15 _REORDER_CTR Reset value 0x0000_FFFF Register offset 130A0 131A0 132A0 133A0 134A0 135A0 136A0 137A0 138A0 139A0 13AA0 13BA0 13CA0 13DA0 13EA0 13FA0 Bits 0 1 2 3 4 5 6 7 00 7 CTR 8 15 CTR 16 23 THRESH 24 31 THRESH Bits Name Description Type Reset Value 0 15 CTR Reorder Counter This counter is updated every time the input queue is reordered This counter counts up to 0xFFFFa...

Page 361: ...e fields and some read only fields using the I2 C register loading capability on boot Refer to I2 C Interface on page 141 for more information on the use of I2C controller register loading capability Software must not access reserved addresses or bits because this can affect device operation in non deterministic ways Table 44 IDT Specific RapidIO Registers Port Register Offset Description BC 10000...

Page 362: ...L_PWRON in the SMACx_CFG_GBL register TX_EN in the SMACx_CFG_CH3 register TX_EN in the SMACx_CFG_CH2 register TX_EN in the SMACx_CFG_CH1 register TX_EN in the SMACx_CFG_CH0 register RX_PLL_PWRON in the SMACx_CFG_CH0 register RX_PLL_PWRON in the SMACx_CFG_CH1 register RX_PLL_PWRON in the SMACx_CFG_CH2 register RX_PLL_PWRON in the SMACx_CFG_CH3 register RX_EN in the SMACx_CFG_CH0 register RX_EN in t...

Page 363: ...me Description Type Reset Value 0 HALF_RATE Baud Rate Control 0 Running at 2 5Gbps and 3 125Gbps 1 Running at 1 25Gbps This bit corresponds to the SerDes PLL divider setting selected by the IO_SPEED field in the SRIO MAC x Digital Loopback and Clock Selection Register on page 377 Caution This field should not be independently modified Changing it can lead to unpredictable behavior R W Undefined 1 ...

Page 364: ...es Configuration Global on page 372 is set to 1 R W 0x1 18 DPLL_RESE T A rising edge resets the frequency register of the DPLL The rising edge may be generated by writing a 0 and then a 1 to the register bit R W 0x1 19 20 Reserved N A R W 0 21 23 RX_EQ_VAL 2 0 Receive Equalization control Internal linear equalizer boost is approximately rx_eq_val 1 0 5dB Example 3 b100 2 5dB boost R W 0x5 24 26 RX...

Page 365: ...s Serial Port Electrical Layer Registers 365 Tsi578 User Manual June 6 2016 Integrated Device Technology www idt com 31 Reserved N A Note Only write 1 to this reserved field R W 1 Continued Bits Name Description Type Reset Value ...

Page 366: ...erved Bits Name Description Type Reset Value 0 HALF_RATE Baud rate control 0 Running at 2 5 Gbps and 3 125 Gbps 1 Running at 1 25 Gbps This bit corresponds to the SerDes PLL divider setting selected by the IO_SPEED field in the SRIO MAC x Digital Loopback and Clock Selection Register on page 377 Caution This field should not be independently modified Changing it can lead to unpredictable behavior ...

Page 367: ...ration Global on page 372 is set to 1 R W 0x1 18 DPLL_RESE T A rising edge resets the frequency register of the DPLL The rising edge can be generated by writing a 0 and then a 1 to the register bit R W 0x1 19 20 Reserved N A R W 0 21 23 RX_EQ_VAL 2 0 Receive Equalization control Internal linear equalizer boost is approximately rx_eq_val 1 0 5dB For example 3 b100 2 5dB boost R W 0x5 24 26 RX_DPLL_...

Page 368: ... 1 0 RX_ALIGN _EN Reserved Bits Name Description Type Reset Value 0 HALF_RATE Baud rate control 0 Running at 2 5 Gbps and 3 125 Gbps 1 Running at 1 25 Gbps This bit corresponds to the SerDes PLL divider setting selected by the IO_SPEED field in the SRIO MAC x Digital Loopback and Clock Selection Register on page 377 Caution This field should not be independently modified Changing it can lead to un...

Page 369: ...DPLL_RESE T A rising edge resets the frequency register of the DPLL The rising edge can be generated by writing a 0 and then a 1 to the register bit R W 0x1 19 20 Reserved N A R W 0 21 23 RX_EQ_VAL 2 0 Receive Equalization control Internal linear equalizer boost is approximately rx_eq_val 1 0 5dB For example 100 2 5dB boost R W 0x5 24 26 RX_DPLL_M ODE 2 0 DPLL Mode selection When RX_EN is not asse...

Page 370: ...eserved Bits Name Description Type Reset Value 0 HALF_RATE Baud rate control 0 Running at 2 5Gbps and 3 125Gbps 1 Running at 1 25Gbps This bit corresponds to the SerDes PLL divider setting selected by the IO_SPEED field in the SRIO MAC x Digital Loopback and Clock Selection Register on page 377 Caution This field should not be independently modified Changing it can lead to unpredictable behavior R...

Page 371: ...onfiguration Global on page 372 is set to 1 R W 0x1 18 DPLL_RESE T A rising edge resets the frequency register of the DPLL The rising edge can be generated by writing a 0 and then a 1 to the register bit R W 0x1 19 20 Reserved N A R W 0 21 23 RX_EQ_VAL 2 0 Receive Equalization control Internal linear equalizer boost is approximately rx_eq_val 1 0 5dB For example 3 b100 2 5dB boost R W 0x5 24 26 RX...

Page 372: ...s BYPASS_INIT is set to 1 R W 1 1 BYPASS_INI T Control bit to bypass initialization logic 0 default SerDes initialization is determined by SP_IO_SPEED 1 0 1 Bypass initialization logic set by the SP_IO_SPEED 1 0 pins and allow direct control to SerDes See BYPASS_INIT Functionality on page 362 for more information on this bit R W 0 2 Reserved N A R 0 3 7 TX_LVL 4 0 Fine Resolution setting of Tx sig...

Page 373: ...CK_O FF 0 Turns on the MPLL clock 1 Stops the reference clock This bit is read only unless BYPASS_INIT in is set to 1 R W 0 26 31 Reserved N A R W Undefined The reserved bits in this register are connected to signals that are configuration dependent Table 46 TX_LVL Values TX_LVL Value TX_LVL 0 4 Vdiff pp mV 0 0x00 5 b00000 929 8 1 0x01 5 b00001 939 4 2 0x02 5 b00010 949 1 3 0x03 5 b00011 958 8 4 0...

Page 374: ... 5 b10101 1133 1 22 0x16 5 b10110 1142 8 23 0x17 5 b10111 1152 5 24 0x18 5 b11000 1162 2 25 0x19 5 b11001 1171 9 26 0x1A 5 b11010 1181 6 27 0x1B 5 b11011 1191 3 28 0x1C 5 b11100 1200 9 29 0x1D 5 b11101 1210 6 30 0x1E 5 b11110 1220 3 31 0x1F 5 b11111 1230 0 Table 47 AC JTAG level programmed by ACJT_LVL 4 0 ACJT_LVL 4 0 Vmin level peak to peak differential mV Vmin level peak single ended mV 5 h02 31...

Page 375: ... www idt com 5 h07 521 133 5 h08 563 144 5 h09 605 155 5 h0A 648 165 5 h0B 692 176 5 h14 605 100 5 h15 670 111 5 h16 735 121 5 h17 800 133 5 h18 865 144 5 h19 932 155 5 h1A 997 165 5 h1B 1065 3176 Table 47 AC JTAG level programmed by ACJT_LVL 4 0 ACJT_LVL 4 0 Vmin level peak to peak differential mV Vmin level peak single ended mV ...

Page 376: ...Register offset 130C4 132C4 134C4 136C4 138C4 13AC4 13CC4 13EC4 Bits 0 1 2 3 4 5 6 7 00 07 Reserved 08 15 Reserved MPLL_PRESCALE 1 0 Unused 16 23 Unused 24 31 Unused Reserved Bits Name Description Type Reset Value 0 9 Reserved Reserved R 0 10 11 MPLL_PRES CALE 1 0 Controls the MPLL s REF_CLK prescaler Should be set to 2 b10 in Tsi578 Mapping 00 Reserved 01 Reserved 10 Divide REF_CLK by 2 11 Unused...

Page 377: ...d to determine when a link is powered up and enabled but dead that is there is no link partner responding When a link is declared dead the transmitting port on the Tsi578 removes all packets from its transmit queue and ensure that all new packets sent to port are dropped rather than placed in the transmit queue This feature affects both RapidIO ports sharing the MAC This feature is not limited to ...

Page 378: ...mation refer to Port Loopback Testing on page 79 R W 0 23 DLB_EVEN_ EN Digital Equipment Loopback Mode Even numbered Port Digital equipment loopback mode connects Tx data flow to Rx data flow before the 8B10b encoder decoder 0 Normal operation 1 Loopback enabled for the even numbered port served by this MAC The loopback path does not include the 8b 10B encoder decoder For more information refer to...

Page 379: ...ing to this register overrides the configuration provided by the pin 0 Normal mode of operation 1 Port powered down R W Undefined 29 PWDN_X4 Power down control for even numbered ports using this MAC Initially this field reflects the sampled value of the SPx_PWDN pin where x is 0 2 4 14 Writing to this register overrides the configuration provided by the odd numbered pins connected to this MAC 0 No...

Page 380: ...6 7 00 07 Reserved RDR_LIMIT 08 15 RDR_LIMIT _EN Reserved IN_ARB_MODE Reserved TEA_INT_E N TEA_EN 16 23 TEA_OUT 15 8 24 31 TEA_OUT 7 0 Bits Name Description Type Reset Value 0 3 Reserved N A R 0x0 4 7 RDR_LIMIT Reorder Limit When packets arrive at an ingress port they are sent to the fabric in order The fabric can change the order due to packet priority if enabled through IN_ARB_MODE and the fabri...

Page 381: ...rrupt is produced when a TEA event occurs R W 0 15 TEA_EN TEA Enable 0 TEA timer is disabled similar to writing all 0s to the TEA_OUT field 1 TEA timer is enabled R W 1 16 31 TEA_OUT 1 5 0 TEA Period This value is multiplied by 2 15 to determine the number of ISF clock cycles a request waits for an acknowledge before a transaction error acknowledge TEA occurs For example assume the ISF clock is op...

Page 382: ...Q PORT9_IR Q PORT8_IR Q 24 31 PORT7_IR Q PORT6_IR Q PORT5_IR Q PORT4_IR Q PORT3_IR Q PORT2_IR Q PORT1_IR Q PORT0_IR Q Bits Name Description Type Reset Value 0 15 Reserved N A R 0 16 PORT15_IRQ Serial Port 15 IRQ Indicates that a TEA has occurred on this port Writing a 1 to this bit clears it and causes the IRQ signal to be de asserted R W1C 0 17 PORT14_IRQ Serial Port 14 IRQ R W1C 0 18 PORT13_IRQ ...

Page 383: ...d Device Technology www idt com 26 PORT5_IRQ Serial port 5 IRQ R W1C 0 27 PORT4_IRQ Serial port 4 IRQ R W1C 0 28 PORT3_IRQ Serial port 3 IRQ R W1C 0 29 PORT2_IRQ Serial port 2 IRQ R W1C 0 30 PORT1_IRQ Serial port 1 IRQ R W1C 0 31 PORT0_IRQ Serial port 0 IRQ R W1C 0 Continued Bits Name Description Type Reset Value ...

Page 384: ...R P8_ERR 24 31 P7_ERR P6_ERR P5_ERR P4_ERR P3_ERR P2_ERR P1_ERR P0_ERR Bits Name Description Type Reset Value 0 15 Reserved N A R 0 16 P15_ERR Port 15 violated the maximum multicast latency time and will not be multicast to R W1C 0 17 P14_ERR Port 14 violated the maximum multicast latency time and will not be multicast to R W1C 0 18 P13_ERR Port 13 violated the maximum multicast latency time and w...

Page 385: ...0 27 P4_ERR Port 4 violated the maximum multicast latency time and will not be multicast to R W1C 0 28 P3_ERR Port 3 violated the maximum multicast latency time and will not be multicast to R W1C 0 29 P2_ERR Port 2 violated the maximum multicast latency time and will not be multicast to R W1C 0 30 P1_ERR Port 1 violated the maximum multicast latency time and will not be multicast to R W1C 0 31 P0_...

Page 386: ...000_0000 Register offset 1AA0C Bits 0 1 2 3 4 5 6 7 00 07 Reserved 08 15 Reserved 16 23 P15_SET P14_SET P13_SET P12_SET P11_SET P10_SET P9_SET P8_SET 24 31 P7_SET P6_SET P5_SET P4_SET P3_SET P2_SET P1_SET P0_SET Bits Name Description Type Reset Value 0 15 Reserved N A R 0 16 P15_SET Port 15 multicast mask is overridden once every time this bit is written as a 1 R W1S 0 17 P14_SET Port 14 multicast...

Page 387: ... once every time this bit is written as a 1 R W1S 0 27 P4_SET Port 4 multicast mask is overridden once every time this bit is written as a 1 R W1S 0 28 P3_SET Port 3 multicast mask is overridden once every time this bit is written as a 1 R W1S 0 29 P2_SET Port 2 multicast mask is overridden once every time this bit is written as a 1 R W1S 0 30 P1_SET Port 1 multicast mask is overridden once every ...

Page 388: ...PORT7 PORT6 PORT5 PORT4 PORT3 PORT2 PORT1 PORT0 Bits Name Description Type Reset Value 0 3 Reserved N A Note These upper 4 bits are reserved in order to be compatible with the I2C IP Refer to the I2C Chapter R 0 4 RCS Combined 4 Reset Control Symbols interrupt status from all ports R 0 5 MCS Combined Multicast Event Control Symbol interrupt status from all ports R 0 6 I2C I2 C Interrupt Port R 0 7...

Page 389: ...t R 0 21 PORT10 Port 10 Interrupt R 0 22 PORT9 Port 9 Interrupt R 0 23 PORT8 Port 8 Interrupt R 0 24 PORT7 Port 7 Interrupt R 0 25 PORT6 Port 6 Interrupt R 0 26 PORT5 Port 5 Interrupt R 0 27 PORT4 Port 4 Interrupt R 0 28 PORT3 Port 3 Interrupt R 0 29 PORT2 Port 2 Interrupt R 0 30 PORT1 Port 1 Interrupt R 0 31 PORT0 Port 0 Interrupt R 0 Continued Bits Name Description Type Reset Value ...

Page 390: ..._EN PORT5_EN PORT4_EN PORT3_EN PORT2_EN PORT1_EN PORT0_EN Bits Name Description Type Reset Value 0 3 Reserved N A R 0 4 RCS_EN Four Reset Control Symbols Interrupt Enable R W 0 5 MCS_EN Multicast Event Control Symbol Interrupt Enable R W 0 6 I2C_EN I2C Interrupt Port Enable R W 0 7 TEA_EN TEA interrupt Enable R W 0 8 13 Reserved N A R 0 14 MC_LAT_EN Multicast Latency Interrupt Enable R W 0 15 Rese...

Page 391: ... Enable R W 0 25 PORT6_EN Port 6 Interrupt Enable R W 0 26 PORT5_EN Port 5 Interrupt Enable R W 0 27 PORT4_EN Port 4 Interrupt Enable R W 0 28 PORT3_EN Port 3 Interrupt Enable R W 0 29 PORT2_EN Port 2 Interrupt Enable R W 0 30 PORT1_EN Port 1 Interrupt Enable R W 0 31 PORT0_EN Port 0 Interrupt Enable R W 0 Continued Bits Name Description Type Reset Value ...

Page 392: ...AC14 Bits 0 1 2 3 4 5 6 7 00 07 PW_TIMER Reserved 08 15 Reserved 16 23 Reserved 24 31 Reserved Bits Name Description Type Reset Value 0 3 PW_TIMER Port write Timer This field defines the time period to repeat sending an error reporting port write request for software assistance The timer is stopped by software writing to the error detect registers The timeout value is computed by 167772160 ns x pw...

Page 393: ...a port write is sent any remaining port write requests from any port sets a bit in the register Register name RIO_PW_OREQ_STATUS Reset value 0x0000_0000 Register offset 1AC18 Bits 0 1 2 3 4 5 6 7 00 07 Reserved 08 15 Reserved 16 23 PORTX_OREG 24 31 PORTX_OREG Bits Name Description Type Reset Value 0 15 Reserved N A R 0 16 31 PORTX_OREG Port x Port Write Outstanding Request When a bit is set it ind...

Page 394: ...served MCES_CTRL Reserved 08 15 Reserved 16 23 Reserved 24 31 Reserved Bits Name Description Type Reset Value 0 1 Reserved N A R 0 2 3 MCES_CTRL MCES Pin Control 00 Disabled The MCES pin does not affect generation or receipt of Multicast Event Control Symbol 01 MCES pin is an input see Generating an MCS on page 56 10 MCES pin is an output see MCS Reception on page 55 11 Reserved R W 0 4 31 Reserve...

Page 395: ...sion of the IDT specific registers that is supported by this device Register name RIO 0 15 _MC_REG_VER Reset value 0x0000_0001 Register offset 1B000 1B100 1B200 1B300 1B400 1B500 1B600 1B700 1B800 1B900 1BA00 1BB00 1BC00 1BD00 1BE00 1BF00 Bits 0 1 2 3 4 5 6 7 00 07 Reserved 08 15 Reserved 16 23 Reserved 24 31 REG_VER Bits Name Description Type Reset Value 0 23 Reserved N A R 0 24 31 REG_VER IDT MC...

Page 396: ...e 0 Do not remove port from multicast operations if the multicast maximum latency timer expires for this port 1 Remove this port from future multicast operations if the multicast maximum latency timer expires for this port R W 0 1 7 Reserved N A R 0 8 31 MAX_MC_L AT The time period after which the oldest packet copy residing in the broadcast buffer is deemed to have expired If MAX_MC_LAT 0x0000 th...

Page 397: ...2 packets are accepted if the number of free buffer is greater than this value This value must be smaller than PRIO1WM Note It is a programming error for this value to be either greater than or equal to PRIO1WM or PRIO0WM or greater than 7 R W 0x1 16 20 Reserved N A R 0 21 23 PRIO1WM Priority 1 packets are accepted if the number of free buffer is greater than this value This value must be smaller ...

Page 398: ... 1B910 1BA10 1BB10 1BC10 1BD10 1BE10 1BF10 Bits 0 1 2 3 4 5 6 7 00 07 Reserved WRR_EN CHOOSE_ UC 08 15 Reserved 16 23 Reserved 24 31 Reserved WEIGHT Bits Name Description Type Reset Value 0 5 Reserved N A R 0 6 WRR_EN Weighted Round Robin Enable 0 Weighted Round Robin is disabled and no preference is given to multicast nor unicast packets The registers WEIGHT and CHOOSE_UC have no effect 1 Weight ...

Page 399: ...BB14 1BC14 1BD14 1BE14 1BF14 Bits 0 1 2 3 4 5 6 7 00 07 Reserved WRR_EN CHOOSE_ UC 08 15 Reserved 16 23 Reserved 24 31 Reserved WEIGHT Bits Name Description Type Reset Value 0 5 Reserved N A R 0 6 WRR_EN Weighted Round Robin Enable 0 Weighted Round Robin is disabled and no preference is given to multicast nor unicast packets The registers WEIGHT and CHOOSE_UC have no effect 1 Weight Round Robin is...

Page 400: ...BB18 1BC18 1BD18 1BE18 1BF18 Bits 0 1 2 3 4 5 6 7 00 07 Reserved WRR_EN CHOOSE_ UC 08 15 Reserved 16 23 Reserved 24 31 Reserved WEIGHT Bits Name Description Type Reset Value 0 5 Reserved N A R 0 6 WRR_EN Weighted Round Robin Enable 0 Weighted Round Robin is disabled and no preference is given to multicast nor unicast packets The registers WEIGHT and CHOOSE_UC have no effect 1 Weight Round Robin is...

Page 401: ...BB1C 1BC1C 1BD1C 1BE1C 1BF1C Bits 0 1 2 3 4 5 6 7 00 07 Reserved WRR_EN CHOOSE_ UC 08 15 Reserved 16 23 Reserved 24 31 Reserved WEIGHT Bits Name Description Type Reset Value 0 5 Reserved N A R 0 6 WRR_EN Weighted Round Robin Enable 0 Weighted Round Robin is disabled and no preference is given to multicast nor unicast packets The registers WEIGHT and CHOOSE_UC have no effect 1 Weight Round Robin is...

Page 402: ...es The SerDes is fully initialized when MPLL_PWR_ON is equal to 1 see SRIO MAC x SerDes Configuration Global on page 372 The SerDes register offsets in this section are based on lane 0 In order to define lanes 1 2 and 3 the offset is incremented by 0x40 for each lane For example 0x1E000 represents lane 0 of SerDes 0 0x1E040 represents lane 1 of SerDes 0 0x1E080 represents lane 2 of SerDes 0 and 0x...

Page 403: ...Reserved 16 23 Reserved PAT0 24 31 PAT0 TRIGGER_ ERR MODE Bits Name Description Type Reset Value 0 17 Reserved NA R 0x0 18 27 PAT0 Pattern for MODE setting 3 5 Program the desired pattern in these 10bits when using modes 3 5 Note This field returns to its reset value on reset R W 0x0 28 TRIGGER_E RR Insert a single error into a LSB Note This field returns to its reset value on reset R W 0x0 29 31 ...

Page 404: ...Reserved 16 23 Reserved PAT0 24 31 PAT0 TRIGGER_ ERR MODE Bits Name Description Type Reset Value 0 17 Reserved NA R 0x0 18 27 PAT0 Pattern for MODE setting 3 5 Program the desired pattern in these 10bits when using modes 3 5 Note This field returns to its reset value on reset R W 0x0 28 TRIGGER_E RR Insert a single error into a LSB Note This field returns to its reset value on reset R W 0x0 29 31 ...

Page 405: ...Reserved 16 23 Reserved PAT0 24 31 PAT0 TRIGGER_ ERR MODE Bits Name Description Type Reset Value 0 17 Reserved NA R 0x0 18 27 PAT0 Pattern for MODE setting 3 5 Program the desired pattern in these 10bits when using modes 3 5 Note This field returns to its reset value on reset R W 0x0 28 TRIGGER_E RR Insert a single error into a LSB Note This field returns to its reset value on reset R W 0x0 29 31 ...

Page 406: ...Reserved 16 23 Reserved PAT0 24 31 PAT0 TRIGGER_ ERR MODE Bits Name Description Type Reset Value 0 17 Reserved NA R 0x0 18 27 PAT0 Pattern for MODE setting 3 5 Program the desired pattern in these 10bits when using modes 3 5 Note This field returns to its reset value on reset R W 0x0 28 TRIGGER_E RR Insert a single error into a LSB Note This field returns to its reset value on reset R W 0x0 29 31 ...

Page 407: ...signal overflows Note Read operations on this register is pipelined Two reads needed to get current value The values are volatile and the value may change at any time R W 0x0 1 15 COUNT Current error count If OV14 field is active multiply count by 128 Note Read operation on this register is pipelined Two reads needed to get current value The values are volatile that is value may change at any time...

Page 408: ...1 and count 215 1 signal overflows Note Read operations on this register is pipelined Two reads needed to get current value The values are volatile and the value may change at any time R W 0x0 1 15 COUNT Current error count If OV14 field is active multiply count by 128 Note Read operation on this register is pipelined Two reads needed to get current value The values are volatile that is value may ...

Page 409: ...1 and count 215 1 signal overflows Note Read operations on this register is pipelined Two reads needed to get current value The values are volatile and the value may change at any time R W 0x0 1 15 COUNT Current error count If OV14 field is active multiply count by 128 Note Read operation on this register is pipelined Two reads needed to get current value The values are volatile that is value may ...

Page 410: ...1 and count 215 1 signal overflows Note Read operations on this register is pipelined Two reads needed to get current value The values are volatile and the value may change at any time R W 0x0 1 15 COUNT Current error count If OV14 field is active multiply count by 128 Note Read operation on this register is pipelined Two reads needed to get current value The values are volatile that is value may ...

Page 411: ...he reference Note Read operations on this register is pipelined Two reads needed to get current value The values are volatile and the value may change at any time R W 0x0 15 DTHR_0 Bits below the useful resolution Note Read operations on this register is pipelined Two reads needed to get current value The values are volatile and the value may change at any time R W 0 16 20 Reserved NA R 0x0 21 30 ...

Page 412: ...he reference Note Read operations on this register is pipelined Two reads needed to get current value The values are volatile and the value may change at any time R W 0x0 15 DTHR_0 Bits below the useful resolution Note Read operations on this register is pipelined Two reads needed to get current value The values are volatile and the value may change at any time R W 0 16 20 Reserved NA R 0x0 21 30 ...

Page 413: ...he reference Note Read operations on this register is pipelined Two reads needed to get current value The values are volatile and the value may change at any time R W 0x0 15 DTHR_0 Bits below the useful resolution Note Read operations on this register is pipelined Two reads needed to get current value The values are volatile and the value may change at any time R W 0 16 20 Reserved NA R 0x0 21 30 ...

Page 414: ...he reference Note Read operations on this register is pipelined Two reads needed to get current value The values are volatile and the value may change at any time R W 0x0 15 DTHR_0 Bits below the useful resolution Note Read operations on this register is pipelined Two reads needed to get current value The values are volatile and the value may change at any time R W 0 16 20 Reserved NA R 0x0 21 30 ...

Page 415: ...range within a consecutive 256 byte address space For peripheral addresses the lowest address maps to the least significant byte of the internal register LSB while the highest address maps to the most significant byte of the internal register MSB Tip The internal address for the I2 C registers is 0x1D000 to 0x1DFFC Table 49 I2 C Register Map Internal Address Peripheral Address Register Name See 0x...

Page 416: ...e I2C Internal Read Data Register 0x1D218 0x1D21C 0x18 0x1F Reserved 0x1D220 0x20 0x23 EXI2C_ACC_STAT Externally Visible I2 C Slave Access Status Register 0x1D224 0x24 0x27 EXI2C_ACC_CNTRL Externally Visible I2C Internal Access Control Register 0x1D228 0x1D27C 0x28 0x7F Reserved 0x1D280 0x80 0x83 EXI2C_STAT Externally Visible I2 C Status Register 0x1D284 0x84 0x87 EXI2C_STAT_ENABLE Externally Visi...

Page 417: ..._SD Setup and Hold Timing Register 0x1D34C n a I2C_SCL_PERIOD I2C_SCLK High and Low Timing Register 0x1D350 n a I2C_SCL_MIN_PERIOD I2C_SCLK Minimum High and Low Timing Register 0x1D354 n a I2C_SCL_ARB_TIMEOUT I2C_SCLK Low and Arbitration Timeout Register 0x1D358 n a I2C_BYTE_TRAN_TIMEOUT I2 C Byte Transaction Timeout Register 0x1D35C n a I2C_BOOT_DIAG_TIMER I2C Boot and Diagnostic Timer 0x1D360 0x...

Page 418: ...y a chip reset 13 2 1 I2 C Device ID Register This register identifies the version of the IDT I2C block in this device Register name I2C_DEVID Reset value 0x0000_0001 Register offset 0x1D100 Bits 0 1 2 3 4 5 6 7 00 07 Reserved 08 15 Reserved 16 23 Reserved 24 31 Reserved REV Bits Name Description Type Reset Value 00 27 Reserved Reserved R 0x000_0000 28 31 REV Indicates the revision ID for the I2 C...

Page 419: ...d to be unaffected by this reset Register name I2C_RESET Reset value 0x0000_0000 Register offset 0x1D104 Bits 0 1 2 3 4 5 6 7 00 07 SRESET Reserved 08 15 Reserved 16 23 Reserved 24 31 Reserved Bits Name Description Type Reset Value 00 SRESET Reset under Software Control Setting this bit resets the I2C block The R W fields of configuration and control registers are not affected nor is this register...

Page 420: ...processed from MSB to LSB within an I2 C transaction 1 Data from to data registers is ordered processed from LSB to MSB within an I2 C transaction Data registers are I2 C Master Transmit Data Register and I2 C Master Receive Data Register R W 0 09 13 Reserved Reserved R 0x00 14 15 PA_SIZE Peripheral Address Size 00 No peripheral address used 01 8 bit peripheral device addressing using LSB of PADDR...

Page 421: ...ers Register Descriptions 421 Tsi578 User Manual June 6 2016 Integrated Device Technology www idt com Do not change this register while a master operation is active The effect on the transaction cannot be determined ...

Page 422: ...CNTRL Reset value 0x0000_0000 Register offset 0x1D10C Bits 0 1 2 3 4 5 6 7 00 07 START WRITE Reserved SIZE 08 15 Reserved 16 23 PADDR 24 31 PADDR Bits Name Description Type Reset Value 00 START Start Operation 0 I2 C operation is not in progress self clears 1 Start of an I2 C operation Clears itself back to zero when the initiated operation has completed This bit cannot be cleared by software once...

Page 423: ...ue of 000 should not be normally used for a Read operation as any device put into read mode assumes at least one byte will be read An exception would be the SMBus Quick Command protocol to a device that is known to not hold the bus following the slave address phase R W 000 08 15 Reserved Reserved R 0 16 31 PADDR Peripheral address for master operation If PA_SIZE in the I2 C Master Configuration Re...

Page 424: ...ait for ACK If PA_SIZE is 00 or 11 this phase is skipped Any loss of arbitration will abort with MCOL Any NACK will abort with MNACK 4 Send Data WRITE 1 If SIZE 0 send SIZE bytes from I2C_MST_TDATA based on DORDER Wait for ACK from each This phase is skipped if WRITE 1 Any loss of arbitration will abort with MCOL Any NACK will abort with MNACK 5 Read Data Setup WRITE 0 Send RESTART Repeat the Addr...

Page 425: ...ORDER is 1 bytes are loaded from LSB to MSB in order RBYTE0 RBYTE1 RBYTE2 RBYTE3 If the transaction size is less than four 4 bytes that is SIZE in the I2C Master Control Register 4 then any remaining bytes in the register are left unchanged that is they retain the values they had from the prior read operation Register name I2C_MST_RDATA Reset value 0x0000_0000 Register offset 0x1D110 Bits 0 1 2 3 ...

Page 426: ...RDER is 1 bytes are taken from LSB to MSB in order TBYTE0 TBYTE1 TBYTE2 TBYTE3 If the transaction size is less than 4 bytes that is SIZE in the I2 C Master Control Register 4 then any remaining bytes in the register are unused The contents of this register are not affected by the transaction Register name I2C_MST_TDATA Reset value 0x0000_0000 Register offset 0x1D114 Bits 0 1 2 3 4 5 6 7 00 07 TBYT...

Page 427: ...YTES Bits Name Description Type Reset Value 00 SLV_ACTIVE Slave Active 0 Slave is not addressed 1 Slave is addressed by external master and a read or write is active on the bus This bit is set following the slave address phase if the address matched the SLV_ADDR or Alert Response Address and the slave interface was enabled Note This bit is zeroed on a reset controlled by the I2C Reset Register R 0...

Page 428: ...aster 11 Data outgoing read by external master At the end of a slave operation this field will hold its value until the next START RESTART If a slave operation aborts this field will qualify where in the transaction the error occurred R 0x0 07 SLV_AN Slave Ack Nack 0 Slave transaction is not in the ACK NACK bit of a byte 1 Slave transaction is in the ACK NACK bit of a byte This qualifies the SLV_P...

Page 429: ...orts this field will qualify where in the transaction the error occurred R 000 23 MST_AN Master Ack Nack 0 Master transaction is not in the ACK NACK bit of a byte 1 Master transaction is in the ACK NACK bit of a byte This qualifies the MST_PHASE field R 0 24 27 Reserved Reserved R 0x0 28 31 MST_ NBYTES Master Number of Bytes This is the running count of the number of data bytes transferred in the ...

Page 430: ...et Register is de asserted Register name I2C_INT_STAT Reset value 0x0000_0000 Register offset 0x1D11C Bits 0 1 2 3 4 5 6 7 00 07 Reserved OMB_ EMPTY IMB_FULL 08 15 Reserved BL_FAIL BL_OK 16 23 Reserved SA_ FAIL SA_ WRITE SA_READ SA_OK 24 31 MA_DIAG Reserved MA_COL MA_TMO MA_NACK MA_ATMO MA_OK Bits Name Description Type Reset Value 0 5 Reserved Reserved R 0x00 6 OMB_EMPTY Outgoing Mailbox Empty 0 I...

Page 431: ...n by an external master invoking a write to an internal register This will not assert if slave writes are disabled WR_EN in the I2 C Slave Configuration Register 0 R W1C 0 22 SA_READ Slave Read 0 Interrupt status not asserted 1 Internal register read performed The Externally Visible I2C Internal Read Data Register was read by an external master invoking a read to an internal register This will not...

Page 432: ... W1C 0 29 MA_NACK Master NACK 0 Interrupt status not asserted 1 NACK received during transaction A transaction initiated through the I2 C Master Control Register aborted due to receipt of a NACK in response to slave address peripheral address or a written byte This can also be set at the end of boot load due to BL_FAIL R W1C 0 30 MA_ATMO Master Arbitration Timeout 0 Interrupt status not asserted 1...

Page 433: ...served BL_FAIL BL_OK 16 23 Reserved SA_ FAIL SA_ WRITE SA_READ SA_OK 24 31 MA_DIAG Reserved MA_COL MA_TMO MA_NACK MA_ATMO MA_OK Bits Name Description Type Reset Value 0 5 Reserved Reserved R 0x00 6 OMB_ EMPTY Enable OMB_EMPTY Interrupt 0 Interrupt is disabled 1 Interrupt is enabled R W 0 7 IMB_FULL Enable IMB_FULL Interrupt 0 Interrupt is disabled 1 Interrupt is enabled R W 0 8 13 Reserved Reserve...

Page 434: ...Enable MA_DIAG Interrupt 0 Interrupt is disabled 1 Interrupt is enabled R W 0 25 26 Reserved Reserved R 00 27 MA_COL Enable MA_COL Interrupt 0 Interrupt is disabled 1 Interrupt is enabled R W 0 28 MA_TMO Enable MA_TMO Interrupt 0 Interrupt is disabled 1 Interrupt is enabled R W 0 29 MA_NACK Enable MA_NACK Interrupt 0 Interrupt is disabled 1 Interrupt is enabled R W 0 30 MA_ATMO Enable MA_ATMO Inte...

Page 435: ...et value 0x0000_0000 Register offset 0x1D124 Bits 0 1 2 3 4 5 6 7 00 07 Reserved OMB_ EMPTY IMB_ FULL 08 15 Reserved BL_FAIL BL_OK 16 23 Reserved SA_FAIL SA_ WRITE SA_READ SA_OK 24 31 MA_DIAG Reserved MA_COL MA_TMO MA_NACK MA_ATMO MA_OK Bits Name Description Type Reset Value 0 5 Reserved Reserved R 0x00 6 OMB_EMPTY Set OMB_EMPTY Interrupt 0 No effect 1 Interrupt is set R W1S 0 7 IMB_FULL Set IMB_F...

Page 436: ...is set R W1S 0 24 MA_DIAG Set MA_DIAG Interrupt 0 No effect 1 Interrupt is set R W1S 0 25 26 Reserved Reserved R 00 27 MA_COL Set MA_COL Interrupt 0 No effect 1 Interrupt is set R W1S 0 28 MA_TMO Set MA_TMO Interrupt 0 No effect 1 Interrupt is set R W1S 0 29 MA_NACK Set MA_NACK Interrupt 0 No effect 1 Interrupt is set R W1S 0 30 MA_ATMO Set MA_ATMO Interrupt 0 No effect 1 Interrupt is set R W1S 0 ...

Page 437: ... effect 0 Transactions that read the Externally Visible I2 C Internal Read Data Register on page 447 will not invoke reads of the internal registers 1 Transactions that read the Externally Visible I2 C Internal Read Data Register on page 447 will trigger reads of the internal register whose address is in the Externally Visible I2 C Internal Read Address Register on page 446 R W 1 1 WR_EN Register ...

Page 438: ...terface is enabled SLV_ADDR is responded to when transaction started by external master When enabled the slave interface will acknowledge transactions to the SLV_ADDR from an external master If not enabled then all transactions are NACK d except the Alert Response Address read if ALRT_EN is 1 This bit controls access to the peripheral address space of the Tsi578 Access to the internal register spa...

Page 439: ... latched at power up from the state of input pins This allows board configuration of up to four unique Tsi578 devices on the I2C bus These two bits are then locked for writing until the SLV_UNLK bit is set to 1 during a write This feature allows the boot load process to write a slave address value to this register without changing the power up latch field A SLV_ADDR of 0x00 is never valid as that ...

Page 440: ...his register can be read and written after boot loading is complete but has no further effect on block operation Register name I2C_BOOT_CNTRL Reset value Undefined Register offset 0x1D140 Bits 0 1 2 3 4 5 6 7 00 07 CHAIN PSIZE BINC BUNLK Reserved 08 15 Reserved BOOT_ADDR 16 23 PAGE_MODE PADDR 24 31 PADDR Bits Name Description Type Reset Value 00 CHAIN Chain During Boot 0 No chain 1 Chain to new de...

Page 441: ...address as a 256 byte page select typically 2K EEPROMs When enabled and the 1 byte peripheral address wraps back to zero the least significant 3 bits of the device address is incremented followed by a Restart and a new device address cycle The device address starts as the value of the BOOT_ADDR field and is copied internally at boot start or upon a chain operation It is the internal value that is ...

Page 442: ...ield R W Undefined 16 18 PAGE_MODE Page Mode 000 8 bytes 001 32 bytes 010 64 bytes 011 128 bytes 100 256 bytes 101 512 bytes 110 1024 bytes 111 Infinite This field modifies the boot load process to adjust the boundary at which the boot device is re addressed In the default case the boot load sequence reads 8 bytes then does a Restart followed by the device and peripheral address phases By changing...

Page 443: ...ral address this field is shifted left by 3 and then copied internally upon boot start or a chain operation The internal address is then incremented as the boot load progresses For 2 byte addressing the MSB of the peripheral address is sent first For example setting this field to 0x0127 gives a peripheral address of 0x0127 3 0x0938 The first byte sent to the external device is 0x09 and the second ...

Page 444: ...e end of the boot load process this register will contain the last register address read from the EEPROM or the first four bytes of the register count Register name EXI2C_REG_WADDR Reset value 0x0000_0000 Register offset 0x1D200 Bits 0 1 2 3 4 5 6 7 00 07 ADDR 08 15 ADDR 16 23 ADDR 24 31 ADDR Reserved Bits Name Description Type Reset Value 0 29 ADDR Internal Register Write Address Register address...

Page 445: ... 31 WDATA Bits Name Description Type Reset Value 0 31 WDATA Internal Register Write Data Data written by the external I2C master to be used for an internal register write When WSIZE is configured for 4 byte access in the Externally Visible I2C Internal Access Control Register on page 450 the contents of this register are written to an internal register when the MSB is written by an external I2C ma...

Page 446: ... Register name EXI2C_REG_RADDR Reset value 0x0000_0000 Register offset 0x1D210 Bits 0 1 2 3 4 5 6 7 00 07 ADDR 08 15 ADDR 16 23 ADDR 24 31 ADDR Reserved Bits Name Description Type Reset Value 0 29 ADDR Internal Register Read Address Register address to be used when a read to the Externally Visible I2 C Internal Read Data Register invokes an internal register read This address is 4 byte aligned The...

Page 447: ...ading this register When RSIZE is configured for 4 byte access in the Externally Visible I2 C Internal Access Control Register on page 450 this register is updated by the read of an internal register when the LSB is read by an external I2 C master peripheral address 0x14 RDATA 24 31 The register bus address is taken from the Externally Visible I2 C Internal Read Address Register on page 446 Reads ...

Page 448: ... 3 4 5 6 7 00 07 Reserved 08 15 Reserved 16 23 Reserved 24 31 ACC_OK Reserved OMB_ FLAG IMB_ FLAG Reserved ALERT_ FLAG Bits Name Description Type Reset Value 00 23 Reserved Reserved R 0x00_0000 24 ACC_OK Internal Register Access OK 0 No access or access in progress 1 Access was successful This bit is set when a slave access successfully reads or writes data to an internal register through the Exte...

Page 449: ...ox This bit is set when data is written to the incoming mailbox register Externally Visible I2C Incoming Mailbox Register by an external I2C master This bit remains set flag up until software reads the incoming mailbox register and the bit is then cleared flag down When the mailbox is written and the flag is set the IMB_FULL interrupt is asserted A mailbox read is considered complete when the exte...

Page 450: ...slave interface This register corresponds to the I2 C peripheral addresses 0x24 through 0x27 Register name EXI2C_ACC_CNTRL Reset value 0x0000_00A0 Register offset 0x1D224 Bits 0 1 2 3 4 5 6 7 00 07 Reserved 08 15 Reserved 16 23 Reserved 24 31 RSIZE WSIZE RINC WINC Reserved Bits Name Description Type Reset Value 00 23 Reserved Reserved R 0x00_0000 24 25 RSIZE Internal Register Read Access Size 00 1...

Page 451: ...ing is on consecutive internal registers can be read in one I2C transaction without the need to reset the peripheral address because the peripheral address wraps from 0x17 back to 0x14 If auto incrementing is off then the same internal register can be read multiple times in a single I2C transaction The latter could be useful for polling a status register R 0 29 WINC Enable Auto Incrementing on Int...

Page 452: ...W1C occurs the bit remains set The software status bits 1 3 are R W from the register bus They can be set or cleared by software and thereby used for any system purpose An external I2 C master can write 1 to those bits to clear them If the W1C occurs at the same time as software is writing the bit the software written value will take precedence This register corresponds to the I2C peripheral addre...

Page 453: ...oing mailbox not filled since last clear 1 Outgoing mailbox is filled This bit asserted indicates that software has written to the outgoing mailbox since this bit was last cleared R 0 5 IMBR Incoming Mailbox Read 0 Incoming mailbox not read since last clear 1 Incoming mailbox is emptied This bit asserted indicates that software has read the incoming mailbox when the mailbox was full since this bit...

Page 454: ... port could not be sent in the required time R 0 15 MCE Multicast Work Queue Dropped Packet Interrupt 0 No interrupt 1 Multicast logic dropped a packet R 0 16 PORT15 Port 15 Interrupt 0 No interrupt 1 Port 15 has asserted an interrupt to the processor R 0 17 PORT14 Port 14 Interrupt 0 No interrupt 1 Port 14 has asserted an interrupt to the processor R 0 18 PORT13 Port 13 Interrupt 0 No interrupt 1...

Page 455: ...ed an interrupt to the processor R 0 26 PORT5 Port 5 Interrupt 0 No interrupt 1 Port 5 has asserted an interrupt to the processor R 0 27 PORT4 Port 4 Interrupt 0 No interrupt 1 Port 4 has asserted an interrupt to the processor R 0 28 PORT3 Port 3 Interrupt 0 No interrupt 1 Port 3 has asserted an interrupt to the processor R 0 29 PORT2 Port 2 Interrupt 0 No interrupt 1 Port 2 has asserted an interr...

Page 456: ... 0x87 Register name EXI2C_STAT_ENABLE Reset value 0xFFFF_FFFF Register offset 0x1D284 Bits 0 1 2 3 4 5 6 7 00 07 RESET SW_ STAT2 SW_ STAT1 SW_ STAT0 OMBW IMBR I2C TEA 08 15 RCS MCS Reserved LOGICAL MC_LAT MCE 16 23 PORT15 PORT14 PORT13 PORT12 PORT11 PORT10 PORT9 PORT8 24 31 PORT7 PORT6 PORT5 PORT4 PORT3 PORT2 PORT1 PORT0 Bits Name Description Type Reset Value 0 RESET Enable RESET Alert Response 0 ...

Page 457: ...erved Reserved These bits are unused in the Tsi578 The enables can be changed but have no effect R W 111 13 LOGICAL Enable LOGICAL Alert Response 0 Status asserted will not enable setting ALERT_FLAG 1 Status asserted will enable setting ALERT_FLAG R W 1 14 MC_LAT Enable MC_LAT Alert Response 0 Status asserted will not enable setting ALERT_FLAG 1 Status asserted will enable setting ALERT_FLAG R W 1...

Page 458: ...LERT_FLAG 1 Status asserted will enable setting ALERT_FLAG R W 1 24 PORT7 Enable PORT7 Alert Response 0 Status asserted will not enable setting ALERT_FLAG 1 Status asserted will enable setting ALERT_FLAG R W 1 25 PORT6 Enable PORT6 Alert Response 0 Status asserted will not enable setting ALERT_FLAG 1 Status asserted will enable setting ALERT_FLAG R W 1 26 PORT5 Enable PORT5 Alert Response 0 Status...

Page 459: ...able PORT1 Alert Response 0 Status asserted will not enable setting ALERT_FLAG 1 Status asserted will enable setting ALERT_FLAG R W 1 31 PORT0 Enable PORT0 Alert Response 0 Status asserted will not enable setting ALERT_FLAG 1 Status asserted will enable setting ALERT_FLAG R W 1 Continued Bits Name Description Type Reset Value ...

Page 460: ... 1 2 3 4 5 6 7 00 07 DATA 08 15 DATA 16 23 DATA 24 31 DATA Bits Name Description Type Reset Value 0 31 DATA Mailbox data to be transferred to an external I2 C master Every write to this register by software sets the OMB_FLAG bit in the Externally Visible I2 C Slave Access Status Register indicating data is available in the outgoing mailbox When this register is read by an external master the OMB_F...

Page 461: ...is register corresponds to the I2 C peripheral addresses 0x94 through 0x97 Register name EXI2C_MBOX_IN Reset value 0x0000_0000 Register offset 0x1D294 Bits 0 1 2 3 4 5 6 7 00 07 DATA 08 15 DATA 16 23 DATA 24 31 DATA Bits Name Description Type Reset value 0 31 DATA Mailbox data transferred from an external I2 C master Every write to this register sets the IMB_FLAG in the Externally Visible I2 C Sla...

Page 462: ... corresponding bits in the I2C Enable Event Register and then determine whether a related bit in the I2C_INT_STAT register is set Note These registers are affected by a reset controlled by the I2 C Reset Register All events will be cleared and will not assert while SRESET is asserted in the I2 C Reset Register Register name I2C_ EVENT SNAP_EVENT Reset value 0x0000_0000 Register offset 0x1D300 1D30...

Page 463: ...ming mailbox R W1C 0 09 OMBR Outgoing Mailbox Read Event 0 Event not asserted 1 Slave interface completed a read transaction to the outgoing mailbox when the OMB_FLAG was set The event is asserted only if the mailbox was full R W1C 0 10 Reserved Reserved R 0 11 SCOL Slave Collision Detect Event 0 Event not asserted 1 Slave interface detected a bit collision on the I2 C bus during a slave transacti...

Page 464: ...ad Error Event 0 Event not asserted 1 The boot load sequence failed due to an error during register reading a protocol error NACK when ACK expected an I2C_SCLK low timer collision after the device addressing phase or the last six bytes of a register count field not being 0xFF This error will be qualified by the MNACK MCOL or MSCLTO event The last data read from the EEPROM is visible in the EXI2C_R...

Page 465: ...ame slave device This event can also assert during boot load and provides more information on the source of a BLERR event R W1C 0 28 MTRTO Master Transaction Timeout Event 0 Event not asserted 1 Transaction timeout timer expired during a transaction initiated through the I2C Master Control Register R W1C 0 29 MBTTO Master Byte Timeout Event 0 Event not asserted 1 Byte timeout timer expired during ...

Page 466: ... SRESET is asserted in the I2C Reset Register Register name I2C_NEW_EVENT Reset value 0x0000_0000 Register offset 0x1D308 Bits 0 1 2 3 4 5 6 7 00 07 Reserved SDW SDR SD Reserved DTIMER DHIST DCMDD 08 15 IMBW OMBR Reserved SCOL STRTO SBTTO SSCLTO Reserved 16 23 Reserved MTD Reserved BLTO BLERR BLSZ BLNOD BLOK 24 31 Reserved MNACK MCOL MTRTO MBTTO MSCLTO MARBTO Bits Name Description Type Reset Value...

Page 467: ... not asserted 1 Event asserted R W1S 0 12 STRTO Slave Transaction Timeout Event 0 Event not asserted 1 Event asserted R W1S 0 13 SBTTO Slave Byte Timeout Event 0 Event not asserted 1 Event asserted R W1S 0 14 SSCLTO Slave I2C_SCLK Low Timeout Event 0 Event not asserted 1 Event asserted R W1S 0 15 16 Reserved Reserved R 00 17 MTD Master Transaction Done Event 0 Event not asserted 1 Event asserted R...

Page 468: ...ved R 00 26 MNACK Master NACK Received Event 0 Event not asserted 1 Event asserted R W1S 0 27 MCOL Master Collision Detect Event 0 Event not asserted 1 Event asserted R W1S 0 28 MTRTO Master Transaction Timeout Event 0 Event not asserted 1 Event asserted R W1S 0 29 MBTTO Master Byte Timeout Event 0 Event not asserted 1 Event asserted R W1S 0 30 MSCLTO Master I2C_SCLK Low Timeout Event 0 Event not ...

Page 469: ...O MARBTO Bits Name Description Type Reset Value 00 Reserved Reserved R 0 01 SDW Slave Internal Register Write Done Enable 0 Event does not assert to interrupt status 1 Event will assert in interrupt status R W 1 02 SDR Slave Internal Register Read Done Enable 0 Event does not assert to interrupt status 1 Event will assert in the interrupt status R W 1 03 SD Slave Transaction Done Enable 0 Event do...

Page 470: ...TO Slave Byte Timeout Enable 0 Event does not assert to interrupt status 1 Event will assert in the interrupt status R W 1 14 SSCLTO Slave I2C_SCLK Low Timeout Enable 0 Event does not assert to interrupt status 1 Event will assert in the interrupt status R W 1 15 16 Reserved Reserved R 00 17 MTD Master Transaction Done Enable 0 Event does not assert to interrupt status 1 Event will assert in the i...

Page 471: ...1 27 MCOL Master Collision Detect Enable 0 Event does not assert to interrupt status 1 Event will assert in the interrupt status R W 1 28 MTRTO Master Transaction Timeout Enable 0 Event does not assert to interrupt status 1 Event will assert in the interrupt status R W 1 29 MBTTO Master Byte Timeout Enable 0 Event does not assert to interrupt status 1 Event will assert in the interrupt status R W ...

Page 472: ...Type Reset Value 00 03 Reserved Reserved R 0x0 04 15 USDIV Period Divider for Micro Second Based Timers This field divides the reference clock down for use by the Idle Detect Timer the Byte Timeout Timer the I2C_SCLK Low Timeout Timer and the Milli Second Period Divider Period USDIV Period P_CLK USDIV 1 where P_CLK is 10 ns Reset period is 1 microsecond R W 0x0063 16 19 Reserved Reserved R 0x0 20 ...

Page 473: ... 07 START_SETUP 08 15 START_SETUP 16 23 START_HOLD 24 31 START_HOLD Bits Name Description Type Reset Value 00 15 START_SETUP Count for the START Condition Setup Period Defines the minimum setup time for the START condition that is both I2C_SCLK and I2C_SD seen high prior to I2C_SD pulled low This is a master only timing parameter This value also doubles as the effective Stop Hold time Period START...

Page 474: ... STOP Condition Setup Period Defines the minimum setup time for the STOP condition that is both I2C_SCLK seen high and I2C_SD seen low prior to I2C_SD released high This is a master only timing parameter Period STOP_SETUP STOP_SETUP Period P_CLK where P_CLK is 10ns Reset time is 4 01 microseconds R W 0x0191 16 31 IDLE_DET Count for Idle Detect Period Used in two cases First defines the period afte...

Page 475: ...e I2C_SD Setup Period Defines the minimum setup time for the I2C_SD signal that is I2C_SD set to desired value prior to rising edge of I2C_SCLK This applies to both slave and master interface Note This value should be set to the sum of the I2C_SD setup time and the maximum rise fall time of the I2C_SD signal to ensure that the signal is valid on the output at the correct time This time is differen...

Page 476: ...3 SCL_LOW 24 31 SCL_LOW Bits Name Description Type Reset Value 00 15 SCL_HIGH Count for I2C_SCLK High Period Defines the nominal high period of the clock from rising edge to falling edge of I2C_SCLK This is a master only parameter The observed period may be shorter if other devices pull the clock low Period SCL_HIGH SCL_HIGH Period P_CLK where P_CLK is 10 ns Reset time is 5 00 microseconds 100 kHz...

Page 477: ...MINL 24 31 SCL_MINL Bits Name Description Type Reset Value 00 15 SCL_MINH Count for I2C_SCLK High Minimum Period Defines the minimum high period of the clock from rising edge seen high to falling edge of I2C_SCLK This is a master only parameter The observed period may be shorter if other devices pull the clock low Period SCL_MINH SCL_MINH Period P_CLK where P_CLK is 10 ns Reset time is 4 01 micros...

Page 478: ...d from I2C_SCLK falling edge to the next I2C_SCLK rising edge Value 0x0 disables the timeout Period SCL_TO SCL_TO Period USDIV where USDIV is the microsecond time defined in the I2C Time Period Divider Register The reset value of this timeout is 26 000 microseconds 26 milliseconds R W 0x65BB 16 31 ARB_TO Count for Arbitration Timeout Period Defines the maximum amount of time for the master interfa...

Page 479: ...amount of time for a byte to be transferred on the I2C bus This covers the period from Start condition to next ACK NACK between two successive ACK NACK bits or from ACK NACK to Stop Restart condition A value of 0 disables the timeout Period BYTE_TO BYTE_TO Period USDIV where USDIV is the microsecond time defined in I2 C Time Period Divider Register This timeout is disabled on reset and is not used...

Page 480: ...er Initial reset value is used for overall boot load timeout During normal operation this timer can be used for any general purpose timing A value of 0 disables the timeout Period DTIMER COUNT Period MSDIV where MSDIV is the millisecond period define in I2 C Time Period Divider Register Timer begins counting when this register is written If this register is written while the counter is running the...

Page 481: ...uence This register is initialized to the count read from the first two bytes of the EEPROM after reset or to the first two byte read after a boot chaining operation The field counts down as each register address data pair is read R 0x0000_000 0 16 31 PADDR Peripheral Address Value of current peripheral address used by the boot load sequence This field is initialized to zero at reset and increment...

Page 482: ...t Disabled 0 Boot enabled 1 Boot disabled R Undefined 02 PASIZE Peripheral Address Size 0 1 byte peripheral address 1 2 byte peripheral address Note This is the state of the I2C_BOOT_CNTRL PSIZE field at boot load start or after a chain operation R Undefined 03 PINC Page Increment 0 Page increment disabled 1 Page increment enabled R 0 04 24 Reserved Reserved R 0x000 25 31 BOOT_ADDR Boot Device Add...

Page 483: ...in the Logical Common Transport and Physical Layer specifications TheTsi578 fully manages the end to end link on each port A 1 Protocol The RapidIO Physical Layer 1x 4x LP Serial specification defines the protocol for packet delivery between serial RapidIO devices including packet and control symbol transmission flow control error management and other device to device functions A particular device...

Page 484: ... for the 1x and 4x interfaces and defines the link initialization sequence for clock synchronization The PCS function is also responsible for idle sequence generation encoding for transmission and lane striping and decoding lane alignment and de striping on reception The PCS layer also provides methods for determining the operational mode of the port as 4 lane or 1 lane operation and means to dete...

Page 485: ... Code Group Use Number of Groups Encoding 8 bit Value PD packet delimiter 1 K28 3 0x7C SC start of Control Symbol 1 K28 0 0x1C I 1x Idle K or R or A see below 0xBC or 0xFD or 0xFB K 1x Sync 1 K28 5 0xBC R 1x Skip 1 K29 7 0xFD A 1x Align 1 K27 7 0xFB I Idle Column K or R or A see below 0xBC or 0xFD or 0xFB K 4x Idle 4 K28 5 K28 5 K2 8 5 K28 5 0xBC on each lane R 4x Sync 4 K29 7 K29 7 K2 9 7 K29 7 0...

Page 486: ...s 5 bits stype0 0 2 definition P 0 P 1 stype1 0 2 cmd CRC 000 pkt accepte d pkt ackID buf_status 001 pkt rtry pkt ackID buf_status 010 pkt not acce pted pkt ackID cause see below 011 reserved 100 status ackID_stat us buf_status 101 reserved 110 link respons e ackID_stat us port_statu s see below 111 reserved pkt not accepted cause 0 4 definition 00000 reserved 00001 recvd unexpected ackID on pkt 0...

Page 487: ...00110 011 11 reserved 10000 OK 10001 111 11 reserved stype1 stype1 0 2 definition cmd 0 2 cmd function pkt delimiter 000 start of pkt 000 reserved yes 001 stomp 000 reserved yes 010 end of pkt 000 reserved yes 011 restart from rtry 000 reserved N A 100 link req 000 010 reserved N A 011 reset device N A 100 input status N A 101 111 reserved N A 101 multicast event 000 reserved no 110 reserved 000 r...

Page 488: ...A Serial RapidIO Protocol Overview Physical Layer 488 Tsi578 User Manual June 6 2016 Integrated Device Technology www idt com ...

Page 489: ...at are outside of the RapidIO specification The ability to support multiple line rates gives the Tsi578 flexibility in both application support and power consumption Table 53 shows the supported line rates for the Tsi578 The Serial Port Select pin SP_IO_SPEED 1 0 must be set to the values shown in Table 53 to achieve the documented line rates Table 53 Tsi578 Supported Line Rates a S_CLK_p n MHz Ba...

Page 490: ... the recommended method B 1 1 1 Modification by EEPROM Boot Load Modifying the EEPROM is the recommended method for using the S_CLK at 125 MHz to create a 3 125 Gbps link baud rate because the EEPROM boot load accesses the required configuration registers before the SerDes are released from reset This can be performed by modifying the EEPROM loading script for more information see EEPROM Scripts i...

Page 491: ...ted in Example Maintenance Transaction Sequence on page 491 Example Maintenance Transaction Sequence The following procedure configures port two After these steps are complete port two can train with its link partner at a baud rate of 3 125Gbps 1 Reset the MAC by asserting SOFT_RST_x4 and leave the IO_SPEED set to 3 125 Write offset 0x132C8 with 0x7FFF0012 2 Set the BYPASS_INIT bit to enable contr...

Page 492: ...SMACx_CFG_GBL register Write offset 0x132C0 with 0x4A060005 Write offset 0x132c0 with 0xCA060005 11 Set the MPLL_PWRON bit in the SMACx_CFG_GLOBAL register Write offset 0x132C0 with 0xCA060085 Ensure that BYPASS_INIT remains asserted 12 Set TX_EN 2 0 to 0b011 in the SMACx_CFG_CH0 3 register Write offset 0x132B0 with 0x203C2513 Write offset 0x132B4 with 0x203C2513 Write offset 0x132B8 with 0x203C25...

Page 493: ...connect Specification Revision 1 3 B 2 1 1 Port Link Time out CSR RapidIO Part 6 1x 4x LP Serial Physical Layer Specification Revision 1 3 Section 6 6 2 2 Port Link Time out CSR Block Offset 0x20 The RapidIO Interconnect Specification Revision 1 3 defines the Port Link Time out CSR as follows The port link time out control register contains the time out timer value for all ports on a device This t...

Page 494: ..._TIMER_EN to be de asserted When the state machine is not in the SILENT state SILENCE_TIMER_DONE is de asserted IDT Implementation The Tsi578 s silence timer does not have user programmable registers The silence timer is sourced from the P_CLK and any changes to P_CLK are directly reflected in the timer timeout period Table 54 Timer Values with P_CLK and TVAL Variations P_CLK Setting TVAL Setting ...

Page 495: ...te and if the link partner supports 4x mode for all four lanes to be aligned The DISCOVERY_TIMER has a default value of 9 decimal but can be programmed to various values The results of changing the DISCOVERY_TIMER value and P_CLK are shown in Table 55 The DISCOVERY_TIMER field is a 4 bit field whose value is used as a pre scaler for a 17 bit counter clocked by P_CLK Table 55 Timer Values with DISC...

Page 496: ...ollowing formula 2 13 DLT_THRESH P_CLK period P_CLK is 100 MHz which gives a P_CLK period of 10nS Default value of DLT_THRESH is 0x7FFF which corresponds to 32767 Using these parameters the populated formula is 8192 32767 10e 9 2 68 seconds When enabled this timer is used to determine when a link is powered up and enabled but dead that is there is no link partner responding When a link is declared...

Page 497: ...or use by the Idle Detect Timer the Byte Timeout Timer the I2C_SCLK Low Timeout Timer and the Milli Second Period Divider Period USDIV Period P_CLK USDIV 1 P_CLK is 10 ns Tsi578 reset value is 0x0063 MSDIV Period Divider for Milli Second Based Timers The MSDIV field divides the USDIV period down further for use by the Arbitration Timeout Timer the Transaction Timeout Timer and the Boot Diagnostic ...

Page 498: ...ing for the Stop condition when generated by the master control logic and the Idle Detect timer The Stop Idle register is broken down as follows The timer period for the STOP_SETUP is relative to the reference clock The timer period for the Idle Detect is relative to the USDIV period The STOP_SETUP time is shadowed during boot loading and can be reprogrammed prior to a chain operation without affe...

Page 499: ...face It is shadowed during boot loading and can be reprogrammed prior to a chain operation without affecting the bus timing for the current EEPROM SDA_SETUP Count for the I2C_SD Setup Period The SDA_SETUP field defines the minimum setup time for the I2C_SD signal that is I2C_SD is set to a desired value prior to rising edge of I2C_SCLK This applies to both slave and master interface Period SDA_SET...

Page 500: ...LOW field defines the nominal low period of the clock from falling edge to rising edge of I2C_SCLK This is a master only parameter The actual observed period may be longer if other devices pull the clock low Period SCL_LOW SCL_LOW Period P_CLK P_CLK is 10 ns Reset time is 5 00 microseconds 100 kHz Tsi578 reset value is 0x01F4 B 2 3 6 I2C_SCLK Minimum High and Low Timing Register The I2C_SCLK Minim...

Page 501: ...he maximum amount of time for a slave device holding the I2C_SCLK signal low This timeout covers the period from I2C_SCLK falling edge to the next I2C_SCLK rising edge A value of 0 disables the timeout Period SCL_TO SCL_TO Period USDIV USDIV is the microsecond time defined in the I2C Time Period Divider Register The reset value of this timeout is 26 milliseconds Tsi578 reset value is 0x65BB ARB_TO...

Page 502: ...e is 0x0000 TRAN_TO Count for Transaction Timeout Period The TRAN_TO field defines the maximum amount of time for a transaction on the I2C bus This covers the period from Start to Stop A value of 0 disables the timeout Period TRAN_TO TRAN_TO Period MSDIV MSDIV is the millisecond time defined in I2C Time Period Divider Register This timeout is disabled on reset and is not used during boot load Tsi5...

Page 503: ...ters reside is a synchronous bus clocked by the P_CLK source A decrease in the P_CLK frequency causes a proportional increase in register access time during RapidIO maintenance transactions JTAG registers accesses and I2C register accesses RapidIO Maintenance Transaction Maintenance transactions use the internal register bus to read and write registers in the Tsi578 If the P_CLK frequency is decre...

Page 504: ...B Clocking P_CLK Programming 504 Tsi578 User Manual June 6 2016 Integrated Device Technology www idt com ...

Page 505: ...ead_prbs_all txt Script C 1 Tsi578_start_prbs_all txt Script This JTAG script is used to turn on the PRBS pattern generator for each lane to be tested The SerDes in a port are offset by 0x40 from the lane 0 register of the port The SerDes Lane 0 Pattern Generator Control Register is located at offset 0x1e020 Therefore lane 1 is located at offset 0x1e060 lane 2 is located at 0x1e0a0 and lane 3 is l...

Page 506: ...00000002 w 1e6e0 00000002 Port 8 w 1e820 00000002 Start 2 7 Pattern Generator w 1e860 00000002 w 1e8a0 00000002 w 1e8e0 00000002 Port a w 1ea20 00000002 Start 2 7 Pattern Generator w 1ea60 00000002 w 1eaa0 00000002 w 1eae0 00000002 Port c w 1ec20 00000002 Start 2 7 Pattern Generator w 1ec60 00000002 w 1eca0 00000002 w 1ece0 00000002 Port e w 1ee20 00000002 Start 2 7 Pattern Generator w 1ee60 00000...

Page 507: ...t 1 25 Gbps PRBS testing at 2 5 or 3 125 Gbps requires the HALF_RATE bit to be cleared The data to be written therefore becomes 0x203CE511 i 0 Port 0 w 130b0 A03CE511 Clear RX_ALIGN_EN w 130b4 A03CE511 w 130b8 A03CE511 w 130bc A03CE511 Port 2 w 132b0 A03CE511 Clear RX_ALIGN_EN w 132b4 A03CE511 w 132b8 A03CE511 w 132bc A03CE511 Port 4 w 134b0 A03CE511 Clear RX_ALIGN_EN w 134b4 A03CE511 w 134b8 A03C...

Page 508: ...511 w 13eb8 A03CE511 w 13ebc A03CE511 C 3 Tsi578_sync_prbs_all txt Script This JTAG script is used to turn on the PRBS pattern matcher for each lane to be tested The SerDes in a port are offset by 0x40 from the lane 0 register of the port The SerDes Lane 0 Pattern Generator Control Register is located at offset 0x1e020 Therefore lane 1 is located at offset 0x1e060 lane 2 is located at 0x1e0a0 and ...

Page 509: ...2b0 0000000a w 1e2f0 0000000a w 1e230 00000002 w 1e270 00000002 w 1e2b0 00000002 w 1e2f0 00000002 Port 4 w 1e430 0000000a Sync pattern matcher w 1e470 0000000a w 1e4b0 0000000a w 1e4f0 0000000a w 1e430 00000002 w 1e470 00000002 w 1e4b0 00000002 w 1e4f0 00000002 Port 6 w 1e630 0000000a Sync pattern matcher w 1e670 0000000a w 1e6b0 0000000a w 1e6f0 0000000a w 1e630 00000002 w 1e670 00000002 w 1e6b0 ...

Page 510: ...000002 w 1e870 00000002 w 1e8b0 00000002 w 1e8f0 00000002 Port a w 1ea30 0000000a Sync pattern matcher w 1ea70 0000000a w 1eab0 0000000a w 1eaf0 0000000a w 1ea30 00000002 w 1ea70 00000002 w 1eab0 00000002 w 1eaf0 00000002 Port c w 1ec30 0000000a Sync pattern matcher w 1ec70 0000000a w 1ecb0 0000000a w 1ecf0 0000000a w 1ec30 00000002 w 1ec70 00000002 w 1ecb0 00000002 w 1ecf0 00000002 Port e w 1ee30...

Page 511: ... Tsi578_read_prbs_all txt Script This script is used to read the PRBS values Note that the PRBS error counter and overflow bit fields must be read twice to determine the correct value The result of the first read is invalid and should be discarded The result of the second read is correct and should be kept Port0 r 1e030 r 1e030 r 1e070 r 1e070 r 1e0b0 r 1e0b0 r 1e0f0 r 1e0f0 Port2 r 1e230 r 1e230 ...

Page 512: ...ne 6 2016 Integrated Device Technology www idt com Port4 r 1e430 r 1e430 r 1e470 r 1e470 r 1e4b0 r 1e4b0 r 1e4f0 r 1e4f0 Port6 r 1e630 r 1e630 r 1e670 r 1e670 r 1e6b0 r 1e6b0 r 1e6f0 r 1e6f0 Port8 r 1e830 r 1e830 r 1e870 r 1e870 r 1e8b0 r 1e8b0 r 1e8f0 r 1e8f0 Porta r 1ea30 ...

Page 513: ...User Manual June 6 2016 Integrated Device Technology www idt com r 1ea30 r 1ea70 r 1ea70 r 1eab0 r 1eab0 r 1eaf0 r 1eaf0 Portc r 1ec30 r 1ec30 r 1ec70 r 1ec70 r 1ecb0 r 1ecb0 r 1ecf0 r 1ecf0 Porte r 1ee30 r 1ee30 r 1ee70 r 1ee70 r 1eeb0 r 1eeb0 r 1eef0 r 1eef0 ...

Page 514: ...C PRBS Scripts Tsi578_read_prbs_all txt Script 514 Tsi578 User Manual June 6 2016 Integrated Device Technology www idt com ...

Page 515: ...ction shows the EEPROM script used in Modification by EEPROM Boot Load D 1 Script ew 0 0047FFFF ew 4 FFFFFFFF 1 ew 8 138c8 ew c 7FFF0012 2 ew 10 138c0 ew 14 CA060084 3 ew 18 138B0 ew 1c 203CA513 4 ew 20 138B4 ew 24 203CA513 5 ew 28 138B8 ew 2c 203CA513 6 ew 30 138BC ew 34 203CA513 7 ew 38 138B0 ew 3c 203C2513 ...

Page 516: ... com 8 ew 40 138B4 ew 44 203C2513 9 ew 48 138B8 ew 4c 203C2513 A ew 50 138BC ew 54 203C2513 B ew 58 138B0 ew 5c 200C2513 C ew 60 138B4 ew 64 200C2513 D ew 68 138B8 ew 6c 200C2513 E ew 70 138BC ew 74 200C2513 F ew 78 138c0 ew 7c CA060004 10 ew 80 138c0 ew 84 CA060044 11 ew 88 138C4 ew 8c 002C0545 ...

Page 517: ... 12 ew 90 138c0 ew 94 CA060045 13 ew 98 138c0 ew 9c CA060005 14 ew a0 138c0 ew a4 4A060005 15 ew a8 138c0 ew ac CA060005 16 ew b0 138c0 ew b4 CA060085 17 ew b8 138B0 ew bc 203C2513 18 ew c0 138B4 ew c4 203C2513 19 ew c8 138B8 ew cc 203C2513 1A ew d0 138BC ew d4 203C2513 1B ew d8 138B0 ew dc 203CA513 ...

Page 518: ... 203CA513 1D ew e8 138B8 ew ec 203CA513 1E ew f0 138BC ew f4 203CA513 1F ew f8 138B0 ew fc 203CE513 20 ew 100 138B4 ew 104 203CE513 21 ew 108 138B8 ew 10c 203CE513 22 ew 110 138BC ew 114 203CE513 23 ew 118 138c8 ew 11c 7FFF0002 24 start of port 6 initialization ew 120 136c8 ew 124 7FFF0012 25 ew 128 136c0 ew 12c CA060084 ...

Page 519: ... 136B0 ew 134 203CA513 27 ew 138 136B4 ew 13c 203CA513 28 ew 140 136B8 ew 144 203CA513 29 ew 148 136BC ew 14c 203CA513 2a ew 150 136B0 ew 154 203C2513 2b ew 158 136B4 ew 15c 203C2513 2c ew 160 136B8 ew 164 203C2513 2d ew 168 136BC ew 16c 203C2513 2e ew 170 136B0 ew 174 200C2513 2f ew 178 136B4 ew 17c 200C2513 ...

Page 520: ... 136B8 ew 184 200C2513 31 ew 188 136BC ew 18c 200C2513 32 ew 190 136c0 ew 194 CA060004 33 ew 198 136c0 ew 19c CA060044 34 ew 1a0 136C4 ew 1a4 002C0545 35 ew 1a8 136c0 ew 1ac CA060045 36 ew 1b0 136c0 ew 1b4 CA060005 37 ew 1b8 136c0 ew 1bc 4A060005 38 ew 1c0 136c0 ew 1c4 CA060005 39 ew 1c8 136c0 ew 1cc CA060085 ...

Page 521: ... 136B0 ew 1d4 203C2513 3b ew 1d8 136B4 ew 1dc 203C2513 3c ew 1e0 136B8 ew 1e4 203C2513 3d ew 1e8 136BC ew 1ec 203C2513 3e ew 1f0 136B0 ew 1f4 203CA513 3f ew 1f8 136B4 ew 1fc 203CA513 40 ew 200 136B8 ew 204 203CA513 41 ew 208 136BC ew 20c 203CA513 42 ew 210 136B0 ew 214 203CE513 43 ew 218 136B4 ew 21c 203CE513 ...

Page 522: ...ripts Script 522 Tsi578 User Manual June 6 2016 Integrated Device Technology www idt com 44 ew 220 136B8 ew 224 203CE513 45 ew 228 136BC ew 22c 203CE513 46 ew 230 136c8 ew 234 7FFF0002 47 ew 238 8 ew 23c deadbeef ...

Page 523: ...mmable Driver Current and Equalization 77 Error Management 57 Error Management of Multicast Packets 118 Multicast Maximum Latency Timer 119 Silent Discard of Packets 120 Event Notification 121 Interrupt Notifications 136 Overview 121 Port Write Notifications 133 RapidIO Error Rate Events 126 F Fabric Interrupt Status Register 382 Fixed Pattern BERT Transmitter Configuration 83 Functional Overview ...

Page 524: ...PMA Layer 484 Port Aggregation 4x and 1x link modes 68 1x 1x Configuration 69 4x 0x Configuration 69 Port Power up and Power down 214 Port Reset 120 Port Width Override 214 Port Write Notifications 133 Power Down 72 Configuration and Operation Through Power Down 73 Power up Option Signals 212 Power up Options 212 Default Port Speed 214 Port Power up and Power down 214 Port Width Override 214 Power...

Page 525: ...ontroller 226 Multicast 224 Power Supplies 227 Serial Port Configuration 220 Serial Port Lane Ordering Select 223 Serial Port Receive 219 Serial Port Speed Select 222 Serial Port Transmit 219 Signal Types 215 Signals 215 Supported Line Rates 489 System Behaviour 86 Input Queuing Model 94 Output Arbitration 88 Output Queuing Model 91 Transfer Modes 87 T Throughput 190 Traffic Efficiency 190 U Utili...

Page 526: ...Index 526 Tsi578 User Manual June 6 2016 Integrated Device Technology www idt com ...

Page 527: ...June 6 2016 CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose CA 95138 for SALES 800 345 7015 or 408 284 8200 www idt com for Tech Support srio idt com ...

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