12. Serial RapidIO Registers > RapidIO Error Management Extension Registers
299
Tsi578 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
12.7.11
RapidIO Port x Error Capture Attributes CSR and Debug 0
This register indicates the type of information contained in the Port
x
Error Capture registers. In the
case of multiple detected errors during the same clock cycle, only one of the errors must be reflected in
the error type (ERR_TYPE) field.
When VAL_CAPT is set, the fields (except VAL_CAPT) are read-only. In debug mode this register is
unlocked and all its fields are used for writing the content of the debug packet.
Register name: SP{0..15}_ERR_ATTR_CAPT_DBG0
Reset value: 0x0000_0000
Register offset: 1048, 1088, 10C8, 1108, 1148, 1188,
11C8, 1208, 1248, 1288, 12C8, 1308,
1348, 1388, 13C8, 1408
Bits
0
1
2
3
4
5
6
7
00:07
INFO_TYPE
Reserved
ERR_TYPE
08:15
Reserved
16:23
Reserved
24:31
Reserved
VAL_CAPT
Bits
Name
Description
Type
Reset
Value
0:1
INFO_TYPE
Type of information logged.
• 00 = Packet
• 01 = Control Symbol and unaligned /SC/or/PD/ or undefined
code-group
• 10 = Implementation specific (capture register contents are
implementation specific to report implementation specific errors)
• 11 = Reserved for serial port
R/W
0
2
Reserved
N/A
R
0
3:7
ERR_TYPE
Error Type
Encoded 5-bit value of captured error bit in the
. For detailed information on the
ERR_TYPE values, refer to
.
When an ERR_TYPE is reported, only specific errors cause the
capture registers to capture valid data.
R/W
0
8:30
Reserved
N/A
R
0
31
VAL_CAPT
Capture Valid Information
This bit is set by hardware to indicate that the packet/control symbol
capture registers contain valid information. For control symbols,
only capture register 0 contains meaningful information.
Software writes 0 to clear this bit and unlock all capture registers of
port
x
.
R/W0C
0
