IDT Tsi578, User Manual

Page: 364 / 527

12. Serial RapidIO Registers > Serial Port Electrical Layer Registers 364
Tsi578 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
12:15 TX_BOOST[
3:0] Transmit Boost control
Programmed boost value (ratio of drive level of transition bit to
non-transition bit) is:
boost = -20*log(1-(tx_boost[3:0]+0.5)/32)dB,
except that setting tx_boost to 0 produces 0dB of boost. This produces
results up to 5.75dB in steps of ~0.37dB
R/W 0xC
16 RX_PLL_PW
RON Power up/reset the receive PLL
0 = Rx PLL off
1 = Rx PLL on
This bit is read only unless BYPASS_INIT bit “SRIO MAC x SerDes
Configuration Global” on page 372 is set to 1.
R/W 0x1
17 RX_EN Enable receive clock and data outputs
RX_EN can only be asserted when both RX_PLL_PWRON and
RX_PLL_STATE are both asserted.
Set to 1 to enable Receive Data; 0 to disable Receive Data
This bit is read only unless BYPASS_INIT bit “SRIO MAC x SerDes
Configuration Global” on page 372 is set to 1.
R/W 0x1
18 DPLL_RESE
T A rising edge resets the frequency register of the DPLL. The rising edge
may be generated by writing a 0 and then a 1 to the register bit. R/W 0x1
19:20 Reserved N/A R/W 0
21:23 RX_EQ_VAL
[2:0] Receive Equalization control
Internal linear equalizer boost is approximately = (rx1)*0.5dB
Example: 3’b100 = 2.5dB boost
R/W 0x5
24:26 RX_DPLL_M
ODE[2:0] DPLL Mode Selection
When RX_EN is not asserted, this can change any time. This should not
change when RX_EN is asserted,
R/W 0x0
27 TX_CKO_E
N 0 = Port is not in used.
1 = Power-up clock for Transmit Domain. Must be set 1 even when only
one lane is in use.
R/W 1
28:29 LOS_CTL[1:
0] Enable LOS detector and/of filtering of raw LOS output
00 = LOS detector disabled
11 = Heavy filtering for generic LOS signaling
Other values are reserved.
R/W 0x0
30 RX_ALIGN_
EN Enable Word Alignment
0 = Alignment (framer) disabled
1 = Alignment enabled
Note: Must be disabled during PRBS test (see “Bit Error Rate Testing
(BERT)” on page 80 )
R/W 1
(Continued)
Bits Name Description Type
Reset
Value