1. Functional Overview > Overview
25
Tsi578 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
•
10 Gbit/s of instantaneous multicast input bandwidth
1
•
Packets are replicated to each egress port in parallel
•
The multicast engine can accept a bursts of traffic with different packet sizes
•
Arbitration at the egress port to allow management of resource contention between multicast or
non-multicast traffic.
Other Device Interfaces
•
Master and Slave mode I
2
C port, supports up to 8 EEPROMs
•
Optionally loads default configuration from ROMs during boot-up, through I
2
C
•
Ability to read and write EEPROMs through I
2
C during system operation
•
IEEE 1149.1 and 1149.6 boundary scan, with register access
Internal switching fabric (ISF)
•
Full-duplex,80 Gbps line rate, non-blocking switching fabric
•
Prevents head-of-line blocking on each port
•
Eight packet buffers per ingress port
•
Eight packet buffers per egress port
Register Access
•
Registers can be accessed from any RapidIO interface and both the JTAG interface and I
2
C
•
Optionally loads default configuration from ROMs during boot-up, through I
2
C
•
Supports one outstanding maintenance transaction per interface
•
Supports 32-bit wide (4 byte) register access
1. All bandwidths assume the internal switching fabric is clocked at 156.25 MHz.
System behavior when multicasting of packets which require responses is not defined in
the
RapidIO Interconnect Specification (Revision 1.3) - Part 11 Multicast Specification
.
