12. Serial RapidIO Registers > Serial Port Electrical Layer Registers
372
Tsi578 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
12.10.6
SRIO MAC x SerDes Configuration Global
This register configures the SerDes of all four lanes of each port.
Register name: SMAC{0,2,4,6,8,10,12,14}_CFG_GBL
Reset value: undefined
Register offset: 130C0, 132C0, 134C0, 136C0,
138C0, 13AC0, 13CC0, 13EC0
Bits
0
1
2
3
4
5
6
7
00:07
SERDES_R
STN
BYPASS_I
NIT
Reserved
TX_LVL[4:0]
08:15
Reserved
ACJT_LVL[4:0]
16:23
Reserved
LOS_LVL[4:0]
24:31
MPLL_PW
R_ON
MPLL_CK_
OFF
Reserved
Bits
Name
Description
Type
Reset
Value
0
SERDES_RS
TN
Active low reset signal to the SerDes
This bit is read only unless BYPASS_INIT is set to 1.
R/W
1
1
BYPASS_INI
T
Control bit to bypass initialization logic
0 = (default) SerDes initialization is determined by SP_IO_SPEED[1,0]
1 = Bypass initialization logic set by the SP_IO_SPEED[1,0] pins and
allow direct control to SerDes.
“BYPASS_INIT Functionality” on page 362
for more information on
this bit.
R/W
0
2
Reserved
N/A
R
0
3:7
TX_LVL[4:0]
Fine Resolution setting of Tx signal level.
Equation: Pk-Pk output level (without attenuation) = 1230 x (48 +
tx_lvl/2)/63.5 mV Vdiff-pp
Note: TX_LVL should be set to >= 0b01010 (which results in an output
of 1Vp-p).
Refer to
for more information on available
settings.
R/W
0x0A
8:10
Reserved
N/A
R/W
0
11:15
ACJT_LVL[4:
0]
ACJT Receiver Comparator Level
This sets the hysterisis level for AC JTAG (
Refer to IEEE 1149.6 for setting the correct voltage levels.
R/W
0x06
16:18
Reserved
N/A
R
0x0
