8. Performance > Performance Monitoring
188
Tsi578 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
illustrates the path a packet flows through a Tsi578. For Tsi578 latency performance, packet
reception time begins with the time the first bit of a packet is seen on the input pins. Packet
transmission begins when the first bit of a packet has been transmitted on the output pins.
As part of the resolution of resource contention, higher priority packets can be allowed to pass packets
of lower priority. Latencies should therefore decrease as the priority of a packet increases.
A specific time for packet latency can only be specified when there are no conditions that create
resource contention between packets. For example, if a single stream of packets passing from one
ingress port to a single egress port is the only traffic handled by the Tsi578, it is possible to specify the
latency for the packets in this stream.
A complex traffic pattern is defined to be one which has resource contention. Complex traffic patterns
make specifying the exact latency figure that each packet experiences difficult, because the amount of
contention that a packet experiences can vary widely. As such, these scenarios are not covered in this
manual.
Figure 41: Latency Illustration
In the Tsi578, packets experience packet latency variations caused by the asynchronous ability of the
device. Packets can experience an extra one or two clock cycles of delay over the minimum latency
when crossing from one clock domain to another clock domain. These factors should be taken into
account when creating a system timing budget (refer to
).
8.2
Performance Monitoring
The main purpose of the performance monitoring functionality is to observe the data traffic on the
RapidIO interface. The RapidIO traffic can come from different sources (different processing
endpoints) and can cause data congestion in one of the destination interfaces. This congestion can have
a negative impact on overall system performance. Performance monitoring can be used to identify and
help prevent situations that negatively impact system performance.
Tsi578
Packet Source
Ingress
Port
Egress
Port
Destination
Port
Ingress
Link
Egress
Link
ISF
Packets
T
0
= first bit to
arrive at Ingress
Packets
T
1
= first bit to
leave at Egress
Latency Equation:
Latency = T
1
-T
0
