12. Serial RapidIO Registers > RapidIO Error Management Extension Registers
302
Tsi578 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
12.7.13
RapidIO Port x Packet Error Capture CSR 1 and Debug 2
12.7.14
RapidIO Port x Packet Error Capture CSR 2 and Debug 3
Register name: SP{0..15}_ERR_CAPT_1_DBG2
Reset value: 0x0000_0000
Register offset: 1050, 1090, 10D0, 1110, 1150, 1190, 11D0,
1210, 1250, 1290, 12D0, 1310,
1350, 1390, 13D0, 1410
Bits
0
1
2
3
4
5
6
7
00:7
CAPT_1[0:7]
8:15
CAPT_1[8:15]
16:23
CAPT_1[16:23]
24:31
CAPT_1[24:31]
Bits
Name
Description
Type
Reset
Value
0:31
CAPT_1
Bytes 4 to 7 of the packet
R/W
0
Register name: SP{0..15}_ERR_CAPT_2_DBG3
Reset value: 0x0000_0000
Register offset: 1054, 1094, 10D4, 1114, 1154, 1194,
11D4, 1214, 1254, 1294, 12D4, 1314,
1354, 1394, 13D4, 1414
Bits
0
1
2
3
4
5
6
7
0:7
CAPT_2[0:7]
8:15
CAPT_2[8:15]
16:23
CAPT_2[16:23]
24:31
CAPT_2[24:31]
Bits
Name
Description
Type
Reset
Value
0:31
CAPT_2
Byte 8 to 11 of the packet
R/W
0