IDT Tsi578, User Manual

Page: 139 / 527

6. Event Notification > Interrupt Notifications 139
Tsi578 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
For those port specific interrupt causes which are not visible in the “Global Interrupt Status Register”
on page 388 register, the interrupt handler must access the port’s registers to determine the cause of an
interrupt. There are two RapidIO standard registers which must be accessed - the “RapidIO Port x Error
and Status CSR” on page 278 , and the “RapidIO Port x Error Detect CSR” on page 294 .
The Implementation Specific Error (IMP_SPEC_ERR) bit in the “RapidIO Port x Error Detect CSR”
on page 294 leads to a number of other IDT specific error and performance related interrupts. These
interrupts are found in one other register, the “RapidIO Port x Interrupt Status Register” on page 326 .
The Tsi578 also provides the implementation specific option of sending an interrupt for some of the
bits found in the
“RapidIO Port x Error Detect CSR” on page 294 .
All interrupt sources and their associated data can be configured by register writes in order to facilitate
the testing of software.
Table 16: Port x Error and Status Register Status
Status Bit Further Information Interrupt Enable Interrupt Clearing
OUTPUT_DROP RIO Serial Port x Control
CSR
RIO Port x Error Rate CSR
RIO Port x Error Rate
Threshold CSR
RIO Port x Packet Time to
Live CSR
RIO Port x Interrupt Status
CSR
RIO Port x Control
Independent CSR for the
TEA interrupts.
There is no specific
interrupt status bit for
OUTPUT_DROP of
packets when
OUTPUT_FAIL is
asserted. This must be
inferred by the fact that
OUTPUT_DROP is set
and no TEA interrupts are
asserted.
Write 1 to OUTPUT_DROP to
clear the RIO Port x Interrupt
Status CSR TEA interrupt bits
for the port.
Writing 1 to this bit will not clear
the Port x Error Rate CSR
ERR_RATE_CNT, so the next
time a packet is sent to this port
it may be dropped again.
OUTPUT_FAIL RIO Port x Error Rate CSR
RIO Port x Error Rate
Threshold CSR
Port x Error Rate
Threshold CSR Write 1 to OUTPUT_FAIL to
clear this interrupt.
Writing 1 to this bit will not clear
the Port x Error Rate CSR
ERR_RATE_CNT, so this bit
may become set again
immediately.
OUTPUT_DEG RIO Port x Error Rate CSR
RIO Port x Error Rate
Threshold CSR
Port x Error Rate
Threshold CSR Write 1 to OUTPUT_DEG to
clear this interrupt.
Writing 1 to this bit will not clear
the Port x Error Rate CSR
ERR_RATE_CNT, so this bit
may become set again
immediately.