9. JTAG Interface > JTAG Register Access Details
203
Tsi578 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
9.3.2
Write Access to Registers from the JTAG Interface
The following steps are required in order to write to a register through the JTAG interface:
1.
Move to the Tap controller “Shift-IR” state and program the instruction register with IRAC
instruction by writing into Instruction Register bits [2:0] with 3’b101.
2.
Move to the “Shift-DR” state and shift the data[31:0], R/W = 1 and the address[20:0] serially in the
TDI pin. To prevent corruption of un-used bits, the full DR bits have to be written. The following
values must be written:
•
DR[119:99] = ADDR[20:0]
•
DR[98] = R/W
•
DR[97:66] = DATA[31:0]
•
DR[65:64] = 0b0
•
DR[63:0] = 0b0.
3.
Move to the “Run-test idle” state and loop in this state for a minimum of 20 TCK cycles.
4.
Move to the “shift-DR” state again and shift-in 120 zero bits to DR[119:0], while at the same time
verify the Ready and Error bits that are being shifted-out as the first two bits shifted-out.
5.
Go back to step two to perform another write.
9.3.3
Read Access to Registers from the JTAG Interface
The following steps are required in order to read a register through the JTAG interface:
1.
Move to the Tap controller “Shift-IR” state and program the instruction register with IRAC
instruction.
— This step is optional if the instruction register is already programmed during the write cycle.
2.
Move to the “Shift-DR” state and shift the R/W = 0 and the address[20:0] serially in the TDI pin.
To prevent corruption of un-used bits, the full DR bits have to be written. The following values
must be written:
•
DR[119:99] = ADDR[20:0]
•
DR[98] = R/W
•
DR[97:66] = DATA[31:0]
•
DR[65:64] = 0b0
•
DR[63:0] = 0b0
3.
Move to the “Run-test idle” state and loop in this state for a minimum of 20 TCK cycles.
4.
Move to the “Shift-DR” state and shift in 120 bits of 0. The first two bits in data shifted out are the
Error and Ready bits. The next 32 bits are data. The rest of the shifted out data can be discarded.
5.
Verify that the Error bit is at logic low and the Ready bit is at logic high.
6.
Go back to step two to perform another read.
