10. Clocks, Resets and Power-up Options > Clocks
208
Tsi578 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
10.1.4
Clock Domains
The Tsi578 contains a number of clock domains that are generated from the two input reference clocks.
These domains are detailed in
. For more information about special line rate support see
.
10.1.5
Clock Gating
When a RapidIO port is powered down using the PWDN_X1/X4 bits in the
Loopback and Clock Selection Register” on page 377
, the clock to that RapidIO port is gated to
prevent the port from consuming power.
Table 27: Tsi578 Clock Domains
Clock Domain
Clock Source
Frequency
a
a.
For more electrical characteristics of the clocks, please refer to the
Tsi578
Hardware Manual
.
Description
Internal Register
Domain (P_CLK
domain)
P_CLK
b
b.
For more information on programming additional frequencies for the P_CLK, refer to
“P_CLK Programming” on page 493
.
100 MHz
This clock domain includes all internal registers within
each of the internal blocks, as well as the bus that
performs the register accesses.
The domain uses the input P_CLK directly.
Internal Switching
Fabric (ISF) Domain
S_CLK_p/n
156.25 MHz
This clock domain includes the switching matrix of the
ISF, the Multicast blocks, and the portion of each block
that communicates with the ISF.
The domain uses the S_CLK_P/N.
Serial Transmit
Domain
S_CLK_p/n
156.25 MHz
This clock domain is used to clock all the Serial RapidIO
transmit ports.
The S_CLK_P/N input is used directly to clock the
transmit logic. This clock is used to generate the
high-speed clock that is used to output the serial data on
output pins SP{0..15}_T{A..D}_P/N.
The maximum data rate for this domain is 3.125 Gb/s
per lane.
I
2
C Domain
P_CLK
divided by 1024
97.7 kHz
This clock domain is responsible for driving the I
2
C
output clock pin I2C_SCLK.
This clock domain is generated by dividing the P_CLK
input by a programmable value.
The majority of the I
2
C logic runs in the Internal Register
Domain (P_CLK domain).
