3. Serial RapidIO Electrical Interface > Bit Error Rate Testing (BERT)
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Tsi578 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
BERT testing is enabled on a per-bit lane basis, and normal traffic flow on the bit lane ceases when
BERT testing is enabled. To enable BERT testing, program the
“SerDes Lane 0 Pattern Generator
to enable either normal operation, PRBS-based BERT, or
fixed-pattern-based BERT.
When testing a link on the Tsi578 with the BERT feature, the link partner device must support PRBS
testing with at least one of the two polynomials shown in
, or it must support fixed-pattern tests.
Alternatively, the link partner must support some form of loopback to the Tsi578. Consult the
appropriate documentation for other devices to determine if they support these features, and to
determine how to configure them.
3.9.1.1
Disable SerDes Framing
Depending on the type of testing required in the system, the SerDes framing function might need to be
disabled in the Tsi578. For example, framing must be disabled if a BERT test is performed.
To disable the framer, write to the RX_ALIGN_EN bit in the SMACx_CFG_CHy register (see
MAC x SerDes Configuration Channel 0”
). Disabling this feature makes sure that data passes through
the loopback path without being re-aligned to 10 bit codeword boundaries.
4
2 byte DC balanced pattern constructed as {PAT0, ~PAT0}
5
4 byte DC balanced pattern constructed as: {0x000, PAT0,
0x3FF, ~PAT0}
6:7 Reserved
BERT testing must be performed across a link from one Tsi578 MAC to another Tsi578 MAC
or between the Tsi578 and a device that supports the same polynomial equation.
Other PRBS test sequences may be unsuitable for testing in an AC coupled system. The
PRBS pattern must ensure that it does not introduce baseline wander and cause an
unrealistically high bit error rate. The PRBS patterns generated by the Tsi578 are DC
balanced.
Table 8: Patterns Supported by Generator
MODE Setting
Description
