B. Clocking > P_CLK Programming
497
Tsi578 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
B.2.3
I
2
C interface and Timers
The I
2
C interface clock is derived from the P_CLK. Decreasing the frequency of P_CLK causes a
proportional decrease in the I
2
C serial clock and affects the I
2
C timers. The timer values can be
re-programmed during boot loading but the changes does not take effect until after the boot load has
completed. As a result, a decrease from 100 MHz to 50 MHz of P_CLK causes a doubling of the boot
load time of the EEPROM. Once boot loading has completed, the new values take effect and the I
2
C
interface can operate at the optimum rate of the attached devices.
B.2.3.1
I
2
C Time Period Divider Register
The I2C Time Period Divider Register provides programmable extension of the reference clock period
into longer periods used by the timeout and idle detect timers.
USDIV Period Divider for Micro-Second Based Timers
The USDIV field divides the reference clock down for use by the Idle Detect Timer, the Byte Timeout
Timer, the I2C_SCLK Low Timeout Timer, and the Milli-Second Period Divider.
•
Period(USDIV) = Period(P_CLK) * (USDIV + 1)
•
P_CLK is 10 ns
•
Tsi578 reset value is 0x0063
MSDIV Period Divider for Milli-Second Based Timers
The MSDIV field divides the USDIV period down further for use by the Arbitration Timeout Timer,
the Transaction Timeout Timer, and the Boot/Diagnostic Timeout Timer.
•
Period (MSDIV) = Period(USDIV) * (MSDIV + 1)
•
Tsi578 reset value is 0x03E7
B.2.3.2
I2C Start Condition Setup/Hold Timing Register
The I2C Start Condition Setup/Hold Timing Register programs the setup and hold timing for the start
condition when generated by the master control logic. The timer periods are relative to the reference
clock.
This register is shadowed during boot loading, and can be reprogrammed prior to a chain operation
without affecting the bus timing for the current EEPROM.
START_SETUP Count for the START Condition Setup Period
The START_SETUP field defines the minimum setup time for the START condition; that is, both
I2C_SCLK and I2C_SD seen high prior to I2C_SD pulled low. This is a master-only timing parameter.
Ti
p
This value also doubles as the effective Stop Hold time.
