12. Serial RapidIO Registers > IDT-Specific RapidIO Registers
315
Tsi578 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
12.8.6
RapidIO Port x Route Config Output Port CSR
This register and SPx_ROUTE_CFG_DESTID operate together to provide indirect read and write
access to the LUTs. The registers are identical to RIO_ROUTE_CFG_DESTID and
RIO_ROUTE_CFG_PORT, except the RIO_ROUTE_CFG_PORT are per-port registers and they
include an auto-increment bit to increment the contents of the destination ID register after a read or
write operation.
Register name: SP{BC,0..15}_ROUTE_CFG_PORT
Reset value: Undefined
Register offset: 10074, 11074, 11174, 11274, 11374,
11474, 11574, 11674, 11774, 11874, 11974,
11A74, 11B74, 11C74, 11D74, 11E74, 11F74
Bits
0
1
2
3
4
5
6
7
00:07
Reserved
08:15
Reserved
16:23
Reserved
24:31
PORT
Bits
Name
Description
Type
Reset
Value
0:23
Reserved
N/A
R
0
24:31
PORT
This is the RapidIO output port through which all transactions meant for
CFG_DEST_ID are sent.
Writing a value greater or equal to PORT_TOTAL field in the
Switch Port Information CAR” on page 252
sets the LUT entry to an
unmapped state. For future compatibility, write the value 0xFF to
indicate an unmapped destination ID.
When reading an unmapped value from the LUT, this field is set to 0xFF.
R/W
Undefined
