7. I
2
C Interface > Timeouts
180
Tsi578 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
•
“I2C_SCLK Low and Arbitration Timeout Register”
) – This timeout
applies only to master transactions initiated by setting the START bit in the
. Its purpose is to limit the length of time the master controller tries to gain ownership of
the bus. The arbitration timer is disabled once the <Start><Slave Address><Read/Write> are
successfully transmitted without detecting another master attempting a different transaction. If the
Tsi578 I
2
C master subsequently loses ownership of the bus after this phase of the transaction, the
transaction is aborted. If the Tsi578 I
2
C master detects another master corrupting the
<Start><Slave Address><Read/Write> bits it has transmitted, the Tsi578 I
2
C master reverts to
waiting for bus idle then tries again. The arbitration timeout continues to run in this case. If the
arbitration timer expires before ownership is gained and the master is waiting for bus idle, then it
aborts the operation and sets the MARBTO event, which causes a MA_ATMO interrupt status to
be updated in the
. An optional interrupt can also be sent to the
Interrupt Controller if the MA_ATMO is enabled in the
If the Tsi578 I
2
C master was in the midst of transmitting the <Slave Address> when the timeout
expires, it allows the <Slave Address> to complete. If an ACK or NACK is successfully received,
the master continues as if the timeout had not expired. If another I
2
C master collides with <Slave
Address>, the timeout immediately takes effect following the <Slave Address> bit where the
collision took place.
•
Byte timeout (see
C Byte/Transaction Timeout Register”
) – This timeout is disabled on reset. It
detects a situation where one or more devices are stretching the clock enough to slow the transfer
speed on the bus beyond some limit. This timeout is available primarily to detect a violation of the
SMBus TLOW:MEXT time. The response to this timeout expiring depends on the phase of the
transfer and whether it is detected by the master or slave interface. For a master transaction, the
master continues to generate clocks until the next bit time where it would have control of the bus;
that is, writing data or generating an Ack/Nack in response to a read byte. At that time, the master
generates a Stop condition, aborts the operation and sets the MBTTO event, which causes an
MA_TMO interrupt status to get updated in the
. An optional
interrupt can also be sent to the Interrupt Controller if the MA_TMO bit is enabled in the
. For a slave transaction, the slave waits for the start of the next bit time,
releases the I2C_SD and I2C_SCLK signals and sets the SBTTO event, which causes an SA_FAIL
interrupt status to get updated in the I2C_INT_STAT register. An optional interrupt can be sent to
the Interrupt Controller if the SA_FAIL bit is enabled in the
slave then reverts to looking for the next Start/Restart/Stop.
