12. Serial RapidIO Registers > RapidIO Physical Layer Registers
280
Tsi578 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
29
PORT_ERR
Port Error
PORT_ERR on the even port is composed of a logical OR of
PORT_ERR signal produced by the individual lanes independent of
whether the MAC is configured in 4x mode or 1x mode. Therefore,
when the MAC is in a x1 configuration, and an error occurs on the
odd port, the PORT_ERR bit will be asserted in the Error and
Status CSR of both the odd and even ports. The assertion of
PORT_ERR in the even port's Error and Status CSR occurs
independently of the state of the PORT_OK bit of the even port.
Inbound or Outbound port has encountered an error from which the
hardware was unable to recover (fatal error).
The following fatal errors cause a PORT_ERR:
• Four link-request tries with link-response, but no outstanding
ackID
• Four link-request tries with time-out error for link-response
• Dead link timer is enabled (in the DLT_EN bit in the
Digital Loopback and Clock Selection Register” on page 377
) and
the timer expires. Refer to
for more
information on this feature.
• The Lane Sync Timer (LST) expires for at least one lane of a port
(for more information, see
).
R/W1C
0
30
PORT_OK
Port OK
Inbound and Outbound ports are initialized and can communicate
with the adjacent device. This bit and bit 31, Port Un-initialized, are
mutually exclusive.
R
0
31
PORT_UNINIT
Port Un-initialized
Inbound and Outbound ports are not initialized. This bit and bit 30,
PORT_OK, are mutually exclusive.
This bit is set to a 1 after reset.
R
1
(Continued)
Bits
Name
Description
Type
Reset
Value
