12. Serial RapidIO Registers > RapidIO Logical Layer and Transport Layer Registers
245
Tsi578 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
12.5
RapidIO Logical Layer and Transport Layer Registers
Every processing element contains a set of capability registers (CARs) that allows another processing
element to determine its capabilities through maintenance read operations. All registers are 32 bits
wide and are organized and accessed in 32-bit quantities. CARs are read-only and are big-endian — bit
0 is the most significant bit.
A processing element contains a set of command and status registers (CSRs) that allows another
processing element to control and determine the status of its internal hardware. All registers are
organized and accessed in the same way as the CARs.
All of the registers in this section are defined in the
RapidIO Interconnect Specification (Revision 1.3)
.
These registers are reset by the HARD_RST_b reset input signal, as well as when the Tsi578 performs
a self-reset. The registers within a port are also reset by a
. For more information on Tsi578
reset implementation and behavior, see
“Clocks, Resets and Power-up Options” on page 205
It is possible to override reset values of writable fields, and some read-only fields, using the I
2
C
register loading capability on boot. Refer to
for more information on the
use of I
2
C register loading capability.
1E0F4
SMAC{0,2,4,6,8,10,12,14}_FP_VAL
_3
“SerDes Lane 3 Frequency and Phase Value Register” on
page 414
1E0F8-1E0FC
Reserved
When an individual port is powered down, the RapidIO Logical Layer and Transport Layer
Registers for that port are read only and return 0.
The I
2
C register loading capability is only used on a power-on reset (that is, HARD_RST_b)
Table 36: Register Map (Continued)
Offset
Register Name
See
