IDT Tsi578, User Manual

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7. I
2
C Interface > Bus Timing 183
Tsi578 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
7.13 Bus Timing
Figure 40 shows the relationship of the bus timing parameters to the generation of the I2C_SCLK and
I2C_SD signals on the I
2
C bus. These parameters are configured in the following registers:
• “I
2
C Start Condition Setup/Hold Timing Register”
• “I
2
C Stop/Idle Timing Register”
• “I2C_SD Setup and Hold Timing Register”
• “I
2
C Stop/Idle Timing Register”
• “I2C_SCLK High and Low Timing Register”
• “I2C_SCLK Minimum High and Low Timing Register”
The bus timing resets to 100-kHz operation. By reprogramming these registers, other bus speeds can be
configured. Speeds above 100 kHz are not guaranteed to conform to the
I
2
C Specification because of
the absence of Schmitt triggers on the input of the I2C_SD and I2C_SCLK signals, and the absence of
slope controlled outputs for the I2C_SD and I2C_SCLK signals. It is up to the board or system
designer to decide on the applicability of operation at speeds above 100 kHz.
Bus timing does not normally change during a transaction, even if these registers are changed. The
timing registers are sampled at certain times to prevent this from occurring. The following are the times
when timing adjustments take effect:
• On hard reset (times are reset to 100 kHz)
• When reset using the “I
2
C Reset Register”
• At the start of a master transaction through the “I
2
C Master Control Register” , when the START
condition is generated
• Upon a chain operation during boot load
Timing parameters are discussed further in the following sections.