13. I2C Registers > Register Descriptions
474
Tsi578 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
13.2.28
I
2
C Stop/Idle Timing Register
This register programs the setup timing for the Stop condition when generated by the master control
logic, and the Idle Detect timer. The Start Setup time doubles as the Stop Hold. The timer period for the
Stop setup is relative to the reference clock. The timer period for the Idle Detect is relative to the
USDIV period. The STOP setup time is shadowed during boot loading, and can be reprogrammed prior
to a chain operation without affecting the bus timing for the current EEPROM.
Register name: I2C_STOP_IDLE
Reset value:
0x0191_0033
Register offset: 0x1D344
Bits
0
1
2
3
4
5
6
7
00:07
STOP_SETUP
08:15
STOP_SETUP
16:23
IDLE_DET
24:31
IDLE_DET
Bits
Name
Description
Type
Reset
Value
00:15
STOP_SETUP
Count for STOP Condition Setup Period
Defines the minimum setup time for the STOP condition;
that is, both I2C_SCLK seen high and I2C_SD seen low
prior to I2C_SD released high. This is a master-only timing
parameter.
Period(STOP_SETUP) = (STOP_SETUP * Period(P_CLK)),
where P_CLK is 10ns.
Reset time is 4.01 microseconds.
R/W
0x0191
16:31
IDLE_DET
Count for Idle Detect Period
Used in two cases. First, defines the period after reset
during which the I2C_SCLK signal must be seen high to call
the bus idle. This period is needed to avoid interfering with
an ongoing transaction after reset. Second, defines the
period before a master transaction during which the
I2C_SCLK and I2C_SD signals must both be seen high to
call the bus idle. This period is a protection against external
master devices not correctly idling the bus.
Period(IDLE_DET) = (IDLE_DET * Period(USDIV)), where
USDIV is the microsecond time defined in the
. A value of zero results in no idle
detect period, meaning the bus will be sensed as idle
immediately.
Reset time is 51 microseconds.
R/W
0x0033
