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Hitachi HD6417032, Hardware Manual

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Accesses to on-chip spaces are as follows: On-chip supporting module spaces (area 5 when
address bit A27 is 1) are always 3-state access spaces, regardless of WCR, with no 

WAIT

 signal

sampling. Accesses to on-chip ROM (area 0 when MD2–MD0 are 010) and on-chip RAM (area 7
when address bit A27 is 0) are always performed in 1 state, regardless of WCR, with no 

WAIT

signal sampling.

If the bus timing specifications (t

WTS

 and t

WTH

) are not observed when the 

WAIT

 signal is input

in external space access, this will simply mean that 

WAIT

 signal assertion and negation will not

be detected, but will not result in misoperation.  Note, however, that the inability to detect 

WAIT

signal assertion may result in a problem with memory access due to insertion of an insufficient
number of waits.

Summary of Contents for HD6417032

Page 1: ...ccordingly although Hitachi Hitachi Ltd Hitachi Semiconductors and other Hitachi brand names are mentioned in the document these names have all been changed to Renesas Technology Corporation Except for our corporate trademark logo and corporate statement no changes whatsoever have been made to the contents of the document and these changes do not constitute any alteration to the contents of the do...

Page 2: ...SuperH RISC Engine SH7032 and SH7034 HD6417032 HD6477034 HD6437034 HD6417034 HD6437034B HD6417034B Hardware Manual ADE 602 062E Rev 6 0 9 18 02 Hitachi Ltd ...

Page 3: ...of bodily injury such as aerospace aeronautics nuclear power combustion control transportation traffic safety equipment or medical equipment for life support 4 Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating operating supply voltage range heat radiation characteristics installation conditions and other characteristics Hita...

Page 4: ...gic circuits and microcomputers Purpose The purpose of this manual is to give users an understanding of the hardware functions and electrical characteristics of the SH7032 and SH7034 Details of execution instructions can be found in the SH 1 SH 2 SH DSP Programming Manual which should be read in conjunction with the present manual Using this Manual For an overall understanding of the SH7032 and SH...

Page 5: ...DSP Programming Manual ADE 602 085 Users manuals for development tools Manual Title ADE No C C Complier Assembler Optimized Linkage Editor User s Manual ADE 702 304 Simulator Debugger Users Manual ADE 702 266 Hitachi Embedded Workshop Users Manual ADE 702 275 Application Note Manual Title ADE No C C Complier ADE 502 046 ...

Page 6: ...n Clock 7 Clock Pulse Generator CPG Crystal pulse generator duty correction circuit Buses 8 Bus State Controller BSC Division of memory space DRAM interface refresh wait state control parity control 9 Direct Memory Access Controller DMAC Auto request external request on chip peripheral module request cycle steal mode burst mode Timers 10 16 Bit Integrated Timer Pulse Unit ITU Waveform output mode ...

Page 7: ...on selection 16 Parallel I O Ports I O I O ports Memory 17 ROM ROM PROM mode high speed programming system 18 RAM RAM On chip RAM Power Down State 19 Power Down State Sleep mode standby mode Electrical Characteristics 20 Electrical Characteristics Absolute maximum ratings AC characteristics DC characteristics operation timing ...

Page 8: ... Buses 10 16 bit integrated timer pulse unit ITU Timers 13 Serial communication interface SCI 14 A D converter Data processing 15 Pin function controller PFC 16 Parallel I O ports Pins 17 ROM 18 RAM Memory 19 Power down state 20 Electrical characteristics 1 Overview 2 CPU 3 Operating modes 11 Programmable timing pattern controller TPC 12 Watchdog timer WDT Figure 1 Manual Organization ...

Page 9: ... the same contents as the actual registers are thus provided in the on chip peripheral module space In this manual register addresses are specified as though the on chip peripheral module registers were in the 512 bytes H 5FFFE00 H 5FFFFFF Only the values of the A27 A24 and A8 A0 bits are valid the A23 A9 bits are ignored When area H 5000000 H 50001FF is accessed for example the result will be the...

Page 10: ...D6437034AF12 40 to 85 C HD6437034AVFI12 HD6437034AFI12 5 0 V 2 to 20 MHz 20 to 75 C HD6437034AX20 HD6437034ATE20 120 pin plastic 40 to 85 C HD6437034AXI20 HD6437034ATEI20 TQFP TFP 120 3 3 V 2 to 12 5 MHz 20 to 75 C HD6437034AVX12 HD6437034ATE12 40 to 85 C HD6437034AVXI12 HD6437034ATEI12 ROMless 5 0 V 2 to 20 MHz 20 to 75 C HD6417034F20 HD6417034F20 112 pin plastic 40 to 85 C HD6417034FI20 HD641703...

Page 11: ...re 174 Description amended tBACD2 tBRQS tBACD1 6 9 1 4 Register Configuration Table 9 2 DMAC Registers 179 4 added 4 Only the values of bits A27 A24 and A8 A0 are valid bits A23 A9 are ignored For details on the register addresses see section 8 3 5 Area Descriptions 6 9 3 4 DMA Transfer Types 200 Description amended Line 3 destination or source must be the SCI or A D converter table 9 4 6 10 1 4 R...

Page 12: ...reset SYNC1 1 PWM PWM1 1 Output compare A function PWM1 0 IOA2 0 others don t care 6 Table 10 20 ITU Operating Modes Channel 2 303 Table amended Register Setting TSNC TMDR TFCR TOCR TIOR2 TCR2 Operating Mode Sync MDF FDIR PWM Comp PWM Reset Sync PWM Buffer Output Level Select IOA IOB Clear Select Clock Select Synch ronized preset SYNC2 1 PWM PWM2 1 Output compare A function PWM2 0 IOA2 0 others do...

Page 13: ... 2 PBCR2 R W H 0000 H 5FFFFCE 8 16 32 Column address strobe pin control register CASCR R W H 5FFF H 5FFFFEE 8 16 32 Note Only the values of bits A27 A24 and A8 A0 are valid bits A23 A9 are ignored For details on the register addresses see section 8 3 5 Area Descriptions 6 16 2 1 Register Configuration Table 16 1 Port A Register 442 Note added Name Abbreviation R W Initial Value Address Access Size...

Page 14: ...eleted 6 2 Control Signal Timing Table 20 5 Control Signal Timing 474 16 6 MHz deleted 6 3 Bus Timing Table 20 6 Bus Timing 1 478 479 Description amended Read data access time 1 6 tACC1 tcyc 30 4 ns 20 8 20 11 20 12 Read data access time 2 6 tACC2 tcyc n 2 30 3 ns 20 9 20 10 20 13 20 15 Read data access time from CAS 2 6 tCAC2 tcyc n 1 25 3 ns Read data access time from RAS 1 6 tRAC1 tcyc 1 5 20 n...

Page 15: ...r and I O Port Timing 510 16 6 MHz deleted 6 7 Watchdog Timer Timing Table 20 11 Watchdog Timer Timing 511 16 6 MHz deleted 6 8 Serial Communication Interface Timing Table 20 12 Serial Communication Interface Timing 512 16 6 MHz deleted 6 9 A D Converter Timing Table 20 13 A D Converter Timing 513 16 6 MHz deleted 6 20 1 4 A D Converter Characteristics Table 20 14 A D Converter Characteristics 516...

Page 16: ...Table 20 16 DC Characteristics 518 519 12 5 MHz added Conditions VCC 3 3 V 0 3V AVCC 3 3 V 0 3V AVCC VCC 0 3V AVref 3 0 V to AVCC VSS AVSS 0 V φ 12 5 to 20 MHz 1 Ta 20 to 75 C 2 Notes 1 ROMless products only for 20 MHz version 2 Regular specification products for wide temperature range products Ta 40 to 85 C Current Ordinary ICC 25 mA f 12 5 MHz consumption operation 35 60 mA f 20 MHz Sleep 20 mA ...

Page 17: ...19 Control Signal Timing 524 12 5 MHz added and description amended 12 5 MHz 20 MHz Item Symbol Min Max Min Max Unit Figure RES setup time tRESS 320 200 ns 20 48 RES pulse width tRESW 20 20 tcyc NMI reset setup time tNMIRS 320 200 ns NMI reset hold time tNMIRH 320 200 ns NMI setup time tNMIS 160 100 ns 20 49 NMI hold time tNMIH 80 50 ns IRQ0 IRQ7 setup time edge detection tIRQES 160 100 ns IRQ0 IR...

Page 18: ... 2 Notes 1 ROMless products only for 20 MHz version 2 Regular specification products for wide temperature range products Ta 40 to 85 C 6 7 Watchdog Timer Timing Table 20 24 Watchdog Timer Timing 549 Description amended Conditions VCC 3 3 V 0 3V AVCC 3 3 V 0 3V AVCC VCC 0 3V AVref 3 0 V to AVCC VSS AVSS 0 V φ 12 5 to 20 MHz 1 Ta 20 to 75 C 2 Notes 1 ROMless products only for 20 MHz version 2 Regula...

Page 19: ...re match flag B IMFB 0 Clear conditions 0 is written in IMFB after reading IMFB 1 Initial value 1 Set conditions 1 When GRB is functioning as the output compare register and TCNT GRB 2 When GRB is functioning as the input capture register and the TCNT value is transferred to GRB by the input capture signal 0 Input capture compare match flag A IMFA 0 Clear conditions 0 is written in IMFA after read...

Page 20: ...added Watchdog timer WDT TCNT Initialized Initialized Held Held TCSR 1 RSTCR 2 Initialized Serial communication SMR Initialized Initialized Initialized Held interface SCI BRR SCR TDR TSR Held SSR Initialized RDR RSR Held Notes 1 Bits 7 5 OVF WT IT TME are initialized bits 2 0 CKS2 CKS0 are held 2 Not initialized in the case of a reset by the WDT 6 ...

Page 21: ......

Page 22: ... 2 Data Format in Memory 20 2 2 3 Immediate Data Format 21 2 3 Instruction Features 21 2 3 1 RISC Type Instruction Set 21 2 3 2 Addressing Modes 24 2 3 3 Instruction Formats 27 2 4 Instruction Set 31 2 4 1 Instruction Set by Classification 31 2 4 2 Operation Code Map 42 2 5 CPU State 45 2 5 1 State Transitions 45 2 5 2 Power Down State 48 Section 3 Operating Modes 49 3 1 Types of Operating Modes a...

Page 23: ...es in which Exceptions are Not Accepted 63 4 6 1 Immediately after Delayed Branch Instruction 63 4 6 2 Immediately after Interrupt Disabling Instruction 63 4 7 Stack Status after Exception Handling 64 4 8 Notes 65 4 8 1 Value of the Stack Pointer SP 65 4 8 2 Value of the Vector Base Register VBR 65 4 8 3 Address Errors Caused by Stacking During Address Error Exception Handling 65 Section 5 Interru...

Page 24: ...8 6 3 2 Break on Instruction Fetch Cycles to On Chip Memory 90 6 3 3 Program Counter PC Value Saved in User Break Interrupt Exception Processing 90 6 4 Setting User Break Conditions 91 6 5 Notes 92 6 5 1 On Chip Memory Instruction Fetch 92 6 5 2 Instruction Fetch at Branches 92 6 5 3 Instruction Fetch Break 93 Section 7 Clock Pulse Generator CPG 95 7 1 Overview 95 7 2 Clock Source 95 7 2 1 Connect...

Page 25: ...4 Accessing External Memory Space 136 8 4 1 Basic Timing 136 8 4 2 Wait State Control 138 8 4 3 Byte Access Control 141 8 5 DRAM Interface Operation 142 8 5 1 DRAM Address Multiplexing 142 8 5 2 Basic Timing 144 8 5 3 Wait State Control 146 8 5 4 Byte Access Control 148 8 5 5 DRAM Burst Mode 150 8 5 6 Refresh Control 155 8 6 Address Data Multiplexed I O Space Access 159 8 6 1 Basic Timing 159 8 6 ...

Page 26: ... 3 6 DMA Transfer Ending Conditions 212 9 4 Examples of Use 213 9 4 1 DMA Transfer between On Chip RAM and Memory Mapped External Device 213 9 4 2 Example of DMA Transfer between On Chip SCI and External Memory 214 9 4 3 Example of DMA Transfer Between On Chip A D Converter and External Memory 215 9 5 Usage Notes 216 Section 10 16 Bit Integrated Timer Pulse Unit ITU 219 10 1 Overview 219 10 1 1 Fe...

Page 27: ... TCNT Write and Clear 290 10 6 2 Contention between TCNT Word Write and Increment 291 10 6 3 Contention between TCNT Byte Write and Increment 292 10 6 4 Contention between GR Write and Compare Match 293 10 6 5 Contention between TCNT Write and Overflow Underflow 294 10 6 6 Contention between General Register Read and Input Capture 295 10 6 7 Contention Between Counter Clearing by Input Capture and...

Page 28: ... Usage Notes 332 11 4 1 Non Overlap Operation 332 Section 12 Watchdog Timer WDT 335 12 1 Overview 335 12 1 1 Features 335 12 1 2 Block Diagram 336 12 1 3 Pin Configuration 336 12 1 4 Register Configuration 337 12 2 Register Descriptions 337 12 2 1 Timer Counter TCNT 337 12 2 2 Timer Control Status Register TCSR 338 12 2 3 Reset Control Status Register RSTCSR 339 12 2 4 Notes on Register Access 340...

Page 29: ...hronous Mode 374 13 3 3 Multiprocessor Communication 385 13 3 4 Synchronous Operation 393 13 4 SCI Interrupt Sources and the DMAC 403 13 5 Usage Notes 403 Section 14 A D Converter 407 14 1 Overview 407 14 1 1 Features 407 14 1 2 Block Diagram 408 14 1 3 Configuration of Input Pins 409 14 1 4 Configuration of A D Registers 410 14 2 Register Descriptions 410 14 2 1 A D Data Registers A D ADDRA ADDRD...

Page 30: ... Control Register CASCR 439 Section 16 I O Ports I O 441 16 1 Overview 441 16 2 Port A 441 16 2 1 Register Configuration 441 16 2 2 Port A Data Register PADR 442 16 3 Port B 443 16 3 1 Register Configuration 443 16 3 2 Port B Data Register PBDR 444 16 4 Port C 445 16 4 1 Register Configuration 445 16 4 2 Port C Data Register PCDR 446 Section 17 ROM 447 17 1 Overview 447 17 2 PROM Mode 448 17 2 1 S...

Page 31: ... Timing 477 4 DMAC Timing 507 5 16 bit Integrated Timer Pulse Unit Timing 509 6 Programmable Timing Pattern Controller and I O Port Timing 510 7 Watchdog Timer Timing 511 8 Serial Communication Interface Timing 512 9 A D Converter Timing 513 10 AC Characteristics Test Conditions 515 20 1 4 A D Converter Characteristics 516 20 2 SH7034B 3 3 V 12 5 MHz Version and 20 MHz Version Electrical Character...

Page 32: ... ITU 580 A 2 17 Timer Status Registers 0 4 TSR0 TSR4 ITU 581 A 2 18 Timer Counter 0 4 TCNT0 TCNT4 ITU 582 A 2 19 General Registers A0 4 GRA0 GRA4 ITU 583 A 2 20 General Registers B0 4 GRB0 GRB4 ITU 584 A 2 21 Buffer Registers A3 4 BRA3 BRA4 ITU 585 A 2 22 Buffer Registers B3 4 BRB3 BRB4 ITU 586 A 2 23 Timer Output Control Register TOCR ITU 587 A 2 24 DMA Source Address Registers 0 3 SAR0 SAR3 DMAC...

Page 33: ...FC 624 A 2 58 Port B I O Register PBIOR PFC 625 A 2 59 Port A Control Register 1 PACR1 PFC 626 A 2 60 Port A Control Register 2 PACR2 PFC 628 A 2 61 Port B Control Register 1 PBCR1 PFC 630 A 2 62 Port B Control Register 2 PBCR2 PFC 632 A 2 63 Column Address Strobe Pin Control Register CASCR PFC 634 A 2 64 TPC Output Mode Register TPMR TPC 635 A 2 65 TPC Output Control Register TPCR TPC 636 A 2 66 ...

Page 34: ...f TPC Output Groups 2 and 3 are Different 642 A 2 75 Next Data Register B NDRB TPC When the Output Triggers of TPC Output Groups 2 and 3 are Different 642 A 3 Register Status in Reset and Power Down States 643 Appendix B Pin States 646 Appendix C Package Dimensions 652 ...

Page 35: ...xiv ...

Page 36: ...systems to be constructed with advanced functionality at low cost even in applications such as realtime control that require very high speeds an impossibility with conventional microcomputers SH microcomputers include peripheral functions such as large capacity ROM RAM a direct memory access controller DMAC timers a serial communication interface SCI an A D converter an interrupt controller INTC a...

Page 37: ...educe pipeline disruption Instruction set optimized for C language Instruction execution time one instruction cycle 50 ns instruction at 20 MHz operation Address space 4 Gbytes available in the architecture On chip multiplier multiplication operations 16 bits 16 bits 32 bits executed in 1 3 cycles and multiplication accumulation operations 16 bits 16 bits 42 bits 42 bits executed in 2 3 cycles Fiv...

Page 38: ...nal data bus Address space divided into eight areas with the following preset features Bus size 8 or 16 bits Number of wait cycles can be defined by user Type of area external memory area DRAM area etc Simplifies connection to ROM SRAM DRAM and peripheral I O When the DRAM area is accessed RAS and CAS signals for DRAM are output Tp cycles can be generated to assure RAS precharge time Address multi...

Page 39: ...ut with 0 100 duty cycle maximum resolution 50 ns Complementary PWM mode can output a maximum of three pairs of non overlapping PWM waveforms Phase counting mode can count up or down according to the phase of an external two phase clock Timing pattern Maximum 16 bit output 4 bits 4 channels can be output controller TPC Non overlap intervals can be established between pairs of waveforms Timing sour...

Page 40: ...t A 16 input output lines input or output can be selected for each bit Port B 16 input output lines input or output can be selected for each bit Port C 8 input lines Large on chip memory SH7034 on chip ROM version 64 kbyte electrically programmable ROM or masked ROM and 4 kbyte RAM SH7032 ROMless version 8 kbyte RAM 32 bit data can be accessed in one clock cycle ...

Page 41: ...120 pin plastic 40 to 85 C HD6477034XI20 HD6477034TEI20 TQFP TFP 120 3 3 V 2 to 12 5 MHz 20 to 75 C HD6477034VX12 HD6477034VTE12 40 to 85 C HD6477034VXI12 HD6477034VTEI12 Mask 5 0 V 2 to 20 MHz 20 to 75 C HD6437034AF20 HD6437034AF20 112 pin plastic ROM 40 to 85 C HD6437034AFI20 HD6437034AFI20 QFP FP 112 3 3 V 2 to 12 5 MHz 20 to 75 C HD6437034AVF12 HD6437034AF12 40 to 85 C HD6437034AVFI12 HD643703...

Page 42: ... 75 C HD6437034BVX12 6437034B X 120 pin plastic 40 to 85 C HD6437034BVXW12 6437034B XW TQFP TFP 120 ROMless 3 3 V 4 to 20 MHz 20 to 75 C HD6417034BVF20 HD6417034BVF20 112 pin plastic 40 to 85 C HD6417034BVFW20 HD6417034BVFW20 QFP FP 112 20 to 75 C HD6417034BVX20 6417034BVTE20 120 pin plastic 40 to 85 C HD6417034BVXW20 6417034BVTEW20 TQFP TFP 120 Notes 1 The electrical characteristics of the SH7034...

Page 43: ... TP7 TOCXB4 TCLKD PB6 TP6 TOCXA4 TCLKC PB5 TP5 TIOCB4 PB4 TP4 TIOCA4 PB3 TP3 TIOCB3 PB2 TP2 TIOCA3 PB1 TP1 TIOCB2 PB0 TP0 TIOCA2 PC7 AN7 PC6 AN6 PC5 AN5 PC4 AN4 PC3 AN3 PC2 AN2 PC1 AN1 PC0 AN0 Peripheral address bus 24 bits Peripheral data bus 16 bits Internal address bus 24 bits Internal upper data bus 16 bits Internal lower data bus 16 bits Port A Address Address Data address Port B Port C Clock...

Page 44: ...16 A17 A18 A19 A20 A21 CS0 CS1 CASH CS2 CS3 CASL VSS PA0 CS4 TIOCA0 PA1 CS5 RAS PA2 CS6 TIOCB0 PA3 CS7 WAIT V CC V CC MD2 MD1 MD0 RES WDTOVF V CC V PP 1 NMI V CC XTAL EXTAL V SS CK V CC PA15 IRQ3 DREQ1 PA14 IRQ2 DACK1 2 PA13 IRQ1 DREQ0 TCLKB PA12 IRQ0 DACK0 2 TCLKA PA11 DPH TIOCB1 PA10 DPL TIOCA1 PA9 AH IRQOUT ADTRG PA8 BREQ V SS PA7 BACK PA6 RD PA5 WRH LBS PA4 WRL WR 84 83 82 81 80 79 78 77 76 75...

Page 45: ...P9 TxD0 PB10 TP10 RxD1 PB11 TP11 TxD1 PB12 TP12 IRQ4 SCK0 PB13 TP13 IRQ5 SCK1 NC 3 V CC V CC MD2 MD1 MD0 RES WDTOVF V CC V PP 1 NMI V CC XTAL EXTAL V SS CK V CC PA15 IRQ3 DREQ1 PA14 IRQ2 DACK1 2 PA13 IRQ1 DREQ0 TCLKB PA12 IRQ0 DACK0 2 TCLKA PA11 DPH TIOCB1 PA10 DPL TIOCA1 PA9 AH IRQOUT ADTRG PA8 BREQ V SS PA7 BACK PA6 RD PA5 WRH LBS PA4 WRL WR NC 3 NC 3 84 83 82 81 80 79 90 89 88 87 86 85 78 77 76...

Page 46: ... clock Connected to a crystal resonator or external clock input having the same frequency as the system clock CK XTAL 74 79 I Crystal Connected to a crystal resonator with the same frequency as the system clock CK If an external clock is input at the EXTAL pin leave XTAL open CK 71 76 O System clock Supplies the system clock CK to peripheral devices System control RES 79 84 I Reset Low input cause...

Page 47: ...r falling edge can be selected for signal detection IRQ0 IRQ7 66 69 111 112 1 2 71 74 118 119 2 3 I Interrupt request 0 7 Maskable interrupt request signals Level input or edge triggered input can be selected IRQOUT 63 68 O Slave interrupt request output Indicates occurrence of an interrupt while the bus is released Address bus A21 A0 47 44 42 41 39 32 30 23 50 47 45 44 42 35 33 32 29 24 O Address...

Page 48: ...Chip select signals for accessing external memory and devices AH 63 68 O Address hold Address hold timing signal for a device using a multiplexed address data bus HBS LBS 23 58 24 63 O Upper lower byte strobe Upper and lower byte strobe signals Also used as WRH and A0 WR 57 62 O Write Brought low during write access Also used as WRL DMAC DREQ0 DREQ1 67 69 72 74 I DMA transfer request channels 0 an...

Page 49: ... 118 119 I O Serial clock channels 0 and 1 Clock input output pins for SCI0 and SCI1 A D converter AN7 AN0 95 92 90 87 101 98 96 93 I Analog input Analog signal input pins ADTRG 63 68 I A D trigger input External trigger input for starting A D conversion AVref 86 92 I Analog reference power supply Input pin for the analog reference voltage AVCC 85 91 I Analog power supply Power supply pin for anal...

Page 50: ... 39 A12 A12 9 10 AD5 D5 37 40 A13 A13 10 11 AD6 D6 38 41 A14 A14 11 12 AD7 D7 39 42 A15 A15 12 13 VSS VSS 40 43 VSS VSS 13 14 AD8 NC 41 44 A16 A16 14 15 AD9 NC 42 45 A17 VCC 15 16 VCC VCC 43 46 VCC VCC 16 17 AD10 NC 44 47 A18 VCC 17 18 AD11 NC 45 48 A19 NC 18 19 AD12 NC 46 49 A20 NC 19 20 AD13 NC 47 50 A21 NC 20 21 AD14 NC 48 51 CS0 NC 21 22 AD15 NC 49 52 CS1 CASH NC 22 23 VSS VSS 50 53 CS2 NC 23 ...

Page 51: ...A NC 95 101 PC7 AN7 VSS 67 72 PA13 IRQ1 DREQ0 TCLKB NC 96 102 VSS VSS 68 73 PA14 IRQ2 DACK1 NC 97 103 PB0 TP0 TIOCA2 NC 69 74 PA15 IRQ3 DREQ1 NC 104 NC NC 70 75 VCC VCC 98 105 PB1 TP1 TIOCB2 NC 71 76 CK NC 99 106 VCC VCC 72 77 VSS VSS 100 107 PB2 TP2 TIOCA3 NC 73 78 EXTAL NC 101 108 PB3 TP3 TIOCB3 NC 74 79 XTAL NC 102 109 PB4 TP4 TIOCA4 NC 75 80 VCC VCC 103 110 PB5 TP5 TIOCB4 NC 76 81 NMI A9 104 1...

Page 52: ...x register For some instructions the R0 register must be used Register R15 functions as a stack pointer to save or restore status registers SR and the program counter PC during exception handling R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP hardware stack pointer 0 31 R0 functions as an index register in the indexed register addressing mode and indirect indexed GBR addressing mode In s...

Page 53: ...ved bits These bits always read 0 The write value should always be 0 Bits I3 I0 Interrupt mask bits M and Q bits Used by the DIV0U DIV0S and DIV1 instructions Global base register GBR Indicates the base address in indirect GBR addressing mode The indirect GBR addressing mode is used to transfer data to the on chip supporting module register area etc Vector base register VBR Stores the base address...

Page 54: ...accumulate opera tions MACH is sign extended when read because only the lowest 10 bits are valid Procedure register PR Stores the return address for a subroutine procedure Program counter PC Indicates the fourth byte second instruction after the current instruction Figure 2 3 System Registers 2 1 4 Initial Values of Registers Table 2 1 lists the values of the registers after reset Table 2 1 Initia...

Page 55: ...ddress but an address error will occur if an attempt is made to access word data starting from an address other than 2n or longword data starting from an address other than 4n In such cases the data accessed cannot be guaranteed The hardware stack area which is referred to by the hardware stack pointer SP R15 uses only longword data starting from address 4n because this area stores the program cou...

Page 56: ...l instructions are RISC type Their features are as follows 16 Bit Fixed Length Every instruction is 16 bits long making program coding much more efficient One Instruction Cycle Basic instructions can be executed in one cycle using a pipeline system One cycle instructions are executed in 50 ns at 20 MHz Data Length Longword is the standard data length for all operations Memory can be accessed in by...

Page 57: ...be executed in 1 3 cycles 16 bit 16 bit 42 bit 42 bit multiplication accumulation operations can be executed in 2 3 cycles T bit T bit in the status register is set according to the result of a comparison and in turn is the condition True False that determines if the program will branch The T bit in the status register is only changed by selected instructions thus improving the processing speed Ta...

Page 58: ...ister addressing mode Table 2 6 Absolute Address Accessing Classification SH7000 Series CPU Conventional CPU Absolute address MOV L disp PC R1 MOV B R1 R0 DATA L H 12345678 MOV B H 12345678 R0 Note The address of the immediate data is accessed by disp PC 16 32 Bit Displacement When data is accessed by 16 bit or 32 bit displacement the pre existing displacement value is placed in the memory table B...

Page 59: ...ster addressing Rn The effective address is the contents of register Rn A constant is added to the contents of Rn after the instruction is executed 1 is added for a byte operation 2 for a word operation and 4 for a longword operation Rn Rn 1 2 4 Rn 1 2 4 Rn After the instruction is executed Byte Rn 1 Rn Word Rn 2 Rn Longword Rn 4 Rn Pre decre ment indirect register addressing Rn The effective addr...

Page 60: ... disp zero extended Byte Rn disp Word Rn disp 2 Longword Rn disp 4 Indirect indexed register addressing R0 Rn Rn R0 Rn R0 Rn R0 Indirect GBR addressing with displace ment disp 8 GBR The effective address is the GBR value plus an 8 bit displacement disp The value of disp is zero extended and remains the same for a byte operation is doubled for a word operation and is quadrupled for a longword opera...

Page 61: ...ation For a longword operation the lowest two bits of the PC are masked PC H FFFFFFFC PC disp 2 or PC H FFFFFFFC disp 4 2 4 disp zero extended For longword Word PC disp 2 Longword PC H FFFFFFFC disp 4 PC relative addressing disp 8 The effective address is the PC value sign extended with an 8 bit displacement disp doubled and added to the PC PC 2 disp zero extended PC disp 2 PC disp 2 disp 12 The e...

Page 62: ... bit immediate data imm for the MOV ADD and CMP EQ instructions is sign extended imm 8 Immediate data imm for the TRAPA instruction is zero extended and is quadrupled 2 3 3 Instruction Formats The instruction format refers to the source operand and the destination operand The meaning of the operand depends on the instruction code Symbols are as follows xxxx Instruction code mmmm Source register nn...

Page 63: ... MOVT Rn Control register or system register nnnn Register direct STS MACH Rn Control register or system register nnnn Register indirect with pre decrement STC L SR Rn m format xxxx mmmm xxxx xxxx 15 0 mmmm Register direct Control register or system register LDC Rm SR mmmm Register indirect with post increment Control register or system register LDC L Rm SR mmmm Register indirect JMP Rm ...

Page 64: ...h post increment nnnn Register direct MOV L Rm Rn mmmm Register direct nnnn Register indirect with pre decrement MOV L Rm Rn mmmm Register direct nnnn Indexed register indirect MOV L Rm R0 Rn md format xxxx dddd 15 0 mmmm xxxx mmmmdddd Register indirect with displacement R0 Register direct MOV B disp Rn R0 nd4 format xxxx xxxx dddd 15 0 nnnn R0 Register direct nnnndddd Register indirect with displ...

Page 65: ...dddddd PC relative BF label d12 format dddd xxxx 15 0 dddd dddd dddddddddddd PC relative BRA label label disp PC nd8 format dddd nnnn xxxx 15 0 dddd dddddddd PC relative with displacement nnnn Register direct MOV L disp PC Rn i format iiiiiiii Immediate Indexed GBR indirect AND B imm R0 GBR xxxx xxxx i i i i 15 0 i i i i iiiiiiii Immediate R0 Register direct AND imm R0 iiiiiiii Immediate TRAPA imm...

Page 66: ...of the middle of registers connected Arithmetic 17 ADD Binary addition 28 operations ADDC Binary addition with carry ADDV Binary addition with overflow check CMP cond Comparison DIV1 Division DIV0S Initialization of signed division DIV0U Initialization of unsigned division EXTS Sign extension EXTU Zero extension MAC Multiplication and accumulation MULS Signed multiplication MULU Unsigned multiplic...

Page 67: ... SHLLn n bit logical left shift SHLR One bit logical right shift SHLRn n bit logical right shift Branch 7 BF Conditional branch T 0 7 BT Conditional branch T 1 BRA Unconditional branch BSR Branch to subroutine procedure JMP Unconditional branch JSR Branch to subroutine procedure RTS Return from subroutine procedure System 11 CLRT T bit clear 31 control CLRMAC MAC register clear LDC Load to control...

Page 68: ...sive OR of each bit Logical NOT of each bit n bit shift Execution Value when no wait states are inserted cycle Instruction execution cycles The execution cycles shown in the table are minimums The actual number of cycles may be increased 1 When contention occurs between instruction fetches and data access or 2 When the destination register of the load instruction memory register and the register u...

Page 69: ... 0110nnnnmmmm0010 Rm Rn 1 MOV B Rm Rn 0010nnnnmmmm0100 Rn 1 Rn Rm Rn 1 MOV W Rm Rn 0010nnnnmmmm0101 Rn 2 Rn Rm Rn 1 MOV L Rm Rn 0010nnnnmmmm0110 Rn 4 Rn Rm Rn 1 MOV B Rm Rn 0110nnnnmmmm0100 Rm Sign extension Rn Rm 1 Rm 1 MOV W Rm Rn 0110nnnnmmmm0101 Rm Sign extension Rn Rm 2 Rm 1 MOV L Rm Rn 0110nnnnmmmm0110 Rm Rn Rm 4 Rm 1 MOV B R0 disp Rn 10000000nnnndddd R0 disp Rn 1 MOV W R0 disp Rn 10000001nn...

Page 70: ...GBR 1 MOV W R0 disp GBR 11000001dddddddd R0 disp 2 GBR 1 MOV L R0 disp GBR 11000010dddddddd R0 disp 4 GBR 1 MOV B disp GBR R0 11000100dddddddd disp GBR Sign extension R0 1 MOV W disp GBR R0 11000101dddddddd disp 2 GBR Sign extension R0 1 MOV L disp GBR R0 11000110dddddddd disp 4 GBR R0 1 MOVA disp PC R0 11000111dddddddd disp 4 PC R0 1 MOVT Rn 0000nnnn00101001 T Rn 1 SWAP B Rm Rn 0110nnnnmmmm1000 R...

Page 71: ...P GE Rm Rn 0011nnnnmmmm0011 If Rn Rm with signed data 1 T 1 Comparison result CMP HI Rm Rn 0011nnnnmmmm0110 If Rn Rm with unsigned data 1 T 1 Comparison result CMP GT Rm Rn 0011nnnnmmmm0111 If Rn Rm with signed data 1 T 1 Comparison result CMP PZ Rn 0100nnnn00010001 If Rn 0 1 T 1 Comparison result CMP PL Rn 0100nnnn00010101 If Rn 0 1 T 1 Comparison result CMP STR Rm Rn 0010nnnnmmmm1100 If Rn and R...

Page 72: ...n Rm MAC MAC 3 2 MULS Rm Rn 0010nnnnmmmm1111 Signed operation of Rn Rm MAC 1 3 MULU Rm Rn 0010nnnnmmmm1110 Unsigned operation of Rn Rm MAC 1 3 NEG Rm Rn 0110nnnnmmmm1011 0 Rm Rn 1 NEGC Rm Rn 0110nnnnmmmm1010 0 Rm T Rn Borrow T 1 Borrow SUB Rm Rn 0011nnnnmmmm1000 Rn Rm Rn 1 SUBC Rm Rn 0011nnnnmmmm1010 Rn Rm T Rn Borrow T 1 Borrow SUBV Rm Rn 0011nnnnmmmm1011 Rn Rm Rn Underflow T 1 Underflow Note The...

Page 73: ... imm R0 11001011iiiiiiii R0 imm R0 1 OR B imm R0 GBR 11001111iiiiiiii R0 GBR imm R0 GBR 3 TAS B Rn 0100nnnn00011011 If Rn is 0 1 T 1 MSB of Rn 4 Test result TST Rm Rn 0010nnnnmmmm1000 Rn Rm if the result is 0 1 T 1 Test result TST imm R0 11001000iiiiiiii R0 imm if the result is 0 1 T 1 Test result TST B imm R0 GBR 11001100iiiiiiii R0 GBR imm if the result is 0 1 T 3 Test result XOR Rm Rn 0010nnnnm...

Page 74: ...Rn 8 Rn 1 SHLR8 Rn 0100nnnn00011001 Rn 8 Rn 1 SHLL16 Rn 0100nnnn00101000 Rn 16 Rn 1 SHLR16 Rn 0100nnnn00101001 Rn 16 Rn 1 Table 2 16 Branch Instructions Instruction Instruction Code Operation Execution Cycles T Bit BF label 10001011dddddddd If T 0 disp 2 PC PC if T 1 nop 3 1 BT label 10001001dddddddd If T 1 disp 2 PC PC if T 0 nop 3 1 BRA label 1010dddddddddddd Delayed branch disp 2 PC PC 2 BSR la...

Page 75: ... MACL 1 LDS Rm PR 0100mmmm00101010 Rm PR 1 LDS L Rm MACH 0100mmmm00000110 Rm MACH Rm 4 Rm 1 LDS L Rm MACL 0100mmmm00010110 Rm MACL Rm 4 Rm 1 LDS L Rm PR 0100mmmm00100110 Rm PR Rm 4 Rm 1 NOP 0000000000001001 No operation 1 RTE 0000000000101011 Delayed branch stack area PC SR 4 SETT 0000000000011000 1 T 1 1 SLEEP 0000000000011011 Sleep 3 STC SR Rn 0000nnnn00000010 SR Rn 1 STC GBR Rn 0000nnnn00010010...

Page 76: ...Rn 0100nnnn00010010 Rn 4 Rn MACL Rn 1 STS L PR Rn 0100nnnn00100010 Rn 4 Rn PR Rn 1 TRAPA imm 11000011iiiiiiii PC SR stack area imm 4 VRR PC 8 Note The execution cycles shown in the table are minimums The actual number of cycles may be increased 1 When contention occurs between instruction fetches and data access 2 When the destination register of the load instruction memory register and the regist...

Page 77: ...CH Rn STS MACL Rn STS PR Rn 0000 Rn Rm 1011 0000 Rn Rm 11MD MOV B R0 Rm Rn MOV W R0 Rm Rn MOV L R0 Rm Rn 0001 Rn Rm disp MOV L Rm disp 4 Rn 0010 Rn Rm 00MD MOV B Rm Rn MOV W Rm Rn MOV L Rm Rn 0010 Rn Rm 01MD MOV B Rm Rn MOV W Rm Rn MOV L Rm Rn DIV0S Rm Rn 0010 Rn Rm 10MD TST Rm Rn AND Rm Rn XOR Rm Rn OR Rm Rn 0010 Rn Rm 11MD CMP STR Rm Rn XTRCT Rm Rn MULU Rm Rn MULS Rm Rn 0011 Rn Rm 00MD CMP EQ Rm...

Page 78: ...Fx 1011 JSR Rm TAS B Rn JMP Rm 0100 Rm Fx 1100 0100 Rm Fx 1101 0100 Rn Fx 1110 LDC Rm Sr LDC Rm GBR LDC Rm VBR 0100 Rn Rm 1111 MAC W Rm Rn 0101 Rn Rm disp MOV L disp 4 Rm Rn 0110 Rn Rm 00MD MOV B Rm Rn MOV W Rm Rn MOV L Rm Rn MOV Rm Rn 0110 Rn Rm 01MD MOV B Rm Rn MOV W Rm Rn MOV L Rm Rn NOT Rm Rn 0110 Rn Rm 10MD SWAP B Rm Rn SWAP W Rm Rn NEGC Rm Rn NEG Rm Rn 0110 Rn Rm 11MD EXTU B Rm Rn EXTU W Rm ...

Page 79: ...R MOV W R0 disp 8 GBR MOV L R0 disp 8 GBR TRAPA imm 8 1100 01MD disp MOV B disp 8 GBR R0 MOV W disp 8 GBR R0 MOV L disp 8 GBR R0 MOVA disp 8 PC R0 1100 10MD imm TST imm 8 R0 AND imm 8 R0 XOR imm 8 R0 OR imm 8 R0 1100 11MD imm TST B imm 8 R0 GBR AND B imm 8 R0 GBR XOR B imm 8 R0 GBR OR B imm 8 R0 GBR 1101 Rn disp MOV L disp 8 PC Rn 1110 Rn imm MOV imm 8 Rn 1111 ...

Page 80: ...ception handling bus released program execution and power down The transitions between the states are shown in figure 2 6 For more information on the reset and exception handling states see section 4 Exception Handling For details on the power down state see section 19 Power Down State ...

Page 81: ...curs Exception handling ends Bus request generated Exception handling source occurs Bus request cleared Bus request generated Bus request cleared SLEEP instruction with SBY bit cleared SLEEP instruction with SBY bit set From any state when RES 0 and NMI 1 From any state when RES 0 and NMI 0 Reset states Power down state Bus request generated Bus request cleared Standby mode Sleep mode Figure 2 6 T...

Page 82: ...terrupts In a reset the initial values of the program counter PC execution start address and stack pointer SP are fetched from the exception vector table and stored the CPU then branches to the execution start address and execution of the program begins For an interrupt the stack pointer SP is accessed and the program counter PC and status register SR are saved to the stack area The exception hand...

Page 83: ...e all CPU on chip supporting module and oscillator functions are halted CPU internal register contents and on chip RAM data are held Standby mode is cleared by a reset or an external NMI interrupt For resets the CPU returns to the ordinary program execution state through the exception handling state when placed in a reset state during the oscillator settling time For NMI interrupts the CPU returns...

Page 84: ... bits Mode 1 2 0 0 1 MCU mode 1 16 bits Mode 2 0 1 0 MCU mode 2 On chip ROM Mode 7 1 1 1 1 PROM mode Notes 1 SH7034 PROM version only 2 Only modes 0 and 1 are available in the SH7032 and SH7034 ROMless version 3 2 Operating Mode Descriptions 3 2 1 Mode 0 MCU Mode 0 In mode 0 memory area 0 has an eight bit bus width For the memory map see section 8 Bus State Controller BSC 3 2 2 Mode 1 MCU Mode 1 I...

Page 85: ...50 ...

Page 86: ...riorities As figure 4 1 indicates exception handling may be caused by a reset address error interrupt or instruction Exception sources are prioritized as indicated in figure 4 1 If two or more exceptions occur simultaneously they are accepted and handled in the priority order shown ...

Page 87: ...oller A D converter Watchdog timer DRAM refresh control unit part of the bus controller Instruction Trap instruction Illegal slot instruction General illegal instruction TRAPA instruction Undefined instruction or instruction that rewrites the PC 1 placed directly after a delayed branch instruction 2 Undefined code Notes 1 The instructions that rewrite the PC are JMP JSR BRA BSR RTS RTE BT BF and T...

Page 88: ...when undefined code or an instruction that rewrites the PC is decoded directly after a delayed branch instruction in a delay slot When exception handling begins the CPU operates as follows Resets The initial values of the program counter PC and stack pointer SP are read from the exception vector table the respective PC and SP values are H 00000000 and H 00000004 for a power on reset and H 00000008...

Page 89: ...fferent vector numbers and vector table address offsets are assigned to different exception sources The vector table addresses are calculated from the corresponding vector numbers and vector address offsets In exception handling the exception handling routine start address is fetched from the exception vector table indicated by this vector table address Table 4 2 lists vector numbers and vector ta...

Page 90: ...11 H 0000002C H 0000002F User break 12 H 00000030 H 00000033 Reserved for system use 13 31 H 00000034 H 00000037 to H 0000007C H 0000007F Trap instruction user vectors 32 63 H 00000080 H 00000083 to H 000000FC H 000000FF Interrupts IRQ0 64 H 00000100 H 00000103 IRQ1 65 H 00000104 H 00000107 IRQ2 66 H 00000108 H 0000010B IRQ3 67 H 0000010C H 0000010F IRQ4 68 H 00000110 H 00000113 IRQ5 69 H 00000114...

Page 91: ...e highest priority exception There are two types of reset power on reset and manual reset As table 4 4 shows a power on reset initializes the internal state of the CPU and all registers of the on chip supporting modules A manual reset initializes the internal state of the CPU and all registers of the on chip supporting modules except the bus state controller BSC pin function controller PFC and I O...

Page 92: ... read from the exception vector table into the PC and SP and starts program execution A power on reset must be executed when turning on power 4 2 3 Manual Reset When the NMI pin is high a low input at the RES pin drives the chip into the manual reset state To ensure that the chip is properly reset drive the RES pin low for at least 20 tcyc A manual reset initializes the internal state of the CPU a...

Page 93: ...ord or byte data in on chip supporting module space None normal Access to longword data in 16 bit on chip supporting module space None normal Access to longword data in 8 bit on chip supporting module space Address error Note See section 8 Bus State Controller BSC for details on the on chip supporting module space 4 3 2 Address Error Exception Handling When an address error occurs address error ex...

Page 94: ...3 Interrupt Exception Vectors and Rankings in section 5 Interrupt Controller INTC for details on vector numbers and vector table address offsets 4 4 2 Interrupt Priority Rankings Interrupt sources are assigned priorities When multiple interrupts occur at the same time the interrupt controller INTC ascertains their priorities and starts exception handling based on its findings Priorities from 16 0 ...

Page 95: ...nterrupt mask bits I3 I0 of SR When an interrupt is accepted interrupt exception handling begins In the interrupt exception handling sequence the SR and PC values are pushed onto the stack and the priority level of the accepted interrupt is copied to the interrupt mask level bits I3 I0 in SR In NMI exception handling the priority ranking is 16 but the value 15 H F is stored in I3 I0 The exception ...

Page 96: ...nstructions that rewrite the PC are JMP JSR BRA BSR RTS RTE BT BF and TRAPA General illegal instructions Undefined code in other than delay slot 4 5 2 Trap Instruction Trap instruction exception handling is carried out when a trap instruction TRAPA is executed The CPU then 1 Saves the status register by pushing register contents onto the stack 2 Pushes the program counter value onto the stack The ...

Page 97: ... value onto the stack The PC value saved is the branch destination address of the delayed branch instruction immediately before the instruction that contains the undefined code or rewrites the PC 3 Fetches the exception handling routine start address from the vector table corresponding to the exception that occurred branches to that address and starts executing the program The branch is not a dela...

Page 98: ... 2 O X X Not accepted O Accepted Notes 1 Delayed branch instructions JMP JSR BRA BSR RTS RTE 2 Interrupt disabled instructions LDC LDC L STC STC L LDS LDS L STS STS L 4 6 1 Immediately after Delayed Branch Instruction Address errors and interrupts are not accepted when an instruction in a delay slot immediately following a delayed branch instruction is decoded The delayed branch instruction and th...

Page 99: ...s Upper 16 bits Lower 16 bits SR Address of instruction after instruc tion that has finished executing SP Trap instruc tion Upper 16 bits Lower 16 bits Upper 16 bits Lower 16 bits SR Address of instruction after TRAPA instruction SP Illegal slot instruc tion Upper 16 bits Lower 16 bits Upper 16 bits Lower 16 bits SR Branch destination address of delayed branch instuction SP General illegal instruc...

Page 100: ...in the exception handling interrupt etc stacking After the exception handling ends the CPU will then shift to address error exception handling An address error will also occur during the address error exception handling stacking but the CPU is set up to ignore the address error so that it can avoid an infinite series of address errors This allows it to shift program control to the address error ex...

Page 101: ...66 ...

Page 102: ... of interrupt priorities for IRQ and on chip supporting module interrupt sources NMI noise canceller function INTC has an NMI input level bit that indicates the NMI pin status By reading this bit in the interrupt exception handling routine the pin status can be checked for use in a noise canceller function The interrupt controller can notify external devices via the IRQOUT pin that an on chip inte...

Page 103: ... I2 I1 I0 INTC IRQOUT NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 UBC DMAC ITU SCI PRT A D WDT REF UBC User break controller WDT Watchdog timer DMAC Direct memory access controller REF DRAM refresh control unit of BSC ITU 16 bit integrated timer pulse unit ICR Interrupt control register SCI Serial communication interface IPRA IPRE Interrupt priority registers A E PRT Parity control unit of BSC SR ...

Page 104: ...ling the detection of external interrupt input signals Table 5 2 Interrupt Controller Register Configuration Name Abbr R W Address 2 Initial Value Bus width Interrupt priority register A IPRA R W H 5FFFF84 H 0000 8 16 32 Interrupt priority register B IPRB R W H 5FFFF86 H 0000 8 16 32 Interrupt priority register C IPRC R W H 5FFFF88 H 0000 8 16 32 Interrupt priority register D IPRD R W H 5FFFF8A H ...

Page 105: ... A user break interrupt occurs when a break condition is satisfied in the user break controller UBC A user break interrupt has priority level 15 User break interrupt exception handling sets the interrupt mask level bits I3 I0 in the status register SR to level 15 For further details on the user break interrupt see section 6 User Break Controller UBC 5 2 3 IRQ Interrupts IRQ interrupts are requeste...

Page 106: ...terrupt sources Each interrupt source is allocated a different vector number and vector table address offset The vector table address is calculated from this vector number and address offset In interrupt exception handling the exception handling routine start address is fetched from the vector table indicated by this vector table address See table 4 3 Calculation of Exception Vector Table Address ...

Page 107: ... IPRB 3 0 71 H 0000011C H 0000011F DMAC0 DEI0 0 15 0 IPRC 15 12 3 72 H 00000120 H 00000123 Reserved 2 73 H 00000124 H 00000127 DMAC1 DEI1 1 74 H 00000128 H 0000012B Reserved 0 75 H 0000012C H 0000012F DMAC2 DEI2 0 15 0 IPRC 11 8 3 76 H 00000130 H 00000133 Reserved 2 77 H 00000134 H 00000137 DMAC3 DEI3 1 78 H 00000138 H 0000013B Reserved 0 79 H 0000013C H 0000013F ITU0 IMIA0 0 15 0 IPRC 7 4 3 80 H ...

Page 108: ...H 00000193 RxI0 2 101 H 00000194 H 00000197 TxI0 1 102 H 00000198 H 0000019B TEI0 0 103 H 0000019C H 0000019F SCI1 ERI1 0 15 0 IPRE 15 12 3 104 H 000001A0 H 000001A3 RxI1 2 105 H 000001A4 H 000001A7 TxI1 1 106 H 000001A8 H 000001AB TEI1 0 107 H 000001AC H 000001AF PRT 1 PEI 0 15 0 IPRE 11 8 3 108 H 000001B0 H 000001B3 A D ITI 2 109 H 000001B4 H 000001B7 Reserved 1 110 H 000001B8 H 000001BB Reserve...

Page 109: ...bus state controller See section 8 Bus State Controller BSC for details 2 REF DRAM refresh control unit of bus controller See section 8 Bus State Controller BSC for details 3 Always read as 0 Always write 0 in reserved bits As indicated in table 5 4 four IRQ pins or four groups of on chip supporting modules are assigned to each interrupt priority register The priority levels for the four pins or g...

Page 110: ... NMIL cannot be modified The NMI input level can be read to determine the NMI pin level Bit 15 NMIL Description 0 NMI input level is low 1 NMI input level is high Bits 14 9 Reserved These bits are always read as 0 The write value should always be 0 Bit 8 NMI Edge Select NMIE NMIE selects whether the falling or rising edge of the interrupt request signal at the NMI pin is sensed Bit 8 NMIE Descript...

Page 111: ... executing that instruction the CPU starts interrupt exception handling See figure 5 4 6 In interrupt exception handling first SR and PC are pushed onto the stack 7 The priority level of the accepted interrupt is copied to the interrupt mask level bits I3 I0 in the status register SR 8 When the accepted interrupt is level sensed or from an on chip supporting module the IRQOUT pin returns to the hi...

Page 112: ...e interrupt request signal to the CPU figure 5 1 The IRQOUT pin returns to the high level when the interrupt controller has accepted the interrupt of a level higher than that specified by bits I3 to I0 in the CPU s status register 2 If the accepted interrupt is edge sensed the IRQOUT pin returns to the high level when the instruction to be executed by the CPU is replaced by interrupt exception han...

Page 113: ...its Lower 16 bits Upper 16 bits Lower 16 bits SR PC 1 Address 4n 8 4n 6 4n 4 4n 2 4n SP 2 Notes Bus width is 16 bits 1 PC stores the start address of the next instruction return instruction after the executed instruction 2 The value of SP must always be a multiple of four Figure 5 3 Stack after Interrupt Exception Handling ...

Page 114: ...The longest sequence is the interrupt or address error exception handling sequence X 4 m1 m2 m3 m4 If an interrupt masking instruction follows however the time may be longer Time from interrupt exception handling saving PC and SR and fetching vector address until fetching of first instruction of interrupt handling routine starts 5 m1 m2 m3 Interrupt Total 7 m1 m2 m3 8 m1 m2 m3 response Minimum 10 ...

Page 115: ...ption Handling Operation IRQOUT Figure 5 4 Example of Pipelining in IRQ Interrupt Acceptance 5 6 Usage Notes When the following operations are performed in the order shown when a pin to which IRQ input is assigned is designated as a general input pin by the pin function controller PFC and inputs a low level signal the IRQ falling edge is detected and an interrupt request is detected immediately af...

Page 116: ... debugger enabling a program to be debugged by itself without using a large in circuit emulator 6 1 1 Features The following break conditions can be set Address CPU cycle or DMA cycle Instruction fetch or data access Read or write Operand size longword access word access or byte access When break conditions are met a user break interrupt is generated A user created user break interrupt exception r...

Page 117: ...reak condition comparator Module bus BBR BAMRH BARH BAMRL BARL Interrupt request Interrupt controller User break interrupt generating circuit UBC BARH BARL Break address registers H and L BAMRH BAMRL Break address mask registers H and L BBR Break bus cycle register Figure 6 1 Block Diagram of User Break Controller ...

Page 118: ... register high BARH R W H 5FFFF90 H 0000 8 16 32 Break address register low BARL R W H 5FFFF92 H 0000 8 16 32 Break address mask register high BAMRH R W H 5FFFF94 H 0000 8 16 32 Break address mask register low BAMRL R W H 5FFFF96 H 0000 8 16 32 Break bus cycle register BBR R W H 5FFFF98 H 0000 8 16 32 Note Only the values of bits A27 A24 and A8 A0 are valid bits A23 A9 are ignored For details on t...

Page 119: ...BA26 BA25 BA24 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 Bit name BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W BARH Bits 15 0 Break Address 31 16 BA31 BA16 BA31 BA16 store the upper bit values bits 31 16 of the address of the break condition BARL Break address register L Bit 15 14 13 12 11 10 9...

Page 120: ... BAM22 BAM21 BAM20 BAM19 BAM18 BAM17 BAM16 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W BAMRH bits 15 0 Break Address Mask 31 16 BAM31 BAM16 BAM31 BAM16 specify whether bits BA31 BA16 of the break address set in BARH are masked or not BAMRL Break address mask register L Bit 15 14 13 12 11 10 9 8 Bit name BAM15 BAM14 BAM13 BAM12 BAM11 BAM10 BAM9 BAM8 Initial value 0 0 0 0 0 0 0...

Page 121: ...10 9 8 Bit name Initial value 0 0 0 0 0 0 0 0 R W Bit 7 6 5 4 3 2 1 0 Bit name CD1 CD0 ID1 ID0 RW1 RW0 SZ1 SZ0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bits 15 8 Reserved These bits are always read as 0 The write value should always be 0 Bits 7 and 6 CPU Cycle DMA Cycle Select CD1 and CD0 CD1 and CD0 select whether to break on CPU and or DMA bus cycles Bit 7 CD1 Bit 6 CD0 ...

Page 122: ...cycles 1 0 Break only on write cycles 1 Break on both read and write cycles Bits 1 and 0 Operand Size Select SZ1 SZ0 SZ1 and SZ0 select the bus cycle operand size as a break condition Bit 1 SZ1 Bit 0 SZ0 Description 0 0 Operand size is not a break condition Initial value 1 Break on byte access 1 0 Break on word access 1 Break on longword access Note When setting a break on an instruction fetch cle...

Page 123: ...reak conditions are satisfied the UBC sends a user break interrupt request to the interrupt controller 3 On receiving the user break interrupt request the interrupt controller checks its priority level The user break interrupt has priority level 15 so it is accepted only if the interrupt mask level in bits I3 I0 in the status register SR is 14 or lower When the I3 I0 bit level is 15 the user break...

Page 124: ...pt RW1 RW0 ID1 ID0 CD1 CD0 BARH BARL BAMRH BAMRL 32 32 32 32 32 Internal address bits 31 0 CPU cycle DMA cycle Instruction fetch Data access Read cycle Write cycle Byte size Word size Longword size Figure 6 2 Break Condition Logic ...

Page 125: ...on The user break interrupt is generated before the fetched instruction is executed If a break condition is set on the fetch cycle of a delayed slot instruction immediately following a delayed branch instruction or on the fetch cycle of an instruction that follows an interrupt disabling instruction however the user break interrupt is not accepted immediately so the instruction is executed The user...

Page 126: ... conditions No user break interrupt occurs because instructions are always fetched from even addresses If the first fetched address after a branch is odd and a user break is set on this address however user break exception handling will be carried out after address error exception handling CPU Data Access Bus Cycle Register settings BARH H 0012 BARL H 3456 BBR H 006A Conditions set Address H 00123...

Page 127: ... instruction overrun fetch Next but one instruction overrun fetch Branch destination fetch Instruction execution Conditional branch instruction execution Branch destination instruction execution 2 TRAPA instruction branch taken TRAPA Instruction fetch cycles TRAPA instruction fetch Next instruction overrun fetch Next but one instruction overrun fetch Branch destination fetch Instruction execution ...

Page 128: ...n fetch Task B first instruction fetch instruction replaced by interrupt exception handling 0xf000978 Overrun fetch UBC first instruction fetch 0x00011a0a 0x00011a0c 0xf000974 0x02000030 f Figure 6 3 UBC Operation It actually takes at least two cycles for the UBC interrupt generated by the address 0x00011a0c instruction fetch cycle to be sent to the interrupt controller and interrupt exception han...

Page 129: ...94 ...

Page 130: ...ty cycle correction circuit Internal clock φ CPG Figure 7 1 Block Diagram of Clock Pulse Generator 7 2 Clock Source Clock pulses can be supplied from a connected crystal resonator or an external clock 7 2 1 Connecting a Crystal Resonator Circuit Configuration A crystal resonator can be connected as shown in figure 7 2 Use the damping resistance Rd shown in table 7 1 Use an AT cut parallel resonati...

Page 131: ...00 200 0 0 0 Crystal Resonator Figure 7 3 shows an equivalent circuit of the crystal resonator Use a crystal resonator with the characteristics listed in table 7 2 C0 XTAL EXTAL CL L Rs Figure 7 3 Crystal Resonator Equivalent Circuit Table 7 2 Crystal Resonator Parameters Frequency MHz Parameter 2 4 8 12 16 20 Rs max Ω 500 120 80 60 50 40 Co max pF 7 7 7 7 7 7 ...

Page 132: ...en below Make the external clock frequency the same as the system clock CK XTAL EXTAL Open External clock input Figure 7 4 External Clock Input Method tEXr tEXf VIL VIH 1 2 Vcc tEXH tEXL tcyc Figure 7 5 Input Clock Waveform Table 7 3 Input Clock Specifications 5 V Specifications fmax 20 MHz 1 3 3 V Specifications fmax 12 5 MHz 3 3 V Specifications fmax 20 MHz 2 Unit tEXr f VIL VIH Max 5 Max 10 Max...

Page 133: ...sign Duty Cycle Correction Circuit Duty cycle corrections are conducted for an input clock over 5 MHz Duty cycles may not be corrected for a clock of under 5 MHz but AC characteristics for the high level pulse width tCH and low level pulse width tCL of the clock are satisfied and the chip will operate normally Figure 7 7 shows the standard characteristics of duty cycle correction This duty cycle c...

Page 134: ...1 2 5 10 20 MHz 70 60 50 40 30 Input duty Input frequency Note With the SH7034B compensation is performed in the input duty range of 60 to 40 Output duty Figure 7 7 Duty Cycle Correction Circuit Standard Characteristics ...

Page 135: ...100 ...

Page 136: ...e inserted using the WAIT pin Wait state insertion can be controlled by software Register settings can be used to specify the insertion of 1 4 cycles for areas 0 2 and 6 long wait function The type of memory connected can be specified for each area Outputs control signals for accessing the memory and peripheral chips connected to the area Direct interface to DRAM Multiplexes row column addresses a...

Page 137: ...erface Area control unit Comparator Module bus RD WRH WRL HBS LBS AH CS7 to CS0 RAS Wait control unit DRAM control unit Parity control unit Peripheral bus BSC WCR Wait state control register RTCSR Refresh timer control status register BCR Bus control register RTCNT Refresh timer counter DCR DRAM area control register RTCOR Refresh time constant register RCR Refresh control register PCR Parity cont...

Page 138: ...be CASH O Column address strobe signal for accessing the upper 8 bits of the DRAM Low column address strobe CASL O Column address strobe signal for accessing the lower 8 bits of the DRAM Address hold AH O Signal for holding the address for address data multiplexing Wait WAIT I Wait state request signal Address bus A21 A0 O Address output Data bus AD15 AD0 I O Data I O During address data multiplex...

Page 139: ...5FFFFA6 8 16 32 DRAM area control register DCR R W H 0000 H 5FFFFA8 8 16 32 Parity control register PCR R W H 0000 H 5FFFFAA 8 16 32 Refresh control register RCR R W H 0000 H 5FFFFAC 8 16 32 2 Refresh timer control status register RTCSR R W H 0000 H 5FFFFAE 8 16 32 2 Refresh timer counter RTCNT R W H 0000 H 5FFFFB0 8 16 32 2 Refresh time constant register RTCOR R W H 00FF H 5FFFFB2 8 16 32 2 Notes...

Page 140: ... CAS and multiplexed addresses Areas 2 4 can only be used as external memory space Area 5 can be used as on chip supporting module space or external memory space Area 6 can be used as address data multiplexed I O space or external memory space For address data multiplexed I O space an address and data are multiplexed and input output from pins AD15 AD0 Area 7 can be used as on chip RAM space or ex...

Page 141: ...AS CAS 2 H A000000 H AFFFFFF External memory 4 MB 16 CS2 3 H B000000 H BFFFFFF External memory 4 MB 16 CS3 4 H C000000 H CFFFFFF External memory 4 MB 16 CS4 5 H D000000 H DFFFFFF External memory 4 MB 16 CS5 6 H E000000 H EFFFFFF External memory 4 MB 16 CS6 7 H F000000 H FFFFFFF On chip RAM 8 kB 8 4 kB 9 32 Notes 1 When MD2 MD0 pins are 010 SH7034 2 When MD2 MD0 pins are 000 or 001 3 Select with MD...

Page 142: ...an external memory space or DRAM space 0 sets it as external memory space and 1 sets it as DRAM space The setting of the DRAM area control register is valid only when this bit is set to 1 Bit 15 DRAME Description 0 Area 1 is external memory space Initial value 1 Area 1 is DRAM space Bit 14 Multiplexed I O Enable Bit IOE IOE selects whether area 6 is used as external memory space or an address data...

Page 143: ... as the high level duty cycle ratio of signal RD 0 sets 50 1 sets 35 Bit 12 RDDTY Description 0 RD signal high level duty cycle is 50 of T1 state Initial value 1 RD signal high level duty cycle is 35 of T1 state Bit 11 Byte Access Select BAS BAS selects whether byte access control signals are WRH WRL and A0 or LBS WR and HBS during word space accesses When this bit is cleared to 0 WRH WRL and A0 s...

Page 144: ... WAIT signal value For the external memory space of areas 0 2 and 6 read cycles are completed in one state plus the number of long wait states set in wait state controller 3 WCR3 when the corresponding bits are cleared to 0 When they are set to 1 the number of wait states is 1 plus the long wait state when the WAIT signal is low as well a wait state is inserted The DRAM space area 1 finishes the c...

Page 145: ...1 and RLW0 bits in RCR is inserted Bits 7 2 Reserved These bits are always read as 1 The write value should always be 1 Bit 1 Wait State Control During Write WW1 WW1 determines the number of states in write cycles for the DRAM space area 1 and whether or not to sample the WAIT signal When the DRAM enable bit DRAME in BCR is set to 1 and area 1 is being used as DRAM space clearing WW1 to 0 makes th...

Page 146: ...al is not sampled during the single mode DMA memory read cycle for the corresponding area If it is set to 1 sampling takes place For the external memory spaces of areas 1 3 5 and 7 single mode DMA memory read cycles are completed in one state when the corresponding bits are cleared to 0 When they are set to 1 the number of wait states is 2 plus the wait states from the WAIT signal For the external...

Page 147: ... 2 states wait state from WAIT long pitch Note Sampled in the address data multiplexed I O space Bits 7 0 Single Mode DMA Memory Write Wait State Control DWW7 DWW0 DWW7 DWW0 determine the number of states in single mode DMA memory write cycles for each area and whether or not to sample the WAIT signal Bits DWW7 DWW0 correspond to areas 7 0 respectively If a bit is cleared to 0 the WAIT signal is n...

Page 148: ...ycle 2 states wait state from WAIT long pitch Note Sampled in the address data multiplexed I O space 8 2 4 Wait State Control Register 3 WCR3 Wait state control register 3 is a 16 bit read write register that controls WAIT pin pull up and the insertion of long wait states WCR3 is initialized to H F800 by a power on reset It is not initialized by a manual reset or in standby mode Bit 15 14 13 12 11...

Page 149: ...1 A6LW0 Description 0 0 1 state inserted 1 2 states inserted 1 0 3 states inserted 1 4 states inserted Initial value Bits 10 0 Reserved These bits are always read as 0 The write value should always be 0 8 2 5 DRAM Area Control Register DCR The DRAM area control register DCR is a 16 bit read write register that selects the type of DRAM control signal the number of precharge cycles the burst operati...

Page 150: ...n 0 RAS up mode Return RAS signal to high and wait for the next DRAM access Initial value 1 RAS down mode Keep RAS signal low and wait for the next DRAM access Bit 13 RAS Precharge Cycle Count TPC TPC selects whether the RAS signal precharge cycle TP will be 1 state or 2 When TPC is cleared to 0 a 1 state precharge cycle is inserted when 1 is set a 2 state precharge cycle is inserted Bit 13 TPC De...

Page 151: ...d to 0 addresses are not multiplexed when set to 1 they are multiplexed Bit 10 MXE Description 0 Multiplexing of row and column addresses disabled Initial value 1 Multiplexing of row and column addresses enabled Bits 9 and 8 Multiplex Shift Count 1 and 0 MXC1 and MXC0 Shift row addresses downward by a certain number of bits 8 10 when row and column addresses are multiplexed MXE 1 Regardless of the...

Page 152: ...W R W Bit 15 8 Reserved These bits are always read as 0 Bit 7 Refresh Control RFSHE RFSHE determines whether or not to perform DRAM refresh operations When this bit is cleared to 0 no DRAM refresh control is performed and the refresh timer counter RTCNT can be used as an 8 bit interval timer When set to 1 DRAM refresh control is performed Bit 7 RFSHE Description 0 Refresh control disabled RTCNT ca...

Page 153: ...e bits are always read as 0 The write value should always be 0 8 2 7 Refresh Timer Control Status Register RTCSR The refresh timer control status register RTCSR is a 16 bit read write register that selects the clock input to the refresh timer counter RTCNT and controls compare match interrupts CMI It is initialized to H 0000 by a power on reset but is not initialized by a manual reset or in standb...

Page 154: ...pt CMI generated when CMF is set to 1 in RTCSR RTCNT value RTCOR value When cleared to 0 the CMI interrupt is disabled when set to 1 it is enabled Bit 6 CMIE Description 0 Compare match interrupt request CMI is disabled Initial value 1 Compare match interrupt request CMI is enabled Bits 5 3 Clock Select Bits 2 0 CKS2 CKS0 These bits select the clock input to RTCNT from among the seven types of clo...

Page 155: ...R from being written incorrectly it must be written by a different method from most other registers A word transfer operation is used H 69 is written in the upper byte and the actual data is written in the lower byte For details see section 8 2 11 Notes on Register Access Bit 15 14 13 12 11 10 9 8 Bit name Initial value 0 0 0 0 0 0 0 0 R W Bit 7 6 5 4 3 2 1 0 Bit name Initial value 0 0 0 0 0 0 0 0...

Page 156: ...15 14 13 12 11 10 9 8 Bit name Initial value 0 0 0 0 0 0 0 0 R W Bit 7 6 5 4 3 2 1 0 Bit name Initial value 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W 8 2 10 Parity Control Register PCR The parity control register PCR is a 16 bit read write register that selects the parity polarity and space to be parity checked PCR is initialized to H 0000 by a power on reset but is not initialized by a ...

Page 157: ... DPH and DPL pins when data is output regardless of the parity Bit 14 PFRC Description 0 Parity output not forced Initial value 1 High output forced Bit 13 Parity Polarity PEO PEO selects even or odd parity When cleared to 0 parity is even when set to 1 parity is odd Bit 13 PEO Description 0 Even parity Initial value 1 Odd parity Bits 12 and 11 Parity Check Enable Bits 1 and 0 PCHK1 and PCHK0 Thes...

Page 158: ...byte and the write data in the lower byte When writing to RTCNT place H 69 in the upper byte and the write data in the lower byte When writing to RTCOR place H 96 in the upper byte and the write data in the lower byte These transfers write data in the lower byte of the respective registers If the upper byte differs from the above passwords no writing occurs H 5A Write data RCR 15 0 8 7 H A5 Write ...

Page 159: ...y 4 Gbyte space 16 Mbyte space 4 Mbyte space 128 Mbyte space Figure 8 3 Address Format Since this chip uses a 32 bit address 4 Gbytes of space can be accessed in the architecture however the upper 4 bits A31 A28 are always ignored and not output Bit A27 is basically only used for switching the bus width When the A27 bit is 0 H 0000000 H 7FFFFFF the bus width is 8 bits when the A27 bit is 1 H 80000...

Page 160: ...CAS 2 H A000000 H AFFFFFF External memory 4 MB 16 CS2 3 H B000000 H BFFFFFF External memory 4 MB 16 CS3 4 H C000000 H CFFFFFF External memory 4 MB 16 CS4 5 H D000000 H DFFFFFF External memory 4 MB 16 CS5 6 H E000000 H EFFFFFF External memory 4 MB 16 CS6 7 H F000000 H FFFFFFF On chip RAM 8 kB 8 4 kB 9 32 Notes 1 When MD2 MD0 pins are 010 SH7034 2 When MD2 MD0 pins are 000 or 001 3 Select with MD0 p...

Page 161: ... 8 bit external memory space when the MD2 MD0 pins are 000 a 16 bit external memory space when these bits are 001 and a 32 bit on chip ROM space when they are 010 the on chip ROM is available only in the SH7034 Area 5 is an 8 bit on chip supporting module space when the A27 bit and A8 bit are both 0 and a 16 bit on chip supporting module space when the A27 bit is 0 and the A8 bit is 1 When the A27...

Page 162: ...ea for all areas is the 4 Mbytes that can be specified with the 22 bits A21 A0 Regardless of the values of A23 and A22 the same 4 Mbytes of actual space is accessed As illustrated in figure 8 4 a the A23 and A22 bit regions 00 01 10 and 11 are called shadows of actual areas Shadows are allocated in 4 Mbyte units for both 8 bit and 16 bit bus widths When the same addresses H 3200000 H 3600000 H 3A0...

Page 163: ...16 bit space 8 bit space H 33FFFFF H 37FFFFF H 3BFFFFF Actual space Location actually accessed Logical address space Location indicated by address Location indicated by address Location indicated by address Location indicated by address 8 bit space H 3000000 H 3200000 H 33FFFFF H 3400000 H 3600000 H 3A00000 H 3E00000 H 37FFFFF H 3800000 H 3BFFFFF H 3C00000 H 3FFFFFF a Shadow allocation b Actual sp...

Page 164: ...it is a 32 bit on chip ROM space In the SH7032 area 0 can only be used as external memory space since there is no on chip ROM and this last setting is meaningless The capacity of the on chip ROM is 64 kbytes so bits A23 A16 are ignored in on chip ROM space and the shadow is in 64 kbyte units The CS0 signal is disabled In external memory space the A23 and A22 bits are not output and the shadow is i...

Page 165: ...a 0 is determined by the MD2 MD0 pins regardless of the A27 bit setting Figure 8 5 Memory Map of Area 0 Area 1 Area 1 is an area with address bits A26 A24 set to 001 and an address range of H 1000000 H 1FFFFFF and H 9000000 H 9FFFFFF Figure 8 6 shows a memory map of area 1 Area 1 can be set for use as DRAM space or external memory space with the DRAM enable bit DRAME in the bus control register BC...

Page 166: ...address A21 A0 A23 and A22 not output CS1 valid DRAME 0 or DRAME 1 MXE 0 Logical address space H 9000000 H 9FFFFFF H 1000000 H 1FFFFFF DRAM space maximum 16 Mbytes DRAME 1 Logical address space Actual space A27 1 16 bit space A27 0 8 bit space A27 1 16 bit space Multiplexed MXE 1 16 bit space Not multi plexed MXE 0 4 Mbyte space CS1 not valid CAS RAS output Actual space Shadow Shadow Figure 8 6 Me...

Page 167: ...nd 4 states can be selected for the number of long waits inserted into the bus cycle using bits A02LW1 and A02LW0 in WCR3 H A000000 H A3FFFFF H A400000 H A7FFFFF H A800000 H ABFFFFF H AC00000 H AFFFFFF H 2000000 H 2400000 H 2800000 H 2C00000 H 23FFFFF H 27FFFFF H 2BFFFFF H 2FFFFFF Shadow Shadow Shadow Shadow External memory space 4 Mbytes Logical address space 16 bit space 8 bit space Actual space...

Page 168: ...d the shadow is in 4 Mbyte units The bus width is always 16 bits When external memory space is accessed the CS5 signal is valid H D000000 H D400000 H D800000 H DC00000 H D3FFFFF H D7FFFFF H DBFFFFF H DFFFFFF Shadow Shadow Shadow Shadow External memory space 4 Mbytes H 5000000 H 5FFFFFF Shadow Shadow Actual space Shadow Shadow Shadow Shadow H 5FFFE00 H 50001FF Logical address space 8 or 16 bit spac...

Page 169: ...bit is 0 and the A14 bit is 1 When the A27 bit is 1 it is always a 16 bit space The A23 and A22 bits are not output and the shadow is in 4 Mbyte units When external memory is accessed the CS6 signal is valid The external memory space has a long wait function so between 1 and 4 states can be selected for the number of long waits inserted into the bus cycle using the area 6 long wait insertion bits ...

Page 170: ...s are in 8 kbyte units In the SH7034 the on chip RAM capacity is 4 kbytes so A23 A12 are ignored and the shadows are in 4 kbyte units During on chip RAM access the CS7 signal is not valid H 7000000 H 7400000 H 7800000 H 7C00000 H 73FFFFF H 77FFFFF H 7BFFFFF H 7FFFFFF Shadow Shadow Shadow Shadow External memory space 4 Mbytes H F000000 H FFFFFFF Shadow Shadow Shadow Shadow Shadow Shadow H FFFF000 S...

Page 171: ...iplexed I O enable bit IOE bit in BCR is 0 or space where address bit A27 is 1 Area 7 space where address bit A27 is 0 8 4 1 Basic Timing The bus cycle for external memory space access is 1 or 2 states The number of states is controlled with wait states by the settings of wait state control registers 1 3 WCR1 WCR3 For details see section 8 4 2 Wait State Control Figures 8 11 and 8 12 illustrate th...

Page 172: ...nal Memory Space Access 2 State Read Timing High level duties of 35 and 50 can be selected for the RD signal using the RD duty bit RDDTY in BCR When RDDTY is set to 1 the high level duty is 35 of the T1 state enabling longer access times for external devices Only set to 1 when the operating frequency is a minimum of 10 MHz ...

Page 173: ...ate 1 wait state from WAIT signal Notes 1 The number of long wait states is set by WCR3 2 When DRAME 1 short pitch long pitch is selected with the WW1 bit in WCR1 3 Pin wait cannot be used for the CS7 and WAIT pins of area 3 because they are multiplexed For the CPU read cycle DMAC dual mode read cycle and DMAC single mode read write cycle the access cycle is completed in 1 state when the correspon...

Page 174: ...able between 1 and 4 and the WAIT pin input signal is not sampled When the bits are set to 1 the WAIT signal is sampled and the number of states is 1 plus the number of long wait states plus the number of wait states set by the WAIT signal The WAIT signal is sampled at the rise of the system clock CK directly preceding the last long wait state and the wait states are inserted as long as the level ...

Page 175: ... write cycles to external memory space the number of states and wait state insertion cannot be controlled by WCR1 In areas 1 3 4 5 and 7 the WAIT signal is sampled and the number of states is 2 plus the number of wait states set by the WAIT signal figure 8 13 In areas 0 2 and 6 the number of states is 1 state plus the number of long wait states plus the number of wait states set by the WAIT signal...

Page 176: ...External Memory Space Access Write Cycle The WRH WRL system and the HBS LBS system are available as byte access signals for 16 bit space in address data multiplexing space and external memory space These strobe signals are assigned to pins in the manner A0 HBS WRH LBS WRL WR and the BAS bit in the bus control register BCR is used to switch specify signal sending Note that the byte access signals a...

Page 177: ... control register DCR is set to 1 row addresses and column addresses are multiplexed This allows DRAMs that require multiplexing of row and column addresses to be connected directly to an SH microprocessor without additional multiplexing circuits When addresses are multiplexed MXE 1 setting of the DCR s multiplex shift bits MXC1 MXC0 allows selection of eight nine and ten bit row address shifting ...

Page 178: ...e A20 Value A20 A19 A19 A19 A19 A18 A18 A18 A18 A17 A17 A17 A17 A16 A16 A16 A16 A15 A23 A15 A15 A15 A14 A22 A14 A23 A14 A14 A13 A21 A13 A22 A13 A23 A13 A12 A20 A12 A21 A12 A22 A12 A11 A19 A11 A20 A11 A21 A11 A10 A18 A10 A19 A10 A20 A10 A9 A17 A9 A18 A9 A19 A9 A8 A16 A8 A17 A8 A18 A8 A7 A15 A7 A16 A7 A17 A7 A6 A14 A6 A15 A6 A16 A6 A5 A13 A5 A14 A5 A15 A5 A4 A12 A4 A13 A4 A14 A4 A3 A11 A3 A12 A3 A13...

Page 179: ...ypes of DRAM accesses short pitch and long pitch Short pitch or long pitch can be selected for the respective bus cycles using the RW1 and WW1 bits in WCR1 and the DRW1 and DWW1 bits in WCR2 When the corresponding bits are cleared to 0 DRAM access is short pitch and column address output occurs in 1 state When these bits are 1 DRAM access is long pitch and column address output occurs in 2 states ...

Page 180: ...145 CK A21 A0 RAS CAS WRH WRL AD15 AD0 Tp Write WRH WRL AD15 AD0 Read Tr Tc CDTY 0 CDTY 1 Row address Column address Figure 8 17 Short Pitch Access Timing ...

Page 181: ...y is raised and the cycle period shortened 1 cycle may not always be sufficient for the precharge time for the RAS signal when the DRAM is accessed The BSC allows the precharge cycle to be set to 1 state or 2 states using the RAS signal precharge cycles bit TPC in DCR When the TPC bit is 0 the precharge cycle is 1 state when TPC is 1 the precharge cycle is 2 states Figure 8 19 shows the timing whe...

Page 182: ...t signal is sampled on the rise of the system clock CK directly preceding the second state of the column address output cycle and the wait state is inserted as long as the level is low When a high level is detected it shifts to the second state Figure 8 20 shows the wait state timing in a long pitch bus cycle Tp Tr Tc1 Tcw wait state Tc2 Row address Column address CK A21 A0 RAS CAS WAIT Figure 8 2...

Page 183: ...l CAS signal or dual WE signal system of control signals When 16 bit space is being accessed and the CW2 bit is cleared to 0 for dual CAS signals CASH CASL and WRL signals are output when CW2 is set to 1 for dual WE signals the CASL WRH and WRL signals are output When accessing 8 bit space WRL and CASL are output regardless of the CW2 setting Figure 8 21 shows the control timing of the upper byte ...

Page 184: ... WRL Byte control Tp Tr Tc CK A21 A0 RAS CASH CASL WRH WRL Byte control Row address Column address Fixed high High a Dual CAS signals CW2 0 b Dual WE signals CW2 1 Fixed high High Figure 8 21 Byte Access Control Timing for DRAM Access Upper Byte Write Cycle Short Pitch ...

Page 185: ...22 shows a comparison between full access and burst operation RAS CAS AD15 AD0 RAS CAS A21 A0 AD15 AD0 A21 A0 Row address 1 Column address 1 Row address 2 Column address 2 Data 1 Data 2 Row address 1 Column address 1 Column address 2 Column address 3 Column address 4 Data 1 Data 2 Data 3 Data 4 a Full access read cycle b Burst operation read cycle Figure 8 22 Full Access and Burst Operation Short ...

Page 186: ...s the read cycle timing for short pitch high speed page mode Tp Tr Tc Tc CK A21 A0 RAS CAS Data 4 Data 3 Data 2 Data 1 Tc Tc WR AD15 A0 Column address 1 Column address 2 Column address 3 Column address 4 Row address 1 Figure 8 23 Short Pitch High Speed Page Mode Read Cycle When the write cycle continues for the same row address in short pitch high speed page mode an open cycle silent cycle is prod...

Page 187: ... spaces Figure 8 24 Short Pitch High Speed Page Mode Write Cycle Tp Tr Tc Tc CK A21 A0 RAS CAS Tc Tc WR AD15 AD0 Silent cycle Access A read Access B write Column address A 1 Column address A 2 Column address B 1 Column address B 2 Read data A 1 Read data A 2 Write data B 1 Write data B 2 Row address Note Accesses A and B are examples of 32 bit data accesses in their respective 16 bit bus width spa...

Page 188: ...the CAS signal and column address output cycles 2 states continue as long as the row addresses continue to match When the WAIT signal is detected at the low level the second cycle of the column address output cycle is repeated as the wait state Figure 8 26 shows the timing for long pitch high speed page mode See sections 20 1 3 3 and 20 2 3 3 Bus Timing for more information about the timing Tp Tr ...

Page 189: ...ext DRAM access is the same as the previous DRAM access burst operation continues Figure 8 27 shows the timing of RAS down mode when external memory space is accessed during burst operation The RAS signal can be held low in the DRAM for a limited time the RAS signal must be returned to high within the specified limits even when RAS down mode is selected since the critical low level period is set I...

Page 190: ...CBR or self refresh can be selected When no refresh is performed the refresh timer counter RTCNT can be used as an 8 bit interval timer CAS Before RAS Refresh CBR A refresh is performed at an interval determined by the input clock selected with clock select bits 2 0 CKS2 CKS0 in the refresh timer control status register RTCSR and the value set in the refresh time constant register RTCOR Set the va...

Page 191: ...ount value may be in excess of the refresh cycle For this reason clear RTCNT by writing H 00 before starting refresh control to assure a correct refresh interval When the RW1 bit in WCR1 is set to 1 and the read cycle is set to long pitch the number of wait states selected by the RLW1 and RLW0 bits in RCR will be inserted into the CBR refresh cycle regardless of the status of the WAIT signal Figur...

Page 192: ...esh mode all row addresses should be refreshed again This can be done using the BSC s CBR refresh function to set all row addresses for refresh in software To access a DRAM area while in self refresh mode first clear the RMODE bit to 0 and exit self refresh mode The chip can be kept in the self refresh state and shifted to standby mode by setting it to self refresh mode setting the standby bit SBY...

Page 193: ...d set the interrupt generation timing in RTCOR When the input clock is selected with the CKS2 CKS0 bits in RTCSR RTCNT starts incrementing as an 8 bit interval timer Its value is constantly compared with RTCOR and when a match occurs the CMF bit in RTCSR is set to 1 and a CMI interrupt is produced RTCNT is cleared to H 00 When the clock is selected with the CKS2 CKS0 bits RTCNT starts incrementing...

Page 194: ...When the A14 address bit is 0 the bus width is 8 bits and address output and data input output are performed on the AD7 AD0 pins When the A14 address bit is 1 the bus width is 16 bits and address output and data input output are performed on the AD15 AD0 pins In the address data multiplexed I O space access is controlled with the AH RD and WR signals Accesses in the address data multiplexed I O sp...

Page 195: ... whenever a low level is detected regardless of the WCR setting Figure 8 33 shows an example in which a WAIT signal causes one wait state to be inserted T1 CK A21 A0 CS AH Address AD15 AD0 Address Data output RD Read AD15 AD0 WRH WRL Write T2 Tw wait state T3 T4 WAIT Data input Figure 8 33 Wait State Timing For Address Data Multiplexed I O Space Access 8 6 3 Byte Access Control The byte access con...

Page 196: ...DPH pin input upper byte parity data is accurate for the AD15 AD8 pin input upper byte data or if the DPL pin input lower byte parity data is accurate for the AD7 AD0 pin input lower byte data If the check indicates that either the upper or lower byte parity is incorrect a parity error interrupt is produced PEI When outputting data to the space selected with the PCHK1 and PCHK0 bits the BSC output...

Page 197: ...ted at high speed When in warp mode an external write cycle or DMA single address mode transfer cycle continues for at least 2 states and there is an internal access only the external write cycle will be performed in the initial state The external write cycle and internal access cycle will be performed in parallel from the next state on without waiting for the end of the external write cycle Figur...

Page 198: ...rting module read External space address Write data External space address Write data Read data On chip supporting module address Figure 8 34 Warp Mode Timing Access to On Chip Supporting Module and External Write Cycle 8 9 Wait State Control The WCR1 WCR3 registers of the BSC can be set to control sampling of the WAIT signal when accessing various areas and the number of bus cycle states Table 8 ...

Page 199: ... 7 1 state fixed WAIT signal ignored CPU Write Cycle DMAC Dual Mode Memory Write Cycle WW1 of WCR1 Address Space WW1 of WCR1 0 WW1 of WCR1 1 External memory area 1 Setting prohibited 2 states wait state from WAIT signal External memory areas 3 5 7 2 states wait states from WAIT signal External memory Areas 0 2 6 long wait available 1 state long wait state wait states from WAIT signal DRAM space ar...

Page 200: ... A27 is 0 are always performed in 1 state regardless of WCR with no WAIT signal sampling If the bus timing specifications tWTS and tWTH are not observed when the WAIT signal is input in external space access this will simply mean that WAIT signal assertion and negation will not be detected but will not result in misoperation Note however that the inability to detect WAIT signal assertion may resul...

Page 201: ...sh request is generated while the bus is released to an external device BACK goes high and the bus can be acquired to perform refreshing upon receipt of a BREQ high response from the external device Input all bus requests from external devices to the BREQ pin The signal indicating that the bus has been released is output from the BACK pin Figure 8 35 illustrates the bus release procedure Bus relea...

Page 202: ...BACK goes high even if BREQ input is low Therefore drive BREQ high immediately to release the bus for this chip to hold DRAM data see figure 8 36 2 When BREQ changes from high to low and an internal refresh is requested at the timing of bus release by this chip BACK may remain high The bus is released to the external device since BREQ input is low This operation is based on the above specification...

Page 203: ...t asserted but remains high a momentary narrow pulse shaped spike may be output as shown below BACK BREQ Refresh demand Spike pulse width is approx 2 to 5 ns 2 Preventing spikes in the BACK signal The following measures should be taken to prevent spikes in the BACK signal a When BREQ is input to release the bus make sure that a conflict with a refresh operation does not occur Stop the refresh oper...

Page 204: ...sing BACK as a trigger signal When splitting the BACK signal into two signals and latching each of them using a flip flop or triggering the flip flop the flip flop may operate for one signal but not for the other To capture the BACK signal using a flip flop receive the BACK signal using a single flip flop then distribute the signal see figure below BACK D Q Q D Q Q BACK D Q Q Trigger OK Trigger NG...

Page 205: ...s of DRAM control signals RAS CAS and WR corresponding to RES latch timing Actual output levels are shown by solid lines not by dashed lines CK RES A0 A21 RAS CAS WR AD0 AD15 Row address RES latch timing Tp Tr Tc1 Tc2 Data output Manual reset Column address FFFF Figure 8 38 Long Pitch Mode Write 1 Row address RES latch timing Tp Tr Tc1 Tc2 Data output Manual reset CK RES A0 A21 RAS CAS WR AD0 AD15...

Page 206: ...ake one of the measures described below 1 When resetting manually use the watchdog timer WDT reset function 2 Even if the low width of RAS becomes as short as 1 5 tcyc as shown above use with a frequency that satisfies the DRAM standard tRAS 3 Even if the low width of RAS is 1 5 tcyc use an external circuit so that a RAS signal with a low width of 2 5 tcyc is input in the DRAM if the low width of ...

Page 207: ...but this is not a problem RAS CAS RD WE CK D Q Q RAS CAS DRAM WRH or WRL DWRH or DWRL 2 1 1 OE SuperH Micro computer Notes 1 To prevent signal racing 2 Negative edge latch Figure 8 42 Delayed Write Control Circuit 8 11 3 Maximum Number of States from BREQ Input to Bus Release The maximum number of states from BREQ input to bus release is Maximum number of states for which bus is not released appro...

Page 208: ...ple in the case of a longword read or write in 8 bit ordinary space one bus cycle consists of 4 memory accesses to 8 bit ordinary space as shown in figure 8 44 The bus is not released between these accesses Assuming one memory access to require 2 states the bus is not released for a period of 8 states 8 bits 8 bits Cycle during which bus is not released 8 bits 8 bits Figure 8 44 One Bus Cycle b TA...

Page 209: ...fore the break between bus cycles so that tBRQS is satisfied In the SH7032 and SH7034 the bus is released after the bus cycle in which BREQ is input if BREQ is input between bus cycles after the bus cycle starting next CK A21 to A0 BREQ BACK RD WR RAS CAS CSn tBRQS tBRQS tBZD tBZD tBACD2 tBACD1 Bus cycle Bus cycle Bus release Strobe pin high level output The bus is released after the bus cycle in ...

Page 210: ...accessed by a DACK signal selectable while the other is accessed by address One transfer unit of data is transferred in each bus cycle Device combinations for which transfer is possible External device with DACK and memory mapped external device including external memories External device with DACK and memory mapped external memory Dual address mode transfer channels 0 3 Both the transfer source a...

Page 211: ...e unit ITU Auto request the transfer request is generated automatically within the DMAC Selectable bus modes Cycle steal mode or burst mode Selectable channel priority levels Fixed round robin or external pin round robin modes CPU can be asked for interrupt when data transfer ends Maximum transfer rate 20 M words s 320 MB s For 5 V and 20 MHz Bus mode Burst mode Transmission size Word 9 1 2 Block ...

Page 212: ...wledge Bus controller Iteration control Register control Start up control Request priority control Bus interface DMAC module bus SARn DARn TCRn CHCRn DMAOR Internal bus DMAOR DMA operation register SARn DMA source address register DARn DMA destination address register TCRn DMA transfer count register CHCRn DMA channel control register DEIn DMA transfer end interrupt request to CPU n 0 3 Figure 9 1...

Page 213: ...quest input from external device to channel 0 DMA transfer request acknowledge DACK0 O DMA transfer request acknowledge output from channel 0 to external device 1 DMA transfer request DREQ1 I DMA transfer request input from external device to channel 1 DMA transfer request acknowledge DACK1 O DMA transfer request acknowledge output from channel 1 to external device ...

Page 214: ...2 SAR2 3 R W Undefined H 5FFFF60 16 32 DMA destination address register 2 DAR2 3 R W Undefined H 5FFFF64 16 32 DMA transfer count register 2 TCR2 3 R W Undefined H 5FFFF6A 16 32 DMA channel control register 2 CHCR2 R W 1 H 0000 H 5FFFF6E 8 16 32 3 DMA source address register 3 SAR3 3 R W Undefined H 5FFFF70 16 32 DMA destination address register 3 DAR3 3 R W Undefined H 5FFFF74 16 32 DMA transfer ...

Page 215: ...itial value R W R W R W R W R W R W R W R W R W Bit 23 22 21 0 Bit name Initial value R W R W R W R W R W 9 2 2 DMA Destination Address Registers 0 3 DAR0 DAR3 DMA destination address registers 0 3 DAR0 DAR3 are 32 bit read write registers that specify the destination address of a DMA transfer During a DMA transfer these registers indicate the next destination address in single address mode DAR is...

Page 216: ...W R W R W R W R W Bit 7 6 5 4 3 2 1 0 Bit name Initial value R W R W R W R W R W R W R W R W R W 9 2 4 DMA Channel Control Registers 0 3 CHCR0 CHCR3 DMA channel control registers 0 3 CHCR0 CHCR3 are 16 bit read write registers that control the DMA transfer mode They also indicate the DMA transfer status They are initialized to H 0000 by a reset and in standby mode Bit 15 14 13 12 11 10 9 8 Bit nam...

Page 217: ... 13 and 12 source address mode bits 1 0 SM1 and SM0 SM1 and SM0 select whether the DMA source address is incremented decremented or left fixed in the single address mode SM1 and SM0 are ignored when transfers are made from external devices with DACK to memory mapped external devices or external memory SM1 and SM0 are initialized to 00 by resets or in standby mode Bit 13 SM1 Bit 12 SM0 Description ...

Page 218: ...nsfer request 4 1 0 0 1 IMIA1 On chip ITU1 input capture compare match A interrupt transfer request 4 1 0 1 0 IMIA2 On chip ITU2 input capture compare match A interrupt transfer request 4 1 0 1 1 IMIA3 On chip ITU3 input capture compare match A interrupt transfer request 4 1 1 0 0 Auto request Transfer requests automatically generated within DMAC 4 1 1 0 1 ADI A D conversion end interrupt request ...

Page 219: ...Bit DS DS selects the DREQ input detection method used This bit is valid only in channels 0 and 1 The DS bit is initialized to 0 by a reset and in standby mode Bit 5 DS Description 0 DREQ detected by low level Initial value 1 DREQ detected by falling edge Bit 4 Transfer Bus Mode Bit TM TM selects the bus mode for DMA transfers The TM bit is initialized to 0 by a reset and in standby mode When the ...

Page 220: ...the TE bit read 1 from it and then write 0 When this flag is set setting the DE bit to 1 does not enable a DMA transfer The TE bit is initialized to 0 by a reset and in standby mode Bit 1 TE Description 0 DMA has not ended or was aborted Initial value To clear TE the CPU must read TE after it has been set to 1 then write a 0 in this bit 1 DMA has ended normally Bit 0 DMA Enable Bit DE DE enables o...

Page 221: ... only 0 to clear the flag Bits 15 10 Reserved These bits are always read as 0 The write value should always be 0 Bits 9 and 8 Priority Mode Bits 1 and 0 PR1 and PR0 PR1 and PR0 select the priority level between channels when there are simultaneous transfer requests for multiple channels Bit 9 PR1 Bit 8 PR0 Description 0 0 Fixed priority order Ch 0 Ch 3 Ch 2 Ch 1 Initial value 0 1 Fixed priority or...

Page 222: ...hannel cannot be enabled even if the DE bit in CHCR and the DME bit are set to 1 To clear the NMIF bit read 1 from it and then write 0 It is initialized to 0 by a reset and in standby mode Bit 1 NMIF Description 0 No NMI interrupt Initial value To clear the NMIF bit read 1 from it and then write 0 1 NMI has occurred Bit 0 DMA Master Enable Bit DME DME enables or disables DMA transfers on all chann...

Page 223: ...AC transfers data according to the following procedure 1 Checks to see if transfer is enabled DE 1 DME 1 TE 0 NMIF 0 AE 0 2 When a transfer request arrives and transfer is enabled the DMAC transfers one transfer unit of data For an auto request the transfer begins automatically when the DE bit and DME bit are set to 1 The TCR value will be decremented by 1 The actual transfer flows vary by address...

Page 224: ... TCR CHCR DMAOR Transfer 1 transfer unit TCR 1 TCR SAR and DAR updated DEI interrupt request when IE 1 No Yes No Yes No Yes Yes No Yes No 3 2 Start Notes 1 In auto request mode transfer begins when NMIF AE and TE are all 0 and the DE and DME bits are set to 1 2 DREQ level detection in burst mode external request or cycle steal mode 3 DREQ edge detection in burst mode external request or auto reque...

Page 225: ...a transfer is performed upon a request at the DREQ input Choose to detect DREQ by either the falling edge or low level of the signal input with the DS bit in CHCR0 CHCR3 DS 0 specifies level detection DS 1 specifies edge detection The source of the transfer request does not have to be the data transfer source or destination Table 9 3 Selecting External Request Modes with the RS Bits RS3 RS2 RS1 RS...

Page 226: ...t Any TDR0 Cycle steal 0 1 1 0 SCI1 receiver RXI1 SCI1 receive data full interrupt transfer request RDR1 Any Cycle steal 0 1 1 1 SCI1 transmitter TXI1 SCI1 transmit data empty interrupt transfer request Any TDR1 Cycle steal 1 0 0 0 ITU0 IMIA0 ITU0 input capture A compare match A Any Any Burst Cycle steal 1 0 0 1 ITU1 IMIA1 ITU1 input capture A compare match A Any Any Burst Cycle steal 1 0 1 0 ITU2...

Page 227: ...used it will be cleared at the last transfer 9 3 3 Channel Priority When the DMAC receives simultaneous transfer requests on two or more channels it selects a channel according to a predetermined priority order The three modes fixed mode round robin mode and external pin round robin mode are selected by priority bits PR1 and PR0 in the DMA operation register Fixed Mode In this mode the priority le...

Page 228: ...der after transfer Channel 3 becomes bottom priority The priority of channel 0 which was higher than channel 3 is also shifted Channel 0 becomes bottom priority Channel 2 becomes bottom priority The priority of channels 0 and 3 which were higher than channel 2 are also shifted If immediately thereafter there is a transfer request for channel 3 only channel 3 becomes bottom priority and the priorit...

Page 229: ...ransfer 6 When the channel 3 transfer ends channel 3 becomes the lowest priority 7 The channel 1 transfer begins 8 When the channel 1 transfer ends channels 1 and 2 shift downward in priority so that channel 1 becomes the lowest priority 1 1 3 1 None 1 Channels 0 and 1 3 Channel 3 2 Channel 0 transfer starts Priority order changes 0 3 2 1 3 2 1 0 2 1 0 3 0 3 2 1 Transfer request Waiting channel s ...

Page 230: ...s how the priority order changes when channel 0 and channel 1 transfers are requested simultaneously and a channel 0 transfer is requested again after both channels finish their transfers The DMAC operates as follows 1 Transfer requests are generated simultaneously for channels 1 and 0 2 Channel 1 has a higher priority so the channel 1 transfer begins first channel 0 waits for transfer 3 When the ...

Page 231: ...sfer starts 4 Channel 0 transfer starts 8 Channel 0 transfer ends Priority order changes 3 2 1 0 3 2 0 1 3 2 1 0 3 2 1 0 Transfer request Waiting channel s DMAC operation Channel priority Priority order changes Priority order does not change Waiting for transfer request Figure 9 5 Example of Changes in Priority in External Pin Round Robin Mode ...

Page 232: ...ry mapped external device Single Dual Dual Dual Dual On chip memory Not available Dual Dual Dual Dual On chip supporting module Not available Dual Dual Dual Dual Single Single address mode Dual Dual address mode Address Modes Single Address Mode In single address mode both the transfer source and destination are external one selectable is accessed by a DACK signal while the other is accessed by an...

Page 233: ...Two types of transfers are possible in single address mode 1 transfers between external devices with DACK and memory mapped external devices and 2 transfers between external devices with DACK and external memory The only transfer request for either of these is the external request DREQ Figure 9 7 shows the DMA transfer timing for single address mode The DACK output when a transfer occurs from an e...

Page 234: ...memory space to external device with DACK Figure 9 7 Examples of DMA Transfer Timing in Single Address Mode Dual Address Mode In dual address mode both the transfer source and destination are accessed selectable by an address The source and destination can be located externally or internally The source is accessed in the read cycle and the destination in the write cycle so the transfer is performe...

Page 235: ...dule excluding the DMAC 6 Between memory mapped external device and on chip memory 7 Between memory mapped external device and an on chip supporting module excluding the DMAC 8 On chip memory to on chip memory 9 Between on chip memory and an on chip supporting module excluding the DMAC 10 Between on chip supporting modules excluding the DMAC Transfer requests can be auto requests external requests...

Page 236: ...curs the bus is obtained from the other bus master and a transfer is performed for one transfer unit When that transfer ends the bus is passed to the other bus master This is repeated until the transfer end conditions are satisfied Cycle steal mode can be used with all categories of transfer destination transfer source and transfer request Figure 9 10 shows an example of DMA transfer timing in cyc...

Page 237: ...ve not been satisfied Burst mode cannot be used when the serial communication interface SCI is the transfer request source Figure 9 11 shows an example of DMA transfer timing in burst mode The transfer conditions shown in the figure are Single address mode DREQ level detection CPU CPU CPU DMAC DMAC DMAC DMAC DMAC DREQ Bus cycle DMAC CPU Figure 9 11 Transfer Example in Burst Mode Single Address Mod...

Page 238: ...p supporting module All 2 B C 3 8 16 4 0 3 5 On chip memory and on chip memory All 1 B C 8 16 0 3 5 On chip memory and on chip supporting module All 2 B C 3 8 16 4 0 3 5 On chip supporting module and on chip supporting module All 2 B C 3 8 16 4 0 3 5 B Burst C Cycle steal Notes 1 External requests auto requests and on chip supporting module requests are all available For on chip supporting module ...

Page 239: ...steal mode DMAC ch1 Burst mode CPU CPU DMAC ch1 Burst mode Priority order is ch0 ch3 ch2 ch1 ch1 is in burst mode and ch2 is in cycle steal mode Figure 9 12 Bus Handling when Multiple Channels are Operating 9 3 5 Number of Bus Cycle States and DREQ Pin Sample Timing Number of States in Bus Cycle The number of states in the bus cycle when the DMAC is the bus master is controlled by the bus state co...

Page 240: ...diately prior to the rising edge of the clock pulse CK of the third state after the bus cycle previous to the bus cycle in which the DACK signal is output Figures 9 13 to 9 22 show the sampling timing of the DREQ pin in cycle steal mode for each bus cycle When no DREQ input is detected at the sampling after the aforementioned DREQ detection the next sampling occurs in the next state in which a DAC...

Page 241: ...g the DMAC read cycle Figure 9 14 DREQ Sampling Timing in Cycle Steal Mode Output with DREQ Level Detection and DACK Active Low Dual Address Mode Bus Cycle 1 State CK DREQ DACK Bus cycle CPU CPU CPU DMAC CPU CPU CPU CPU Figure 9 15 DREQ Sampling Timing in Cycle Steal Mode Output with DREQ Level Detection and DACK Active Low Single Address Mode Bus Cycle 2 States ...

Page 242: ...ection and DACK Active Low Dual Address Mode Bus Cycle 2 States CK DREQ DACK Bus cycle T2 Tw T1 DMAC T2 Tw T1 CPU CPU CPU DMAC CPU CPU Note When DREQ is negated at the third state of the DMAC cycle the next DMA transfer will be executed because the sampling is performed at the second state of the DMAC cycle Figure 9 17 DREQ Sampling Timing in Cycle Steal Mode Output with DREQ Level Detection and D...

Page 243: ... Cycle 2 States 1 Wait State CK DREQ DACK Bus cycle Tc Tr Tp Tc CPU CPU CPU DMAC CPU CPU Tc Tr Tp Tc DMAC Note When DREQ is negated at the fourth state of the DMAC cycle the next DMA transfer will be executed because the sampling is performed at the second state of the DMAC cycle Figure 9 19 DREQ Sampling Timing in Cycle Steal Mode Output with DREQ Level Detection and DACK Active Low Single Addres...

Page 244: ...ycle Steal Mode Output with DREQ Level Detection and DACK Active Low Dual Address Mode Bus Cycle DRAM Bus Cycle Long Pitch Normal Mode CK DREQ DACK Bus cycle T3 T2 T1 T4 CPU CPU CPU DMAC CPU CPU T3 T2 T1 T4 DMAC Note When DREQ is negated at the fourth state of the DMAC cycle the next DMA transfer will be executed because the sampling is performed at the second state of the DMAC cycle Figure 9 21 D...

Page 245: ...Q input is being detected by edge once the falling edge of the DREQ signal is detected the DMA transfer continues until the transfer end conditions are satisfied regardless of the status of the DREQ pin No sampling happens during this time After the transfer ends sampling occurs every state until the TE bit of CHCR is cleared When DREQ input is being detected by level once the DREQ input is detect...

Page 246: ...in Burst Mode Single Address DREQ Level Detection DACK Active Low 1 Bus Cycle 2 States CK DREQ DACK Bus cycle CPU CPU DMAC R DMAC W DMAC R CPU DMAC W Figure 9 24 DREQ Pin Sampling Timing in Burst Mode Dual Address DREQ Level Detection DACK Active Low DACK Output in Read Cycle 1 Bus Cycle 2 States ...

Page 247: ...or flag bit is set to 1 in DMAOR or 2 when the DME bit in DMAOR is cleared to 0 Transfers ending when the NMIF or AE bit is set to 1 in DMAOR When an NMI interrupt or DMAC address error occurs the NMIF or AE bit is set to 1 in DMAOR and all channels stop their transfers SAR DAR and TCR are all updated by the transfer immediately preceding the halt The TE bit is not set To resume transfer after NMI...

Page 248: ... Transfer Conditions and Register Settings for Transfer Between On Chip RAM and Memory Mapped External Device Transfer Conditions Register Setting Transfer source on chip RAM SAR3 H FFFFE00 Transfer destination memory mapped external device DAR3 Destination address Number of transfers 8 TCR3 H 0008 Transfer destination address fixed CHCR3 H 1805 Transfer source address incremented Transfer request...

Page 249: ... SCI and External Memory Transfer Conditions Register Setting Transfer source RDR0 of on chip SCI0 SAR3 H FFFFEC5 Transfer destination external memory DAR3 Destination address Number of transfers 64 TCR3 H 0040 Transfer destination address incremented CHCR3 H 4405 Transfer source address fixed Transfer request source transfer request signal SCI0 RXI0 Bus mode cycle steal Transfer unit byte DEI int...

Page 250: ... Chip A D Converter and External Memory Transfer Conditions Register Setting Transfer source ADDRA of on chip A D converter SAR3 H FFFFEE0 ADDRAH register address Transfer destination external memory DAR3 Destination address Number of transfers 16 TCR3 H 0010 Transfer destination address incremented CHCR3 H 4D0D Transfer source address fixed Transfer request source transfer request signal A D conv...

Page 251: ...ng is not executed When the DMAC completes the transfer and the CPU acquires the bus the CPU executes interrupt handling if the interrupt requested during DMAC transfer is not cleared Note Clear conditions for an interrupt request When an interrupt is requested from an on chip supporting module and the interrupt source flag is cleared When an interrupt is requested by IRQ edge detection and the CP...

Page 252: ...ot use the SLEEP instruction but use the transfer end flag bit TE in the channel DMA control register and a polling software loop 7 Sampling of DREQ If DREQ is set to level detection in DMA cycle steal mode sampling of DREQ may take place before DACK is output Note that some system configurations involve unnecessary DMA transfers Operation As shown in Figure 9 25 sampling of DREQ is carried out im...

Page 253: ...tput at DACK read in dual address mode and DMA transfer using DRAM as the source Remedy To prevent unnecessary DMA transfers configure the system so that DREQ is edge detected and the edge corresponding to the next transfer request occurs after DACK output 8 When the following operations are performed in the order shown when the pin to which DREQ input is assigned is designated as a general input ...

Page 254: ...mpare match or input capture Synchronizing mode Two or more timer counters TCNT can be written to simultaneously Two or more timer counters can be simultaneously cleared by a compare match or input capture Counter synchronization functions enable synchronized input output PWM mode PWM output can be provided with any duty cycle When combined with the counter synchronizing function enables up to fiv...

Page 255: ...l of 15 sources Can activate DMAC The compare match input capture interrupts of channels 0 3 can start the DMAC one for each of four channels Output trigger can be generated for the programmable timing pattern controller TPC The compare match input capture signals of channel 0 3 can be used as output triggers for the TPC Table 10 1 summarizes the ITU functions ...

Page 256: ...es No Yes Yes Input capture function Yes Yes Yes Yes Yes Synchronization Yes Yes Yes Yes Yes PWM mode Yes Yes Yes Yes Yes Reset synchronized PWM mode No No No Yes Yes Complementary PWM mode No No No Yes Yes Phase counting mode No No Yes No No Buffer operation No No No Yes Yes DMAC activation GRA0 com pare match or input capture GRA1 com pare match or input capture GRA2 com pare match or input capt...

Page 257: ...dule data bus Bus interface Internal data bus Clock selection Counter control and pulse I O control unit TCLKA TCLKD φ φ 2 φ 4 φ 8 TOCXA4 TOCXB4 TIOCA0 TIOCA4 TIOCB0 TIOCB4 IMIA0 IMIA4 IMIB0 IMIB4 OVI0 OVI4 Control logic TOCR Timer output control register 8 bits TSTR Timer start register 8 bits TSNC Timer synchronization register 8 bits TMDR Timer mode register 8 bits TFCR Timer function control r...

Page 258: ...Bn TCRn TIORn TIERn TSRn Module data bus TIOCAn TIOCBn IMIAn IMIBn OVIn TCNTn Timer counter n 16 bits GRAn GRBn General registers An Bn input capture output compare dual use 16 bits 2 TCRn Timer control register n 8 bits TIORn Timer I O control register n 8 bits TIERn Timer interrupt enable register n 8 bits TSRn Timer status register n 8 bits n 0 or 1 Figure 10 2 Block Diagram of Channels 0 and 1...

Page 259: ...dule data bus TIOCA2 TIOCB2 IMIA2 IMIB2 OVI2 TCNT2 GRA2 GRB2 TCR2 TIOR2 TIER2 TSR2 TCNT2 Timer counter 2 16 bits GRA2 GRB2 General registers A2 B2 input capture output compare dual use 16 bits 2 TCR2 Timer control register 2 8 bits TIOR2 Timer I O control register 2 8 bits TIER2 Timer interrupt enable register 2 8 bits TSR2 Timer status register 2 8 bits Figure 10 3 Block Diagram of Channel 2 ...

Page 260: ...VI3 TCNT3 BRA3 GRA3 TCR3 TIOR3 TIER3 TSR3 BRB3 GRB3 TCNT3 Timer counter 3 16 bits GRA3 GRB3 General registers A3 B3 input capture output compare dual use 16 bits 2 BRA3 BRB3 Buffer registers A3 B3 input capture output compare dual use 16 bits 2 TCR3 Timer control register 3 8 bits TIOR3 Timer I O control register 3 8 bits TIER3 Timer interrupt enable register 3 8 bits TSR3 Timer status register 3 ...

Page 261: ...Timer counter 4 16 bits GRA4 GRB4 General registers A4 B4 input capture output compare dual use 16 bits 2 BRA4 BRB4 Buffer registers A4 B4 input capture output compare dual use 16 bits 2 TCR4 Timer control register 4 8 bits TIOR4 Timer I O control register 4 8 bits TIER4 Timer interrupt enable register 4 8 bits TSR4 Timer status register 4 8 bits Figure 10 5 Block Diagram of Channel 4 ...

Page 262: ...WM output pin in PWM mode Input capture output compare B1 TIOCB1 I O GRB1 output compare GRB1 input capture 2 Input capture output compare A2 TIOCA2 I O GRA2 output compare GRA2 input capture PWM output pin in PWM mode Input capture output compare B2 TIOCB2 I O GRB2 output compare GRB2 input capture 3 Input capture output compare A3 TIOCA3 I O GRA3 output compare GRA3 input capture PWM output pin ...

Page 263: ...08 H 5FFFF05 8 Timer interrupt enable register 0 TIER0 R W H F8 H 78 H 5FFFF06 8 Timer status register 0 TSR0 R W 2 H F8 H 78 H 5FFFF07 8 Timer counter 0 TCNT0 R W H 00 H 5FFFF08 8 16 32 H 5FFFF09 8 16 32 General register A0 GRA0 R W H FF H 5FFFF0A 8 16 32 H 5FFFF0B 8 16 32 General register B0 GRB0 R W H FF H 5FFFF0C 8 16 H 5FFFF0D 8 16 1 Timer control register 1 TCR1 R W H 80 H 00 H 5FFFF0E 8 Tim...

Page 264: ...W H 80 H 00 H 5FFFF22 8 Timer I O control register 3 TIOR3 R W H 88 H 08 H 5FFFF23 8 Timer interrupt enable register 3 TIER3 R W H F8 H 78 H 5FFFF24 8 Timer status register 3 TSR3 R W 2 H F8 H 78 H 5FFFF25 8 Timer counter 3 TCNT3 R W H 00 H 5FFFF26 8 16 H 5FFFF27 8 16 General register A3 GRA3 R W H FF H 5FFFF28 8 16 32 H 5FFFF29 8 16 32 General register B3 GRB3 R W H FF H 5FFFF2A 8 16 32 H 5FFFF2B...

Page 265: ...H FF H 5FFFF3E 8 16 32 H 5FFFF3F 8 16 32 Notes 1 Only the values of bits A27 A24 and A8 A0 are valid bits A23 A9 are ignored For details on the register addresses see section 8 3 5 Area Descriptions 2 Only 0 can be written to clear flags 10 2 ITU Register Descriptions 10 2 1 Timer Start Register TSTR The timer start register TSTR is an eight bit read write register that starts and stops the timer ...

Page 266: ...counting Bit 3 Count Start 3 STR3 STR3 starts and stops TCNT3 Bit 3 STR3 Description 0 TCNT3 is halted Initial value 1 TCNT3 is counting Bit 2 Count Start 2 STR2 STR2 starts and stops TCNT2 Bit 2 STR2 Description 0 TCNT2 is halted Initial value 1 TCNT2 is counting Bit 1 Count Start 1 STR1 STR1 starts and stops TCNT1 Bit 1 STR1 Description 0 TCNT1 is halted Initial value 1 TCNT1 is counting Bit 0 C...

Page 267: ...e for channel 4 Bit 4 SYNC4 Description 0 The timer counter for channel 4 TCNT4 operates independently Preset clear of TCNT4 is independent of other channels Initial value 1 Channel 4 operates synchronously Synchronized preset clear of TNCT4 enabled Bit 3 Timer Synchro 3 SYNC3 SYNC3 selects synchronizing mode for channel 3 Bit 3 SYNC3 Description 0 The timer counter for channel 3 TCNT3 operates in...

Page 268: ... operates synchronously Synchronized preset clear of TNCT0 enabled 10 2 3 Timer Mode Register TMDR The timer mode register TMDR is an eight bit read write register that selects PWM mode for channels 0 4 sets phase counting mode for channel 2 and sets the conditions for the overflow flag OVF TMDR is initialized to H 80 or H 00 by a reset and in standby mode Bit 7 6 5 4 3 2 1 0 Bit name MDF FDIR PWM...

Page 269: ... TIER2 and timer status register 2 TSR2 compare match input capture functions and interrupts however are valid even in phase counting mode Bit 5 Flag Direction FDIR FDIR selects the setting condition for the overflow flag OVF in timer status register 2 TSR2 This bit is valid no matter which mode channel 2 is operating in Bit 5 FDIR Description 0 OVF of TSR2 is set to 1 when TCNT2 overflows or unde...

Page 270: ...put on a compare match of general register A2 GRA2 0 is output on a compare match of general register B2 GRB2 Bit 2 PWM2 Description 0 Channel 2 operates normally Initial value 1 Channel 2 operates in PWM mode Bit 1 PWM Mode 1 PWM1 PWM1 selects the PWM mode for channel 1 When the PWM1 bit is set to 1 and PWM mode is entered the TIOCA1 pin becomes a PWM output pin 1 is output on a compare match of ...

Page 271: ...ary PWM mode or reset synchronized mode for channels 3 and 4 Set the complementary PWM reset synchronized PWM mode while the timer counter TCNT being used is off When these bits are used to set complementary PWM reset synchronized PWM mode they take priority over the PWM4 and PWM3 bits in TMDR While the complementary PWM reset synchronized PWM mode settings and the SYNC4 and SYNC3 bit settings of ...

Page 272: ... GRA4 operates normally in channel 4 Initial value 1 GRA4 and BRA4 operate in buffer mode in channel 4 Bit 1 Buffer Mode B3 BFB3 BFB3 selects buffer mode for GRB3 and BRB3 in channel 3 Bit 1 BFB3 Description 0 GRB3 operates normally in channel 3 Initial value 1 GRB3 and BRB3 operate in buffer mode in channel 3 Bit 0 Buffer Mode A3 BFA3 BFA3 selects buffer mode for GRA3 and BRA3 in channel 3 Bit 0 ...

Page 273: ...W R W Note Undefined Bits 7 2 Reserved Bit 7 is read as undefined Bits 6 2 are always read as 1 The write value to bit 7 should be 0 or 1 The write value to bits 6 2 should always be 1 Bit 1 Output Level Select 4 OLS4 OLS4 selects the output level for complementary PWM mode or reset synchronized PWM mode Bit 1 OLS4 Description 0 TIOCA3 TIOCA4 and TIOCB4 are inverted and output 1 TIOCA3 TIOCA4 and ...

Page 274: ...nction When TCNT overflows changes from H FFFF to H 0000 the overflow flag OVF in the timer status register TSR is set to 1 The OVF of the corresponding channel TSR is also set to 1 when TCNT underflows changes from H 0000 to H FFFF TCNT is connected to the CPU by a 16 bit bus so it can be written or read by either word access or byte access TCNT is initialized to H 0000 by a reset and in standby ...

Page 275: ...FA IMFB bit in the corresponding TSR is set to 1 at the same time The valid edge or edges of the input capture signal are selected in TIOR The TIOR setting is ignored when set for PWM mode complementary PWM mode or reset synchronized PWM mode General registers are connected to the CPU by a 16 bit bus so general registers can be written or read by either word access or byte access General registers...

Page 276: ...H FFFF by a reset and in standby mode Table 10 6 Buffer Registers A and B BRA BRB Channel Abbreviation Function 3 BRA3 BRB3 When used for buffer operation 4 BRA4 BRB4 When the corresponding GRA and GRB are output compare registers the buffer registers function as output compare buffer registers that can automatically transfer the BRA and BRB values to GRA and GRB upon a compare match When the corr...

Page 277: ... mode Table 10 7 Timer Control Register TCR Channel Abbrevi ation Function 0 TCR0 1 TCR1 2 TCR2 3 TCR3 4 TCR4 Bit 7 6 5 4 3 2 1 0 Bit name CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W Note Undefined Bit 7 Reserved Bit 7 is read as undefined The write value should be 0 or 1 TCR controls the TCNTs The TCRs have the same functions on all channe...

Page 278: ... the synchronization Bits 4 and 3 External Clock Edge 1 0 CKEG1 and CKEG0 CKEG1 and CKEG0 select external clock input edge When channel 2 is set for phase counting mode settings of the CKEG1 and CKEG0 bits in TCR are ignored and the phase counting mode operation takes priority Bit 4 CKEG1 Bit 3 CKEG0 Description 0 0 Count rising edges Initial value 1 Count falling edges 1 Count both rising and fal...

Page 279: ...OCB pins If output compare is selected TIOR also selects the output settings If input capture is selected TIOR also selects the input capture edge TIOR is initialized to H 88 or H 08 by a reset and in standby mode Each ITU channel has one TIOR Table 10 8 Timer I O Control Register TIOR Channel Abbrevi ation Function 0 TIOR0 1 TIOR1 2 TIOR2 3 TIOR3 4 TIOR4 Bit 7 6 5 4 3 2 1 0 Bit name IOB2 IOB1 IOB...

Page 280: ...it 3 Reserved Bit 3 always is read as 1 The write value should always be 1 Bits 2 0 I O Control A2 A0 IOA2 IOA0 IOA2 IOA0 select the GRB function Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 GRA Function 0 0 0 Compare match with pin output disabled Initial value 1 0 output at GRA compare match 1 1 0 1 output at GRA compare match 1 1 Output toggles at GRA compare match 1 output for channel 2 only 1 2 1 0 0 GRA...

Page 281: ...it 7 6 5 4 3 2 1 0 Bit name OVF IMFB IMFA Initial value 1 1 1 1 1 0 0 0 R W R W 2 R W 2 R W 2 Notes 1 Undefined 2 Only 0 can be written to clear the flag Bits 7 3 Reserved Bit 7 is read as undefined Bits 6 3 are always read as 1 The write value to bit 7 should be 0 or 1 The write value to bits 6 3 should always be 1 Bit 2 Overflow Flag OVF OVF indicates that a TCNT overflow underflow has occurred ...

Page 282: ...Description 0 Clearing condition Read IMFA when IMFA 1 then write 0 in IMFA Initial value DMAC is activated by an IMIA interrupt only channels 0 3 1 Setting conditions GRA is functioning as an output compare register and TCNT GRA GRA is functioning as an input capture register and the value of TCNT is transferred to GRA by an input capture signal 10 2 12 Timer Interrupt Enable Register TIER The ti...

Page 283: ...o 1 OVIE enables or disables interrupt requests from OVF Bit 2 OVIE Description 0 Disables interrupt requests by OVF Initial value 1 Enables interrupt requests from OVF Bit 1 Input Capture Compare Match Interrupt Enable B IMIEB When the IMFB bit in TSR is set to 1 IMIEB enables or disables interrupt requests by IMFB Bit 1 IMIEB Description 0 Disables interrupt requests by IMFB IMIB Initial value 1...

Page 284: ...ons performed on TCNT in word units are shown in figures 10 6 and 10 7 Byte unit read and write operations on TCNTH and TCNTL are shown in figures 10 8 to 10 11 TCNTH TCNTL H L Bus interface H L CPU Internal data bus Module data bus Figure 10 6 TCNT Access CPU to TCNT Word TCNTH TCNTL H L Bus interface H L CPU Internal data bus Module data bus Figure 10 7 TCNT Access TCNT to CPU Word TCNTH TCNTL H...

Page 285: ...re 10 9 TCNT Access CPU to TCNT Lower Byte TCNTH TCNTL H L Bus interface H L CPU Internal data bus Module data bus Figure 10 10 TCNT Access TCNT to CPU Upper Byte TCNTH TCNTL H L Bus interface H L CPU Internal data bus Module data bus Figure 10 11 TCNT Access TCNT to CPU Lower Byte ...

Page 286: ... the CPU by an 8 bit data bus Figures 10 12 and 10 13 illustrate reading and writing in byte units with the timer control register TCR These registers must be accessed by byte access TCR Bus interface Internal data bus Module data bus CPU Figure 10 12 TCR Access CPU to TCR TCR Bus interface Internal data bus Module data bus CPU Figure 10 13 TCR Access TCR to CPU ...

Page 287: ...d PWM Mode Three pairs of positive and negative PWM waveforms can be obtained using channels 3 and 4 the three phases of the PWM waveform share a transition point on one side When set for reset synchronized PWM mode GRA3 GRB3 GRA4 and GRB4 automatically become output compare registers The TIOCA3 TIOCB3 TIOCA4 TOCXA4 TIOCB4 and TOCXB4 pins also become PWM output pins and TCNT3 becomes an up counter...

Page 288: ...imer counter TCNT starts counting There are two counting modes a free running mode and a periodic mode Procedure for selecting counting mode figure 10 14 1 Set bits TPSC2 TPSC0 in TCR to select the counter clock source If an external clock source is selected set bits CKEG1 and CKEG0 in TCR to select the desired edge of the external clock signal 2 To operate as a periodic counter set CCLR1 and CCLR...

Page 289: ... enable register TIER is set to 1 an interrupt request will be sent to the CPU After TCNT overflows counting continues from H 0000 Figure 10 15 shows an example of free running counting Periodic counter operation is obtained for a given channel s TCNT by selecting compare match as a TCNT clear source Set GRA or GRB for period setting to output compare register and select counter clear upon compare...

Page 290: ...escaling the system clock Figure 10 17 shows the timing External clock source The external clock input pin TCLKA TCLKD source is selected by bits TPSC2 TPSC0 in TCR and its valid edges are selected with the CKEG1 and CKEG0 bits in TCR The rising edge falling edge or both edges can be selected The pulse width of the external clock signal must be at least 1 5 system clocks when a single edge is sele...

Page 291: ...tput from the corresponding TIOCA and TIOCB pins upon compare matches A and B can be in three modes 0 level output 1 level output or toggle Toggle output cannot be selected for channel 2 Procedure for selecting the waveform output mode figure 10 19 1 Set TIOR to select 0 output 1 output or toggle output for compare match output The compare match output pin will output 0 until the first compare mat...

Page 292: ...0 is output upon compare match A and 1 is output upon compare match B When the pin level matches the set level the pin level does not change Figure 10 21 shows an example of toggle output In the figure TCNT operates as a periodic counter cleared by GRB compare match with toggle output at both compare match A and compare match B H FFFF TIOCB TCNT value Time GRB GRA TIOCA Does not change Does not ch...

Page 293: ...CNT changes from the matching value to the next value When a compare match signal is generated the output value set in TIOR is output to the output compare pin TIOCA TIOCB Accordingly when TCNT matches a general register the compare match signal is not generated until the next counter clock pulse Figure 10 22 shows the output timing of the compare match signal N N N 1 CK TCNT input clock TCNT GR C...

Page 294: ...t capture function Procedure for selecting input capture mode figure 10 23 1 Set TIOR to select the input capture function of GR and select the rising edge falling edge or both edges as the input edge of the input capture signal Put the corresponding port into input capture mode using the pin function controller before setting TIOR 2 Set the STR bit in TSTR to 1 to start the TCNT count Input selec...

Page 295: ...TIOCB and both edges of TIOCA are selected as input capture edges In the example TCNT is set to clear at GRB input capture Counter cleared by TIOCB input falling edge TCNT value H 0180 H 0160 H 0005 H 0000 TIOCB TIOCA GRA GRB H 0005 H 0160 H 0180 Time Figure 10 24 Input Capture Operation ...

Page 296: ...IOR Figure 10 25 shows the timing when the rising edge is selected The pulse width of the input capture signal must be at least 1 5 system clocks for single edge capture and 2 5 system clocks for capture of both edges N CK Input capture input TCNT Input capture signal GRA GRB N Figure 10 25 Input Capture Signal Timing ...

Page 297: ...g mode 2 When a value is written in TCNT in any of the synchronized channels the same value is simultaneously written in TCNT in the other channels 3 Set the counter to clear with compare match input capture using bits CCLR1 and CCLR0 in TCR 4 Set the counter clear source to synchronized clear using the CCLR1 and CCLR0 bits 5 Set the STR bits in TSTR to 1 to start the TCNT count Select counter cle...

Page 298: ... are set for counter clears by synchronizing clears Accordingly their timers are sync preset then sync cleared by a GRB0 compare match and then a three phase PWM waveform is output from the TIOCA0 TIOCA1 and TIOCA2 pins See section 10 4 4 PWM Mode for details on PWM mode TCNT0 TCNT2 values Time TIOCA0 Synchronized clear on GRB0 compare match GRB0 GRB1 GRA0 GRB2 GRA1 GRA2 TIOCA1 TIOCA2 Figure 10 27...

Page 299: ... 0 Output 0 TIOCA0 GRA0 GRB0 1 TIOCA1 GRA1 GRB1 2 TIOCA2 GRA2 GRB2 3 TIOCA3 GRA3 GRB3 4 TIOCA4 GRA4 GRB4 Procedure for Selecting PWM Mode Figure 10 28 1 Set bits TPSC2 TPSC0 in TCR to select the counter clock source If an external clock source is selected set bits CKEG1 and CKEG0 in TCR to select the desired edge of the external clock signal 2 Set CCLR1 and CCLR0 in TCR to select the counter clear...

Page 300: ... 1 when TCNT matches GRA and 0 when TCNT matches GRB TCNT can be cleared by compare match with either GRA or GRB This can be used in both free running and synchronized operation Figure 10 30 shows examples of PWM waveforms output with 0 and 100 duty cycles A 0 duty waveform can be obtained by setting the counter clear source to GRB and then setting GRA to a larger value than GRB A 100 duty wavefor...

Page 301: ...eared by GRA compare match TCNT value GRA GRB TIOCA Time Counter cleared by GRB compare match TCNT value GRB GRA TIOCA Time a Counter cleared by GRA b Counter cleared by GRB Figure 10 29 PWM Mode Operation Example 1 ...

Page 302: ...ompare match B TCNT value GRB TIOCA Time GRA write GRA write a 0 duty GRA Counter cleared on compare match A TCNT value GRA GRB TIOCA Time GRB write GRB write b 100 duty H 0000 H 0000 Figure 10 30 PWM Mode Operation Example 2 ...

Page 303: ...ttings for Reset Synchronized PWM Mode Register Setting TCNT3 Initial setting of H 0000 TCNT4 Not used functions independently GRA3 Sets count cycle for TCNT3 GRB3 Sets the turning point for PWM waveform output by the TIOCA3 and TIOCB3 pins GRA4 Sets the turning point for PWM waveform output by the TIOCA4 and TOCXA4 pins GRB4 Sets the turning point for PWM waveform output by the TIOCB4 and TOCXB4 ...

Page 304: ...mpare match range of TCNT3 X GRA3 X set value 7 Set the STR3 bit in TSTR to 1 to start the TCNT3 count 1 2 3 4 5 6 Stop counting Select counter clock Start counting Select counter clear source Reset synchronized PWM mode Select reset synchronized PWM mode Set TCNT Set general registers 7 Reset synchronized PWM mode Figure 10 31 Procedure for Selecting Reset Synchronized PWM Mode ...

Page 305: ...olated from GRA4 and GRB4 The PWM waveform outputs toggle at each compare match GRB3 GRA3 and GRB4 with TCNT3 and when the counter is cleared See section 10 4 8 Buffer Mode for details on simultaneously setting reset synchronized PWM mode and buffer operation GRA3 GRB3 GRB4 GRA4 TIOCA3 TIOCB3 TIOCA4 TOCXA4 TIOCB4 TOCXB4 Counter cleared at GRA3 compare match Time TCNT value Figure 10 32 Reset Synch...

Page 306: ... Settings for Complementary PWM Mode Register Setting TCNT3 Initial setting of non overlap cycle difference with TCNT4 TCNT4 Initial setting of H 0000 GRA3 Sets upper limit of TCNT3 1 GRB3 Sets the turning point for PWM waveform output by the TIOCA3 and TIOCB3 pins GRA4 Sets the turning point for PWM waveform output by the TIOCA4 and TOCXA4 pins GRB4 Sets the turning point for PWM waveform output ...

Page 307: ...tting of GRB3 GRA4 and GRB4 T initial setting of TCNT3 Note GRA3 cycle count 2 count of non overlaps 2cyc upper limit of TCNT3 1 6 Set the STR3 and STR4 bits in TSTR to 1 to start the TCNT3 and TCNT4 counts 1 2 3 4 5 6 Set general registers Start counting Complementary PWM mode Stop counting Select counter clock Set TCNT Complementary PWM mode Select complementary PWM mode Note To re establish com...

Page 308: ...xamples of PWM waveforms with 0 and 100 duty cycles in one phase in complementary PWM mode In this example the pin output changes upon GRB3 compare match so duty cycles of 0 and 100 can be obtained by setting GRB3 to a value larger than GRA3 Combining buffer operation with the above operation makes it easy to change the duty while operating See section 10 4 8 Buffer Mode for details Down counting ...

Page 309: ...eration Example 2 At the point where the up count down count changes in complementary PWM mode TCNT3 and TCNT4 will overshoot and undershoot respectively When this occurs the setting conditions for the IMFA bit of channel 3 and the overflow flag OVF of channel 4 are different from usual Transfer conditions for the buffer also differ The timing is as shown in figures 10 36 and 10 37 ...

Page 310: ...TCNT4 H 0001 H 0000 H FFFF H 0000 Underflow Flag not set Set to 1 Buffer transfer performed Buffer transfer not performed OVF Overflow Figure 10 37 Undershoot Timing The IMFA bit of channel 3 is set to 1 for increment pulses and the OVF bit of channel 4 is set to 1 for underflows only The buffer register BR set for the buffer operation is transferred to GR upon compare match A3 when incrementing o...

Page 311: ... Buffer Transfers when Changing from Increment to Decrement When the contents of GR are in the range GRA3 T 1 to GRA3 do not transfer a value outside this range When the contents of GR are outside this range do not a transfer a value within it Figure 10 39 illustrates a point for caution regarding changing of GR settings with buffer operation GRA3 1 GRA3 GRA3 T 1 GRA3 T TCNT3 TCNT4 Changes prohibi...

Page 312: ...writing a setting from outside the count area into the buffer register BR the same as the count direction when writing the setting that returns to within the count area in BR GRA3 GR H 0000 Output pin Output pin BR GR 0 duty 100 duty Write on decrement Write on increment Figure 10 41 Example of Changing GR Settings with Buffer Operation 2 The above settings are made by detecting the occurrence of ...

Page 313: ...de Figure 10 42 shows the procedure for selecting phase counting mode 1 Set the MDF bit in the timer mode register TMDR to 1 to select phase counting mode 2 Select the flag set conditions using the FDIR bit in TMDR 3 Set the STR2 bit in the timer start register TSTR to 1 to start the count 1 2 3 Phase counting mode Start counting Phase counting mode Select phase counting mode Select flag setting c...

Page 314: ...ent Decrement TCLKB Rising High Falling Low Rising High Falling Low TCLKA Low Rising High Falling High Falling Low Rising TCLKA TCLKB Phase differential Phase differential overlap 1 5 cycles minimum Pulse width 2 5 cycles minimum Phase differential Pulse width Pulse width Overlap Overlap Figure 10 44 Phase Differentials Overlap and Pulse Width in Phase Counting Mode ...

Page 315: ...s in the channel This is illustrated in figure 10 45 BR GR Comparator TCNT Compare match signal Figure 10 45 Compare Match Buffer Operation GR is an Input Capture Register TCNT values are transferred to GR when input capture occurs and the value previously stored in GR is transferred to BR This operation is illustrated in figure 10 46 Input capture signal BR GR TCNT Figure 10 46 Input Capture Buff...

Page 316: ...rt counting Buffer mode Figure 10 47 Procedure for Selecting Buffer Mode Buffer Mode Operation Figure 10 48 shows an example of an operation in buffer mode with GRA set as an output compare register and GRA and buffer register A BRA set for buffer operation TCNT operates as a periodic counter that is cleared by a GRB compare match TIOCA and TIOCB are set to toggle at compare matches A and B Since ...

Page 317: ...er signal BR GR n n 1 N n N Figure 10 49 Compare Match Timing Example for Buffer Operation Figure 10 50 shows an example of input capture operation in buffer mode between GRA and BRA with GRA as an input capture register TCNT is cleared by input capture B The falling edge is selected as the input capture edge at TIOCB Both edges are selected as input capture edges at TIOCA When the TCNT value is s...

Page 318: ...at input capture B Time H 0005 H 0160 H 0005 H 0160 H 0180 Input capture A Figure 10 50 Buffer Mode Operation Example 2 Input Capture Register CK TIOC pin Input capture signal TCNT BR GR n n 1 N N 1 M m n n N M M n Figure 10 51 Input Capture Timing Example for Buffer Operation ...

Page 319: ...on a PWM waveform with a duty cycle of 0 is generated The transfer from BRB to GRB occurs upon TCNT3 and GRA compare match and TCNT4 underflow TCNT3 and TCNT4 values H 1FFF GRA3 H 0999 H 0000 BRB3 GRB3 TIOCA3 TIOCB3 H 1FFF H 1FFF Time H 0999 H 0999 H 1FFF H 0999 TCNT3 TCNT4 GRB3 H 0999 H 0999 Figure 10 52 Buffer Mode Operation Example 3 Complementary PWM Mode ...

Page 320: ... Output levels can be inverted by inverting the output level select bits OLS4 and OLS3 in TOCR in complementary PWM mode and reset synchronized PWM mode Figure 10 53 illustrates the timing T1 T3 T2 CK Address TOCR Inversion TOCR address ITU output pin Figure 10 53 Example of Inverting ITU Output Levels by Writing to TOCR ...

Page 321: ...matches a general register The compare match signal is generated in the last state in which the values match when TCNT is updated from the matching count to the next count Therefore when TCNT matches GRA or GRB the compare match signal is not generated until the next timer clock input Figure 10 54 shows the timing of setting the IMF bits CK TCNT input clock TCNT GR Compare match signal IMF IMI N N...

Page 322: ... 55 shows the timing CK Input capture signal TCNT GR IMF IMI N N Figure 10 55 Timing of Setting IMFA and IMFB for Input Capture Timing of Setting Overflow Flag OVF OVF is set to 1 when TCNT overflows from H FFFF to H 0000 or underflows from H 0000 to H FFFF Figure 10 56 shows the timing H FFFF H 0000 CK TCNT Overflow signal OVF OVI Figure 10 56 Timing of Setting OVF ...

Page 323: ...ing The status flags are cleared by being read by the CPU when set to 1 then being written with 0 This timing is shown in figure 10 57 T1 T3 T2 CK Address IMF OVF TSR address TSR write cycle Figure 10 57 Timing of Status Flag Clearing ...

Page 324: ...AC to transfer data Table 10 17 lists the interrupt sources Table 10 17 ITU Interrupt Sources Channel Interrupt Source Description DMAC Activation Priority Order 0 IMIA0 Compare match or input capture A0 Yes High IMIB0 Compare match or input capture B0 No OVI0 Overflow 0 No 1 IMIA1 Compare match or input capture A1 Yes IMIB1 Compare match or input capture B1 No OVI1 Overflow 1 No 2 IMIA2 Compare m...

Page 325: ...CNT Write and Clear If a counter clear signal occurs in the T3 state of a TCNT write cycle clearing the counter takes priority and the write is not performed The timing is shown in figure 10 58 T1 T3 T2 CK Address Internal write signal Counter clear signal TCNT TCNT write cycle by CPU TCNT address N H 0000 Figure 10 58 Contention between TCNT Write and Clear ...

Page 326: ...te of a TCNT word write cycle writing takes priority and TCNT is not incremented The timing is shown in figure 10 59 T1 T3 T2 CK Address Internal write signal TCNT input clock TCNT TCNT word write cycle by CPU TCNT address N M TCNT write data Figure 10 59 Contention between TCNT Word Write and Increment ...

Page 327: ...ten is not incremented The TCNT byte data that was not written is also not incremented and retains its previous value The timing is shown in figure 10 60 which shows an increment during state T2 of a byte write cycle to TCNTH T1 T3 T2 CK Address Internal write signal TCNT input clock TCNTH TCNTH byte write cycle by CPU TCNTH address N M TCNT write data X X 1 X TCNTL Figure 10 60 Contention between...

Page 328: ...r GR write cycle writing takes priority and the compare match signal is inhibited The timing is shown in figure 10 61 T1 T2 T3 GR write cycle GR address N N 1 N M GR write data Inhibited CK Address Internal write signal TCNT GR Compare match signal Figure 10 61 Contention between General Register Write and Compare Match ...

Page 329: ...writing takes priority over counter incrementing OVF is set to 1 The same applies to underflows The timing is shown in figure 10 62 T1 T2 T3 TCNT write cycle TCNT address H FFFF M TCNT write data CK Address Internal write signal TCNT input clock Overflow signal TCNT OVF Figure 10 62 Contention between TCNT Write and Overflow ...

Page 330: ...uring the T3 state of a general register read cycle the value before input capture is read The timing is shown in figure 10 63 T1 T2 T3 GR read cycle GR address X M CK Address Internal read signal Input capture signal GR Internal data bus X Figure 10 63 Contention between General Register Read and Input Capture ...

Page 331: ...cleared by the input capture signal The counter is not incremented by the increment signal The TCNT value before the counter is cleared is transferred to the general register The timing is shown in figure 10 64 N H 0000 CK Input capture signal Counter clear signal TCNT input clock TCNT GR N Figure 10 64 Contention between Counter Clearing by Input Capture and Counter Increment ...

Page 332: ...ess M CK Address Internal write signal Input capture signal TCNT GR M Figure 10 65 Contention between General Register Write and Input Capture 10 6 9 Note on Waveform Cycle Setting When a counter is cleared by compare match the counter is cleared in the last state in which the TCNT value matches the GR value when TCNT is updated from the matching count to the next count The actual counter frequenc...

Page 333: ...n input capture signal is generated in the T3 state of the write cycle the buffer operation takes priority over the BR write The timing is shown in figure 10 66 T1 T2 T3 BR write cycle BR address N X CK Address Internal write signal Input capture signal GR BR M N TCNT value Figure 10 66 Contention between BR Write and Input Capture ...

Page 334: ...e Lower byte Figure 10 67 Byte Write to Channel 2 or Byte Write to Channel 3 A B TCNT2 A B TCNT3 Word write of AB for channel 2 or 3 W X TCNT2 Y Z TCNT3 Upper byte Lower byte Upper byte Lower byte Figure 10 68 Word Write to Channel 2 or Word Write to Channel 3 10 6 12 Note on Setting Reset Synchronized PWM Mode Complementary PWM Mode When the CMD1 and CMD0 bits in TFCR are set note the following 1...

Page 335: ...3 and TCNT4 will stop counting Clearing complementary PWM mode by any other procedure may result in changes other than those set for the output waveform when complementary PWM mode is set again Complementary PWM mode Normal operation 1 2 Clear the CMD1 bit in TFCR to 0 to set channels 3 and 4 for normal operation Wait at least 1 clock cycle after setting channels 3 and 4 for normal operation and t...

Page 336: ...put compare B function IOB2 0 others don t care Input capture A function PWM0 0 IOA2 1 others don t care Input capture B function PWM0 0 IOB2 1 others don t care Counter Clear Function Clear at compare match input capture A CCLR1 0 CCLR0 1 Clear at compare match input capture B CCLR1 1 CCLR0 0 Synch ronized clear SYNC0 1 CCLR1 1 CCLR0 1 Settable Setting does not affect current mode Note In PWM mod...

Page 337: ...function IOB2 0 others don t care Input capture A function PWM1 0 IOA2 1 others don t care Input capture B function PWM1 0 IOB2 1 others don t care Counter Clear Function Clear at compare match input capture A CCLR1 0 CCLR0 1 Clear at compare match input capture B CCLR1 1 CCLR0 0 Synch ronized clear SYNC1 1 CCLR1 1 CCLR0 1 Settable Setting does not affect current mode Note In PWM mode the input ca...

Page 338: ...B2 0 others don t care Input capture A function PWM2 0 IOA2 1 others don t care Input capture B function PWM2 0 IOB2 1 others don t care Counter Clear Function Clear at compare match input capture A CCLR1 0 CCLR0 1 Clear at compare match input capture B CCLR1 1 CCLR0 0 Synch ronized clear SYNC2 1 CCLR1 1 CCLR0 1 Phase counting MDF 1 Settable Setting does not affect current mode Note In PWM mode th...

Page 339: ...ion PWM3 0 CMD1 0 CMD1 0 IOA2 0 others don t care Output compare B function CMD1 0 CMD1 0 IOB2 0 others don t care Input capture A function PWM3 0 CMD1 0 CMD1 0 IOA2 1 others don t care Input capture B function PWM3 0 CMD1 0 CMD1 0 IOB2 1 others don t care Counter Clear Function Clear at compare match input capture A CMD1 1 CMD0 0 inhib ited 3 CCLR1 0 CCLR0 1 Clear at compare match input capture B...

Page 340: ...RA BFA3 1 others don t care Buffer BRB BFB3 1 others don t care Settable Setting does not affect current mode Notes 1 In PWM mode the input capture function cannot be used When compare match A and compare match B occur simultaneously the compare match signal is inhibited 2 When set for complementary PWM mode do not simultaneously set channel 3 and channel 4 to function synchronously 3 Counter clea...

Page 341: ... CMD1 0 CMD1 0 IOA2 0 others don t care Output compare B function CMD1 0 CMD1 0 IOB2 0 others don t care Input capture A function PWM4 0 CMD1 0 CMD1 0 IOA2 1 others don t care Input capture B function PWM4 0 CMD1 0 CMD1 0 IOB2 1 others don t care Counter Clear Function Clear at compare match input capture A CMD1 1 CMD0 0 inhib ited 3 CCLR1 0 CCLR0 1 Clear at compare match input capture B CMD1 1 CM...

Page 342: ...Setting does not affect current mode Notes 1 In PWM mode the input capture function cannot be used When compare match A and compare match B occur simultaneously the compare match signal is inhibited 2 When set for complementary PWM mode do not simultaneously set channel 3 and channel 4 to function synchronously 3 Counter clearing works with reset synchronized PWM mode but TCNT4 runs independently ...

Page 343: ...308 ...

Page 344: ...bit output data Maximum 16 bit data can be output TPC output can be enabled on a bit by bit basis Four output groups Output trigger signals can be selected in 4 bit groups to provide up to four different 4 bit outputs Selectable output trigger signals Output trigger signals can be selected by group from the 4 channel compare match signals of the 16 bit integrated timer pulse unit ITU Non overlap m...

Page 345: ...compare match signal TP15 TP14 TP13 TP12 TP11 TP10 TP9 TP8 TP7 TP6 TP5 TP4 TP3 TP2 TP1 TP0 Internal data bus NDRB NDRA TPC TPMR TPC output mode register PBCR1 Port B control register 1 TPCR TPC output control register PBCR2 Port B control register 2 NDERB Next data enable register B NDRB Next data register B NDERA Next data enable register A NDRA Next data register A PBDR Port B data register Figu...

Page 346: ...output 2 TP2 Output TPC output 3 TP3 Output TPC output 4 TP4 Output Group 1 pulse output TPC output 5 TP5 Output TPC output 6 TP6 Output TPC output 7 TP7 Output TPC output 8 TP8 Output Group 2 pulse output TPC output 9 TP9 Output TPC output 10 TP10 Output TPC output 11 TP11 Output TPC output 12 TP12 Output Group 3 pulse output TPC output 13 TP13 Output TPC output 14 TP14 Output TPC output 15 TP15 ...

Page 347: ...FFF5 H 5FFFFF7 3 8 16 Next data register B NDRB R W H 00 H 5FFFFF4 H 5FFFFF6 3 8 16 Notes 1 Only the values of bits A27 A24 and A8 A0 are valid bits A23 A9 are ignored For details on the register addresses see section 8 3 5 Area Descriptions 2 Bits used for TPC output cannot be written to 3 These addresses change depending on the TPCR settings When TPC output groups 0 and 1 have the same output tr...

Page 348: ...10 9 8 Bit name PB15 MD1 PB15 MD0 PB14 MD1 PB14 MD0 PB13 MD1 PB13 MD0 PB12 MD1 PB12 MD0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 Bit name PB11 MD1 PB11 MD0 PB10 MD1 PB10 MD0 PB9 MD1 PB9 MD0 PB8 MD1 PB8 MD0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W PCBR2 Bit 15 14 13 12 11 10 9 8 Bit name PB7MD1 PB7MD0 PB6MD1 PB6MD0 PB5MD1 PB5MD0 ...

Page 349: ...oups 1 and 0 TP7 TP0 When used for TPC output the contents of NDRA are transferred to the corresponding PBDR bits when the ITU compare match specified in the TPC output control register TPCR occurs The address of NDRA differs depending on whether TPCR settings select the same trigger or different triggers for TPC output groups 1 and 0 NDRA is initialized to H 00 by a reset It is not initialized in...

Page 350: ...address of the lower 4 bits of NDRA group 0 is H 5FFFFF7 Bits 3 0 of address H 5FFFFF5 and bits 7 4 of address H 5FFFFF7 are reserved bits The write value should always be 1 These bits are always read as 1 Address H 5FFFFF5 Bits 7 4 Next Data 7 4 NDR7 NDR4 NDR7 NDR4 store the next output data for TPC output group 1 Bits 3 0 Reserved These bits are always read as 1 The write value should always be ...

Page 351: ...itialized in standby mode Same Trigger for TPC Output Groups 3 and 2 If TPC output groups 3 and 2 are triggered by the same compare match the address of NDRB is H FFFFF4 The upper 4 bits become group 3 and the lower 4 bits become group 2 Address H 5FFFFF6 consists entirely of reserved bits These bits are always read as 1 and the write value should always be 1 Address H 5FFFFF4 Bits 7 4 Next Data 1...

Page 352: ...rite value should always be 1 Address H 5FFFFF4 Bits 7 4 Next Data 15 12 NDR15 NDR12 NDR15 NDR12 store the next output data for TPC output group 3 Bits 3 0 Reserved These bits are always read as 1 The write value should always be 1 Bit 7 6 5 4 3 2 1 0 Bit name NDR15 NDR14 NDR13 NDR12 Initial value 0 0 0 0 1 1 1 1 R W R W R W R W R W Address H 5FFFFF6 Bits 7 4 Reserved These bits are always read as...

Page 353: ...ing disabling for TPC output groups 1 and 0 TP7 TP0 in bit units Bit 7 0 NDER7 NDER0 Description 0 Disables TPC outputs TP7 TP0 transfer from NDR7 NDR0 to PB7 PB0 is disabled Initial value 1 Enables TPC outputs TP7 TP0 transfer from NDR7 NDR0 to PB7 PB0 is enabled 11 2 6 Next Data Enable Register B NDERB NDERB is an eight bit read write register that enables TPC output groups 3 and 2 TP15 TP8 on a...

Page 354: ... initialized in standby mode Bit 7 6 5 4 3 2 1 0 Bit name G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W Bits 7 and 6 Group 3 Compare Match Select 1 and 0 G3CMS1 and G3CMS0 G3CMS1 and G3CMS0 select the compare match that triggers TPC output group 3 TP15 TP12 Bit 7 G3CMS1 Bit 6 G3CMS0 Description 0 0 TPC output group 3 TP15 ...

Page 355: ...1 Bit 2 G1CMS0 Description 0 0 TPC output group 1 TP7 TP4 output is triggered by compare match in ITU channel 0 1 TPC output group 1 TP7 TP4 output is triggered by compare match in ITU channel 1 1 0 TPC output group 1 TP7 TP4 output is triggered by compare match in ITU channel 2 1 TPC output group 1 TP7 TP4 output is triggered by compare match in ITU channel 3 Initial value Bits 1 and 0 Group 0 Co...

Page 356: ...e should always be 1 Bit 3 Group 3 Non Overlap Mode G3NOV G3NOV selects ordinary or non overlap mode for TPC output group 3 TP15 TP12 Bit 3 G3NOV Description 0 TPC output group 3 operates normally output value updated according to compare match A of the ITU channel selected by TPCR Initial value 1 TPC output group 3 operates in non overlap mode 1 output and 0 output can be performed independently ...

Page 357: ...t group 0 TP3 TP0 Bit 0 G0NOV Description 0 TPC output group 0 operates normally output value updated according to compare match A of the ITU channel selected by TPCR Initial value 1 TPC output group 0 operates in non overlap mode 1 output and 0 output can be performed independently according to compare match A and B of the ITU channel selected by TPCR 11 3 Operation 11 3 1 Overview When correspon...

Page 358: ...its of data can be output at each successive compare match See section 11 3 4 TPC Output Non Overlap Operation for details on non overlap operation 11 3 2 Output Timing If TPC output is enabled next data register NDRA NDRB contents are transferred to the data register PBDR and output when the selected compare match occurs Figure 11 3 shows the timing of these operations The example is for ordinary...

Page 359: ...R1 and CCLR0 bits 4 Set the timer interrupt enable register TIER to enable IMIA interrupts Transfers to NDR can also be set using the DMAC 5 Set the initial output value in the I O port data register to be used by the TPC 6 Set the I O port control register to be used by the TPC as the TP pin function 11 7 Set to 1 the bit that performs TPC output to the next data enable register NDER 8 Select the...

Page 360: ... 3 4 5 6 7 8 9 10 11 Compare match Ordinary TPC output operation Set next TPC output value Set next TPC output value Start count Select TPC output trigger Set TPC output enable Set port output Set initial output value Select interrupt request Figure 11 4 Example of Setting Procedure for Ordinary TPC Output ...

Page 361: ... Write output data H 80 in NDRB 3 When the selected ITU channel starts operating and a compare match occurs the values in NDRB are transferred to PBDR and output The compare match input capture A IMIA interrupt handling routine writes the next output data H C0 in NDRB 4 Five phase pulse output can be obtained by writing H 40 H 60 H 20 H 30 H 10 H 18 H 08 H 88 at successive compare match interrupts...

Page 362: ...terrupts Transfers to NDR can also be set using the DMAC 5 Set the initial output value in the I O port data register to be used by the TPC 6 Set the I O port control register to be used by the TPC as the TP pin function 11 7 Set to 1 the bit that performs TPC output to the next data enable register NDER 8 Select the ITU compare match that will be the TPC output trigger using the TPC output contro...

Page 363: ... 1 2 3 4 5 6 7 8 9 11 12 Compare match A 10 Select interrupt request Set TPC transfer enable Select TPC output trigger Select non overlap group Set next TPC output value TPC output non overlap operation Set next TPC output value Set initial output value Figure 11 6 Example of Setting Procedure for TPC Output Non Overlap Operation ...

Page 364: ...in step 1 as the output trigger Set the G3NOV and G2NOV bits in TPMR to 1 to set non overlap operation Write output data H 95 in NDRB 3 When the selected ITU channel starts operating and a GRB compare match occurs 1 output changes to 0 output when a GRA compare match occurs 0 output changes to 1 output The change from 0 output to 1 output is delayed by the value set in GRA The IMIA interrupt handl...

Page 365: ...6 95 65 NDRB H 0000 GRA GRB PBDR TP15 TP14 TP13 TP12 TP11 TP9 TP8 TP10 TCNT value TCNT 00 95 05 65 41 59 50 56 14 95 05 65 Time Non overlap cycle Figure 11 7 Non Overlap Output Example Four Phase Complementary Output ...

Page 366: ...than ITU compare matches The general register A GRA of the ITU selected by TPCR functions as an input capture register and TPC output occurs in response to an input capture signal Figure 11 8 shows the timing M N N CK TIOC pin Input capture signal NDR DR Figure 11 8 TPC Output by Input Capture ...

Page 367: ...nsferred to DR on compare match A 2 The contents of bits transferred from NDR are only transferred on compare match B when they are 0 No transfer occurs for a 1 Figure 11 9 illustrates TPC output during non overlap operation CR Q NDER Q TPC output pin Port function select DR Q C D NDR Q D Compare match A Compare match B Figure 11 9 TPC Output Non Overlap Operation ...

Page 368: ...his can be ensured by writing the next data to NDR in the IMIA interrupt handling routine The DMAC can also be started using an IMIA interrupt However these write operations should be performed prior to the next compare match B The timing is shown in figure 11 10 Compare match A Compare match B NDR DR NDR write NDR write 0 1 output 0 output NDR write disable period NDR write period 0 1 output 0 ou...

Page 369: ...334 ...

Page 370: ...val timer interrupt is generated at each counter overflow The WDT is also used in recovering from standby mode 12 1 1 Features WDT features are listed below Watchdog timer mode interval timer mode can be selected Outputs WDTOVF in or watchdog timer mode When the counter overflows in watchdog timer mode overflow signal WDTOVF is output externally It is possible to select whether or not to reset the...

Page 371: ...F Internal reset signal WDT TCSR Timer control status register TCNT Timer counter RSTCSR Reset control status register Note The internal reset signal can be generated by a register setting The type of reset can be selected power on or manual reset Figure 12 1 Block Diagram of WDT 12 1 3 Pin Configuration Table 12 1 shows the pin configuration Table 12 1 Pin Configuration Pin Abbreviation I O Funct...

Page 372: ...ails on the register addresses see section 8 3 5 Area Descriptions 12 2 Register Descriptions 12 2 1 Timer Counter TCNT TCNT is an eight bit readable and writable up counter TCNT differs from other registers in that it is more difficult to write See section 12 2 4 Notes on Register Access for details When the timer enable bit TME in the timer control status register TCSR is set to 1 the timer coun...

Page 373: ...ption 0 No overflow of TCNT in interval timer mode Initial value Cleared by reading OVF then writing 0 in OVF 1 TCNT overflow in interval timer mode Bit 6 Timer Mode Select WT IT WT IT selects whether to use the WDT as a watchdog timer or interval timer When TCNT overflows the WDT either generates an interval timer interrupt ITI or generates a WDTOVF signal depending on the mode selected Bit 6 WT ...

Page 374: ...ted is the time from when the TCNT begins counting at H 00 until an overflow occurs 12 2 3 Reset Control Status Register RSTCSR RSTCSR is an eight bit read write register that controls output of the reset signal generated by timer counter TCNT overflow and selects the internal reset signal type RSTCSR differs from other registers in that it is more difficult to write See section 12 2 4 Notes on Re...

Page 375: ...ts the type of internal reset generated if TCNT overflows in watchdog timer mode Bit 5 RSTS Description 0 Power on reset Initial value 1 Manual reset Bits 4 0 Reserved These bits are always read as 1 The write value should always be 1 12 2 4 Notes on Register Access The watchdog timer s TCNT TCSR and RSTCSR registers differ from other registers in that they are more difficult to write The procedur...

Page 376: ... in the lower byte This clears the WOVF bit to 0 The RSTE and RSTS bits are not affected To write to the RSTE and RSTS bits the upper byte must be H 5A and the lower byte must be the write data The values of bits 6 and 5 of the lower byte are transferred to the RSTE and RSTS bits respectively The WOVF bit is not affected Writing 0 to the WOVF bit 15 8 7 0 Address H 5FFFFBA H A5 H 00 Writing to the...

Page 377: ...t external system devices The WDTOVF signal is output for 128 φ clock cycles If the RSTE bit in RSTCSR is set to 1 a signal to reset the chip will be generated internally simultaneous to the WDTOVF signal when TCNT overflows Either a power on reset or a manual reset can be selected by the RSTS bit in RSTCSR The internal reset signal is output for 512 φ clock cycles When a watchdog reset is generat...

Page 378: ...gnal TCNT value WDTOVF and internal reset generated WOVF 1 WT IT 1 TME 1 H 00 written in TCNT Time 512 φ clocks 128 φ clocks WT IT Timer mode select bit TME Timer enable bit Note The internal reset signal is only generated when the RSTE bit is 1 Figure 12 4 Operation in Watchdog Timer Mode ...

Page 379: ...sition to Standby Mode The TME bit in TCSR must be cleared to 0 to stop the watchdog timer counter before it enters standby mode The chip cannot enter standby mode while the TME bit is set to 1 Set bits CKS2 CKS0 so that the counter overflow interval is equal to or longer than the oscillation settling time See sections 20 1 3 and 20 2 3 AC Characteristics for the oscillation settling time Recovery...

Page 380: ...ignal OVF Figure 12 6 Timing of OVF Setting 12 3 5 Timing of Watchdog Timer Overflow Flag WOVF Setting When TCNT overflows the WOVF bit in RSTCSR is set to 1 and a WDTOVF signal is output When the RSTE bit is set to 1 TCNT overflow enables an internal reset signal to be generated for the entire chip figure 12 7 H FF H 00 CK TCNT Overflow signal internal signal WOVF Figure 12 7 Timing of WOVF Bit S...

Page 381: ... TCNT write cycle Figure 12 8 Contention between TCNT Write and Increment 12 4 2 Changing CKS2 CKS0 Bit Values If the values of bits CKS2 CKS0 are altered while the WDT is running the count may increment incorrectly Always stop the watchdog timer by clearing the TME bit to 0 before changing the values of bits CKS2 CKS0 12 4 3 Changing Watchdog Timer Interval Timer Modes To prevent incorrect operat...

Page 382: ... system with the WDTOVF signal use the circuit shown in figure 12 9 Reset input Reset signal to entire system SuperH microcomputer RES WDTOVF Figure 12 9 Example of System Reset Circuit Using WDTOVF Signal 12 4 5 Internal Reset With Watchdog Timer If the RSTE bit is cleared to 0 in watchdog timer mode the chip will not reset internally when a TCNT overflow occurs but TCNT and TCSR in the WDT will ...

Page 383: ...348 ...

Page 384: ...or communication function There are twelve selectable serial data communication formats Data length seven or eight bits Stop bit length one or two bits Parity even odd or none Multiprocessor bit one or none Receive error detection parity overrun and framing errors Break detection by reading the RxD level directly when a framing error occurs Synchronous mode Serial data communication is synchronize...

Page 385: ...ows a block diagram of the SCI Parity generation Parity check Transmit receive control Baud rate generator Clock External clock Bus interface Internal data bus RxD RDR TDR RSR TSR SSR SCR SMR BRR φ φ 4 φ 16 φ 64 TEI TXI RXI ERI SCK TxD SCI Module data bus RSR Receive shift register SMR Serial mode register RDR Receive data register SCR Serial control register TSR Transmit shift register SSR Serial...

Page 386: ...ransmit data pin TxD0 Output SCI0 transmit data output 1 Serial clock pin SCK1 Input output SCI1 clock input output Receive data pin RxD1 Input SCI1 receive data input Transmit data pin TxD1 Output SCI1 transmit data output 13 1 4 Register Configuration Table 13 2 summarizes the SCI internal registers These registers select the communication mode asynchronous or synchronous specify the data format...

Page 387: ...s of bits A27 A24 and A8 A0 are valid bits A23 A9 are ignored For details on the register addresses see section 8 3 5 Area Descriptions 2 Only 0 can be written to clear flags 13 2 Register Descriptions 13 2 1 Receive Shift Register The receive shift register RSR receives serial data Data input at the RxD pin is loaded into RSR in the order received LSB bit 0 first In this way the SCI converts rece...

Page 388: ...e TDRE bit in SSR is 1 however the SCI does not load the TDR contents into TSR The CPU cannot read or write to TSR directly Bit 7 6 5 4 3 2 1 0 Bit name R W 13 2 4 Transmit Data Register The transmit data register TDR is an eight bit register that stores data for serial transmission When the SCI detects that the transmit shift register TSR is empty it moves transmit data written in TDR into TSR an...

Page 389: ...CHR selects seven bit or eight bit data in asynchronous mode In synchronous mode the data length is always eight bits regardless of the CHR setting Bit 6 CHR Description 0 Eight bit data Initial value 1 Seven bit data When seven bit data is selected the MSB bit 7 of the transmit data register is not transmitted Bit 5 Parity Enable PE PE selects whether to add a parity bit to transmit data and chec...

Page 390: ...Length STOP STOP selects one or two bits as the stop bit length in asynchronous mode This setting is used only in asynchronous mode It is ignored in synchronous mode because no stop bits are added In receiving only the first stop bit is checked regardless of the STOP bit setting If the second stop bit is 1 it is treated as a stop bit If the second stop bit is 0 it is treated as the start bit of th...

Page 391: ...the transmit receive clock source The CPU can always read and write to SCR SCR is initialized to H 00 by a reset and in standby mode Bit 7 6 5 4 3 2 1 0 Bit name TIE RIE TE RE MPIE TEIE CKE1 CKE0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 Transmit Interrupt Enable TIE TIE enables or disables the transmit data empty interrupt TXI requested when the transmit data registe...

Page 392: ...pty bit TDRE in the serial status register SSR is fixed at 1 1 Transmitter enabled Serial transmission starts when the transmit data register empty TDRE bit in the serial status register SSR is cleared to 0 after writing transmit data into TDR Select the transmit format in SMR before setting TE to 1 Bit 4 Receive Enable RE RE enables or disables the SCI receiver Bit 4 RE Description 0 Receiver dis...

Page 393: ...tain new transmit data when the MSB is transmitted Bit 2 TEIE Description 0 Transmit end interrupt TEI requests are disabled Initial value The TEI request can be cleared by reading the TDRE bit in the serial status register SSR after it has been set to 1 then clearing TDRE to 0 by clearing the transmit end TEND bit to 0 or by clearing the TEIE bit to 0 1 Transmit end interrupt TEI requests are ena...

Page 394: ...ction and SCK input output for the SCK pin 2 Initial value 3 The output clock frequency is the same as the bit rate 4 The input clock frequency is 16 times the bit rate 13 2 7 Serial Status Register The serial status register SSR is an 8 bit register containing multiprocessor bit values and status flags that indicate the SCI operating status The CPU can always read and write to SSR but cannot writ...

Page 395: ...ription 0 RDR does not contain valid received data Initial value RDRF is cleared to 0 when The chip is reset or enters standby mode Software reads RDRF after it has been set to 1 then writes 0 in RDRF The DMAC reads data from RDR 1 RDR contains valid received data RDRF is set to 1 when serial data is received normally and transferred from RSR to RDR Note RDR and RDRF are not affected by detection ...

Page 396: ...ormally due to a framing error in the asynchronous mode Bit 4 FER Description 0 Receiving is in progress or has ended normally Initial value Clearing the RE bit to 0 in the serial control register does not affect the FER bit which retains its previous value FER is cleared to 0 when The chip is reset or enters standby mode Software reads FER after it has been set to 1 then writes 0 in FER 1 A recei...

Page 397: ...n the last bit of a serial character was transmitted TDR did not contain new transmit data so transmission has ended TEND is a read only bit and cannot be written Bit 2 TEND Description 0 Transmission is in progress TEND is cleared to 0 when Software reads TDRE after it has been set to 1 then writes 0 in TDRE The DMAC writes data in TDR 1 End of transmission Initial value TEND is set to 1 when The...

Page 398: ... Rate Register BRR The bit rate register BRR is an eight bit register that together with the baud rate generator clock source selected by the CKS1 and CKS0 bits in the serial mode register SMR determines the serial transmit receive bit rate The CPU can always read and write to BRR BRR is initialized to H FF by a reset and in standby mode SCI0 and SCI1 have independent baud rate generator control s...

Page 399: ...9200 31250 0 1 0 00 38400 Table 13 3 Bit Rates and BRR Settings in Asynchronous Mode cont φ MHz 2 4576 3 3 6864 Bit Rate bits s n N Error n N Error n N Error 110 1 174 0 26 1 212 0 03 2 64 0 70 150 1 127 0 00 1 155 0 16 1 191 0 00 300 0 255 0 00 1 77 0 16 1 95 0 00 600 0 127 0 00 0 155 0 16 0 191 0 00 1200 0 63 0 00 0 77 0 16 0 95 0 00 2400 0 31 0 00 0 38 0 16 0 47 0 00 4800 0 15 0 00 0 19 2 34 0 ...

Page 400: ... 0 00 0 15 1 73 19200 0 7 0 00 0 7 1 73 31250 0 3 0 00 0 4 1 70 0 4 0 00 38400 0 3 0 00 0 3 1 73 Table 13 3 Bit Rates and BRR Settings in Asynchronous Mode cont φ MHz 6 6 144 7 3728 Bit Rate bits s n N Error n N Error n N Error 110 2 106 0 44 2 108 0 08 2 130 0 07 150 2 77 0 16 2 79 0 00 2 95 0 00 300 1 155 0 16 1 159 0 00 1 191 0 00 600 1 77 0 16 1 79 0 00 1 95 0 00 1200 0 155 0 16 0 159 0 00 0 1...

Page 401: ...00 0 15 1 73 0 19 2 34 31250 0 7 0 00 0 9 1 70 0 9 0 00 0 11 0 00 38400 0 7 0 00 0 7 1 73 0 9 2 34 Table 13 3 Bit Rates and BRR Settings in Asynchronous Mode cont φ MHz 12 288 14 14 7456 16 Bit Rate bits s n N Error n N Error n N Error n N Error 110 2 217 0 08 2 248 0 17 3 64 0 70 3 70 0 03 150 2 159 0 00 2 181 0 16 2 191 0 00 2 207 0 16 300 2 79 0 00 2 90 0 16 2 95 0 00 2 103 0 16 600 1 159 0 00 ...

Page 402: ...16 0 16 2 127 0 00 2 129 0 16 600 1 223 0 00 1 233 0 16 1 255 0 00 2 64 0 16 1200 1 111 0 00 1 116 0 16 1 127 0 00 1 129 0 16 2400 0 223 0 00 0 233 0 16 0 255 0 00 1 64 0 16 4800 0 111 0 00 0 116 0 16 0 127 0 00 0 129 0 16 9600 0 55 0 00 0 58 0 69 0 63 0 00 0 64 0 16 19200 0 27 0 00 0 28 1 02 0 31 0 00 0 32 1 36 31250 0 16 1 20 0 17 0 00 0 19 1 70 0 19 0 00 38400 0 13 0 00 0 14 2 34 0 15 0 00 0 15...

Page 403: ...0 9 0 19 0 39 0 49 0 79 0 99 100k 0 4 0 9 0 19 0 24 0 39 0 49 250k 0 1 0 3 0 7 0 9 0 15 0 19 500k 0 0 0 1 0 3 0 4 0 7 0 9 1M 0 0 0 1 0 3 0 4 2 5M 0 0 0 1 5M 0 0 Blank No setting available Setting possible but error occurs Continuous transmission reception not possible The BRR setting is calculated as follows Asynchronous mode N φ 64 22n 1 B 106 1 Synchronous mode N φ 8 22n 1 B 106 1 B Bit rate bit...

Page 404: ...369 SMR Settings n Clock Source CKS1 CKS0 0 φ 0 0 1 φ 4 0 1 2 φ 16 1 0 3 φ 64 1 1 The bit rate error for asynchronous mode is given by the following formula Error φ 106 N 1 B 64 22n 1 1 100 ...

Page 405: ...d Rate Generator Asynchronous Mode Settings φ MHz Maximum Bit Rate bits s n N 2 62500 0 0 2 097152 65536 0 0 2 4576 76800 0 0 3 93750 0 0 3 6864 115200 0 0 4 125000 0 0 4 9152 153600 0 0 5 156250 0 0 6 187500 0 0 6 144 192000 0 0 7 3728 230400 0 0 8 250000 0 0 9 8304 307200 0 0 10 312500 0 0 12 375000 0 0 12 288 384000 0 0 14 437500 0 0 14 7456 460800 0 0 16 500000 0 0 17 2032 537600 0 0 18 562500...

Page 406: ...0 6144 38400 3 0 7500 46875 3 6864 0 9216 57600 4 1 0000 62500 4 9152 1 2288 76800 5 1 2500 78125 6 1 5000 93750 6 144 1 5360 96000 7 3728 1 8432 115200 8 2 0000 125000 9 8304 2 4576 153600 10 2 5000 156250 12 3 0000 187500 12 288 3 0720 192000 14 3 5000 218750 14 7456 3 6834 230400 16 4 0000 250000 17 2032 4 3008 268800 18 4 5000 281250 19 6608 4 9152 307200 20 5 0000 312500 ...

Page 407: ... SCI clock source is selected by the C A bit in the serial mode register SMR and the CKE1 and CKE0 bits in the serial control register SCR as shown in table 13 9 Asynchronous Mode Data length is selectable seven or eight bits Parity and multiprocessor bits are selectable and so is the stop bit length one or two bits The preceding selections constitute the communication format and character length ...

Page 408: ...put serial clock The on chip baud rate generator is not used Table 13 8 Serial Mode Register Settings and SCI Communication Formats SMR Settings SCI Communication Format Mode Bit 7 C A Bit 6 CHR Bit 5 PE Bit 2 MP Bit 3 STOP Data Length Parity Bit Multipro cessor Bit Stop Bit Length Asynchronous 0 0 0 0 0 8 bit Absent Absent 1 bit 1 2 bits 1 0 Present 1 bit 1 2 bits 1 0 0 7 bit Absent 1 bit 1 2 bit...

Page 409: ...he transmitting and receiving sections of the SCI are independent so full duplex communication is possible The transmitter and receiver are both double buffered so data can be written and read while transmitting and receiving are in progress enabling continuous transmitting and receiving Figure 13 2 shows the general format of asynchronous serial communication In asynchronous serial communication ...

Page 410: ...ta Start bit 1 bit Transmit receive data 7 or 8 bits One unit of communication character or frame Idle mark state Parity bit Stop bit 1 or no bit 1 or 2 bits Figure 13 2 Data Format in Asynchronous Communication Example 8 Bit Data with Parity and Two Stop Bits ...

Page 411: ...TART 7 bit data P STOP 1 1 0 1 START 7 bit data P STOP STOP 0 1 0 START 8 bit data MPB STOP 0 1 1 START 8 bit data MPB STOP STOP 1 1 0 START 7 bit data MPB STOP 1 1 1 START 7 bit data MPB STOP STOP Don t care bits Notes START Start bit STOP Stop bit P Parity bit MPB Multiprocessor bit Clock An internal clock generated by the on chip baud rate generator or an external clock input from the SCK pin c...

Page 412: ...d ORER flags and receive data register RDR which retain their previous contents When an external clock is used the clock should not be stopped during initialization or subsequent operation SCI operation becomes unreliable if the clock is stopped Figure 13 4 shows a sample flowchart for initializing the SCI The procedure for initializing the SCI is as follows 1 Select the communication format in th...

Page 413: ...ows 1 SCI initialization select the TxD pin function with the PFC 2 SCI status check and transmit data write read the serial status register SSR check that the TDRE bit is 1 then write transmit data in the transmit data register TDR and clear TDRE to 0 3 To continue transmitting serial data read the TDRE bit to check whether it is safe to write 1 if so write data in TDR then clear TDRE to 0 When t...

Page 414: ... to 0 Select theTxD pin function as an output port with the PFC TEND 1 Transmission ends 1 2 3 No Yes TDRE 1 Write transmit data in TDR and clear TDRE bit to 0 in SSR All data transmitted No Yes Output break signal No Yes Set DR 0 4 Yes No Figure 13 5 Sample Flowchart for Transmitting Serial Data ...

Page 415: ...ata are output LSB first 3 Parity bit or multiprocessor bit one parity bit even or odd parity or one multiprocessor bit is output Formats in which neither a parity bit nor a multiprocessor bit is output can also be selected 4 Stop bit one or two 1 bits stop bits are output 5 Mark state output of 1 bits continues until the start bit of the next transmit data 6 The SCI checks the TDRE bit when it ou...

Page 416: ... a receive error occurs read the ORER PER and FER bits in SSR to identify the error After executing the necessary error handling clear ORER PER and FER all to 0 Receiving cannot resume if ORER PER or FER remains set to 1 When a framing error occurs the RxD pin can be read to detect the break state 3 SCI status check and receive data read read the serial status register SR check that RDRF is set to...

Page 417: ... Total count received Reception ends 1 No Yes PER FER ORER 1 RDRF 1 Yes Yes Clear the RE bit in SCR to 0 No No Read the RDRF bit in SSR Error handling 3 2 Read the RDR s receive data and clear the RDRF bit in SSR to 0 4 Figure 13 7 Sample Flowchart for Receiving Serial Data ...

Page 418: ...Overrun error handling FER 1 Yes Break No Framing error handling PER 1 Yes Parity error handling Clear ORER PER and FER to 0 in SSR End Clear RE bit to 0 in SCR No No No Yes Yes Figure 13 7 Sample Flowchart for Receiving Serial Data cont ...

Page 419: ...perates as indicated in table 13 11 Note When a receive error flag is set further receiving is disabled The RDRF bit is not set to 1 Be sure to clear the error flags 4 After setting RDRF to 1 if the receive data full interrupt enable bit RIE is set to 1 in SCR the SCI requests a receive data full interrupt RXI If one of the error flags ORER PER or FER is set to 1 and the receive data full interrup...

Page 420: ...e receiving processor and a data sending cycle The multiprocessor bit distinguishes ID sending cycles from data sending cycles The transmitting processor starts by sending the ID of the receiving processor with which it wants to communicate as data with the multiprocessor bit set to 1 Next the transmitting processor sends transmit data with the multiprocessor bit cleared to 0 Receiving processors ...

Page 421: ...shows a sample flowchart for transmitting multiprocessor serial data The procedure for transmitting multiprocessor serial data is listed below 1 SCI initialization select the TxD pin function with the PFC 2 SCI status check and transmit data write read the serial status register SSR check that the TDRE bit is 1 then write transmit data in the transmit data register TDR Also set MPBT multiprocessor...

Page 422: ...it in SSR Output break signal Yes Set DR 0 Clear TE bit to 0 in SCR select theTxD pin function as an output port with the PFC End Yes Read TDRE bit in SSR Clear TDRE bit to 0 Initialize No No Yes No No 1 2 3 4 Start transmitting Figure 13 10 Sample Flowchart for Transmitting Multiprocessor Serial Data ...

Page 423: ... d Stop bit one or two 1 bits stop bits are output e Mark state output of 1 bits continues until the start bit of the next transmit data 3 The SCI checks the TDRE bit when it outputs the stop bit If TDRE is 0 the SCI loads data from TDR into TSR outputs the stop bit then begins serial transmission of the next frame If TDRE is 1 the SCI sets the TEND bit in SSR to 1 outputs the stop bit then contin...

Page 424: ...the receive data register RDR and compare with the processor s own ID If the ID does not match the receive data set MPIE to 1 again and clear RDRF to 0 If the ID matches the receive data clear RDRF to 0 4 Receive error handling and break detection if a receive error occurs read the ORER and FER bits in SSR to identify the error After executing the necessary error handling clear both ORER and FER t...

Page 425: ...lear the RE bit in SCR to 0 No No 1 2 Read the ORER and FER bits in SSR FER 1 or ORER 1 Read the RDRF bit in SSR Read the receive data in RDR Own ID Yes Read the ORER and FER bits in SSR 3 No Error handling Yes Yes 4 Yes No Start receiving No Yes Read the receive data in RDR 5 Figure 13 12 Sample Flowchart for Receiving Multiprocessor Serial Data ...

Page 426: ...ming error handling Yes Start of error handling Overrun error handling Yes FER 1 Clear ORER and FER to 0 in SSR End No No No Clear RE bit to 0 in SCR Figure 13 12 Sample Flowchart for Receiving Multiprocessor Serial Data cont ...

Page 427: ...handler reads data in RDR and clears RDRF to 0 Not own ID so MPIE is set to 1 again No RXI interrupt RDR maintains state 0 1 1 1 1 0 1 MPB MPB Serial data Start bit Data ID1 Stop bit Start bit Data 1 Stop bit Idle mark state D0 D1 D7 D0 D1 D7 0 MPB Figure 13 13 Example of SCI Receive Operation Own ID Does Not Match Data 8 Bit Data with Multiprocessor Bit and One Stop Bit ...

Page 428: ...Data 8 Bit Data with Multiprocessor Bit and One Stop Bit cont 13 3 4 Synchronous Operation In synchronous mode the SCI transmits and receives data in synchronization with clock pulses This mode is suitable for high speed serial communication The SCI transmitter and receiver share the same clock but are otherwise independent so full duplex communication is possible The transmitter and receiver are ...

Page 429: ...ock generated by the on chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI transmit receive clock The clock source is selected by the C A bit in the serial mode register SMR and bits CKE1 and CKE0 in the serial control register SCR See table 13 6 When the SCI operates on an internal clock it outputs the clock signal at the SCK pin Eight clock pulses are...

Page 430: ...CK pin is held in the high state Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Serial clock Serial data Transmit direction Bit 7 TXI interrupt handler writes data in TDR and clears TDRE to 0 1 frame TXI request TXI request TDRE TEND LSB MSB TEI request Figure 13 15 Example of SCI Transmit Operation Transmitting and Receiving Data SCI Initialization Synchronous Mode Before transmitting or receiving software ...

Page 431: ...ve one bit then set TE or RE in the serial control register SCR to 1 Also set RIE TIE TEIE and MPIE Setting the corresponding bit of the pin function controller TE and RE enables the SCI to use the TxD or RxD pin Start of initialization Clear TE and RE bits to 0 in SCR 3 1 bit interval elapsed Set TE or RE to 1 in SCR Set RIE TIE TEIE and MPIE Select communication format in SMR Yes No Set value in...

Page 432: ...er TDR and clear TDRE to 0 3 To continue transmitting serial data read the TDRE bit to check whether it is safe to write 1 if so write data in TDR then clear TDRE to 0 When the DMAC is started by a transmit data empty interrupt request TXI to write data in TDR the TDRE bit is checked and cleared automatically Start transmitting Read TDRE bit in SSR All data transmitted Yes No Transmission ends 1 2...

Page 433: ...ction if a receive error occurs read the ORER bit in SSR to identify the error After executing the necessary error handling clear ORER to 0 Transmitting receiving cannot resume if ORER remains set to 1 3 SCI status check and receive data read read the serial status register SSR check that RDRF is set to 1 then read receive data from the receive data register RDR and clear RDRF to 0 The RXI interru...

Page 434: ...n SSR Total count received Reception ends 1 No Yes ORER 1 RDRF 1 Yes Clear RE bit in SCR to 0 No No Read RDRF bit in SSR 3 Yes Error handling 2 Read receive data in RDR and clear RDRF bit in SSR to 0 4 Figure 13 18 Sample Flowchart for Serial Receiving ...

Page 435: ...RDRF ORER Figure 13 19 Example of SCI Receive Operation In receiving the SCI operates as follows 1 The SCI synchronizes with serial clock input or output and initializes internally 2 Receive data is shifted into RSR in order from the LSB to the MSB After receiving the data the SCI checks that RDRF is 0 so that receive data can be loaded from RSR into RDR If this check passes the SCI sets RDRF to 1...

Page 436: ...E to 0 The TXI interrupt can also be used to determine if the TDRE bit has changed from 0 to 1 3 Receive error handling if a receive error occurs read the ORER bit in SSR to identify the error After executing the necessary error handling clear ORER to 0 Transmitting receiving cannot resume if ORER remains set to 1 4 SCI status check and receive data read read the serial status register SSR check t...

Page 437: ...No Yes Yes No Read ORER bit in SSR Error handling 3 ORER 1 No Read RDRF bit in SSR 5 Yes 4 Read receive data in RDR and clear RDRF bit in SSR to 0 Clear TE and RE bits in SCR to 0 Note When switching from transmitting or receiving to simultaneous transmitting and receiving clear both the TE bit and the RE bit to 0 then set both this to 1 simultaneously Figure 13 20 Sample Flowchart for Serial Tran...

Page 438: ... in SSR is set to 1 TEI cannot start the DMAC A TXI interrupt indicates that transmit data writing is enabled A TEI interrupt indicates that the transmit operation is complete Table 13 12 SCI Interrupt Sources Interrupt Source Description DMAC Activation Priority ERI Receive error ORER PER or FER No High RXI Receive data full RDRF Yes TXI Transmit data empty TDRE Yes TEI Transmit end TEND No Low 1...

Page 439: ... by the data register DR of the I O port and the control register CR of the PFC This feature can be used to send a break signal The DR value substitutes for the mark state until the PFC setting is performed The DR bits should therefore be set as an output port that outputs 1 beforehand To send a break signal during serial transmission clear the DR bit to 0 and select output port as the TxD pin fun...

Page 440: ...eive margin in asynchronous mode can therefore be expressed as shown in equation 1 Equation 1 M 0 5 L 0 5 F 1 F 100 1 2N D 0 5 N M Receive margin N Ratio of clock frequency to bit rate N 16 D Clock duty cycle D 0 to 1 0 L Frame length L 9 to 12 F Absolute deviation of clock frequency From equation 1 if F 0 and D 0 5 the receive margin is 46 875 as given by equation 2 Equation 2 D 0 5 F 0 M 0 5 1 2...

Page 441: ...1 D2 D3 D4 D5 D6 D7 SCK TDRE t Note During external clock operation an error may occur if t is 4φ or less Figure 13 22 Example of Synchronous Transmitting with DMAC Cautions on Use of Synchronous External Clock Mode Set TE RE 1 only when the external clock SCI is 1 Do not set TE RE 1 until at least 4 clocks after the external clock SCK has changed from 0 to 1 When receiving RDRF is set to 1 when R...

Page 442: ...ion voltage range can be set with the analog reference power pin AVref as the analog reference voltage Rapid conversion time 6 7 µs per channel at 20 MHz Single mode or scan mode selectable Single mode One channel A D conversion Scan mode A D conversion repeated on one to four channels Four 16 bit data registers A D conversion results are transferred to and stored in the data registers correspondi...

Page 443: ... approxi mations register Comparator Sample and hold circuit ADI interrupt signal Vref AVSS AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 φ 8 φ 16 ADCSR ADCR AVCC A D converter Internal data bus ADTRG ADCR A D control register ADCSR A D control status register ADDRA A D data register A ADDRB A D data register B ADDRC A D data register C ADDRD A D data register D Figure 14 1 Block Diagram of A D Converter ...

Page 444: ... Table 14 1 Input Pins Pin Name Abbreviation I O Function Analog supply voltage AVCC I Power supply for the analog circuits Analog ground AVSS I Ground and reference voltage for the analog circuits Analog reference power supply AVref I Reference voltage for the analog circuits Analog input 0 AN0 I Analog input pins group 0 Analog input 1 AN1 I Analog input 2 AN2 I Analog input 3 AN3 I Analog input...

Page 445: ...27 A24 and A8 A0 are valid bits A23 A9 are ignored For details on the register addresses see section 8 3 5 Area Descriptions 2 Only 0 can be written in bit 7 to clear the flag 14 2 Register Descriptions 14 2 1 A D Data Registers A D ADDRA ADDRD The four A D data registers ADDRA ADDRD are 16 bit read only registers that store the results of the A D conversion Each result consists of 10 bits The fir...

Page 446: ...p 0 Group 1 A D Data Register AN0 AN4 ADDRA AN1 AN5 ADDRB AN2 AN6 ADDRC AN3 AN7 ADDRD 14 2 2 A D Control Status Register ADCSR The A D control status register ADCSR is an 8 bit read write register that controls the operation of the A D converter mode selection etc ADCSR is initialized to H 00 by a reset and in standby mode Bit 7 6 5 4 3 2 1 0 Bit name ADF ADIE ADST SCAN CKS CH2 CH1 CH0 Initial val...

Page 447: ...al value 1 The A D interrupt ADI request is enabled Bit 5 A D Start ADST ADST selects the start or halting of A D conversion Whenever the A D converter is operating this bit is set to 1 It can also be set to 1 by the A D conversion trigger input pin ADTRG Bit 5 ADST Description 0 A D conversion is halted Initial value 1 Single mode A D conversion is performed This bit is automatically cleared to 0...

Page 448: ...anged only when the ADST bit is cleared to 0 Group Select Channel Select Selected Channels CH2 CH1 CH0 Single Mode Scan Mode 0 0 0 AN0 AN0 Initial value 0 1 AN1 AN0 and AN1 1 0 AN2 AN0 AN2 1 1 AN3 AN0 AN3 1 0 0 AN4 AN4 0 1 AN5 AN4 and AN5 1 0 AN6 AN4 AN6 1 1 AN7 AN4 AN7 14 2 3 A D Control Register ADCR The A D control register ADCR is an 8 bit read write register that selects whether or not to sta...

Page 449: ...pper byte of each register can be read directly but the lower byte is accessed through an 8 bit temporary register TEMP When the CPU reads the upper byte of an A D data register the upper byte is transferred to the CPU and the lower byte to TEMP When the lower byte is accessed the value in TEMP is transferred to the CPU A program should first read the upper byte then the lower byte of the A D data...

Page 450: ...n A to D CPU receives data H AA Upper byte read Module internal data bus Bus interface TEMP H 40 ADDRn L H 40 ADDRn H H AA n A to D CPU receives data H 40 Lower byte read Module internal data bus Figure 14 2 Read Access to A D Data Register Reading H AA40 ...

Page 451: ... D conversion in order to prevent malfunctions Setting the ADST bit to 1 after changing the mode or channel starts A D conversion again changing the mode or channel and setting the ADST bit can be performed simultaneously The following is an example of the A D conversion process in single mode when channel 1 AN1 is selected See figure 14 3 for the timing 1 The program selects single mode SCAN 0 an...

Page 452: ...DDRC ADDRD Waiting Waiting Waiting Waiting Waiting Waiting A D conversion starts Set Set Set Clear Clear A D conversion result 1 A D conversion result 2 Read result Read result A D conversion 1 A D conversion result 2 Note Downward arrows indicate instruction execution Figure 14 3 A D Operation in Single Mode Channel 1 Selected ...

Page 453: ...etting the ADST bit can be performed simultaneously The following is an example of the A D conversion process in scan mode when three channels in group 0 are selected AN0 AN1 and AN2 See figure 14 4 for the timing 1 The program selects scan mode SCAN 1 scan group 0 CH2 0 and analog input channels AN0 AN2 CH1 1 CH2 CH0 0 then sets the ADST bit to 1 to start A D conversion 2 The A D converter sample...

Page 454: ...result 2 Waiting Waiting Waiting A D conversion result 4 A D conversion result 3 A D conversion 1 Waiting A D conversion result 1 Transfer A D conversion 5 A D conversion 3 A D conversion time A D conversion 4 Continuous A D conversion A D conversion 2 Notes 1 Downward arrow indicates instruction executed by software 2 Data being converted is ignored Figure 14 4 A D Operation in Scan Mode Channels...

Page 455: ...is to synchronize the ADCSR write time with the A D conversion process therefore the duration of tD is variable As a result the total conversion time varies within the ranges shown in table 14 4 In scan mode the ranges given in table 14 4 apply to the first conversion The duration of the second and subsequent conversion processes is fixed at 256 states CKS 0 or 128 states CKS 1 CK Write signal ADF...

Page 456: ... All other operations are the same as when the ADST bit is set to 1 regardless of whether the mode is single or scan For the timing see figure 14 6 A D conversion CK ADTRG External trigger signal ADST Figure 14 6 External Trigger Input Timing 14 5 Interrupts and DMA Transfer Requests The A D converter can generate an A D interrupt ADI request at the end of conversion The ADI request is enabled by ...

Page 457: ...e figure 14 7 item 1 Full scale error is the deviation between actual and ideal A D conversion characteristics when the digital output value changes from 1111111110 110 in the figure to the maximum 1111111111 111 in the figure figure 14 7 item 2 Quantization error is the intrinsic error of the A D converter and is expressed as 1 2 LSB figure 14 7 item 3 Nonlinearity error is the deviation between ...

Page 458: ...converter is not used set AVref VCC When the converter is neither in use nor in standby mode connect AVCC and AVref to the power voltage VCC 14 7 2 Handling of Analog Input Pins To prevent damage from voltage surges at the analog input pins AN0 AN7 connect an input protection circuit like the one shown in figure 14 8 The circuit shown also includes an RC filter to prevent errors due to noise This ...

Page 459: ...ADST to 1 in the A D control status register ADCSR or by asserting the _ADTRG pin port C pins begin functioning as analog input pins ANn When A D conversion ends the pins are switched back to the general port digital input function 2 Port C pins not used for A D conversion Pins not selected as AN pins by the channel select setting can be used in the following combinations as general port pins in b...

Page 460: ... PA14 I O port IRQ2 input INTC DACK1 output DMAC 68 3 73 3 A PA13 I O port IRQ1 input INTC TCLKB input ITU DREQ0 input DMAC 67 72 A PA12 I O port IRQ0 input INTC TCLKA input ITU DACK0 output DMAC 66 3 71 3 A PA11 I O port DPH I O D bus TIOCB1 I O ITU 65 70 A PA10 I O port DPL I O D bus TIOCA1 I O ITU 64 69 A PA9 I O port AH output BSC ADTRG input A D IRQOUT output INTC 63 68 A PA8 I O port BREQ in...

Page 461: ...OCXA4 output ITU TP6 output TPC 104 111 B PB5 I O port TIOCB4 I O ITU TP5 output TPC 103 110 B PB4 I O port TIOCA4 I O ITU TP4 output TPC 102 109 B PB3 I O port TIOCB3 I O ITU TP3 output TPC 101 108 B PB2 I O port TIOCA3 I O ITU TP2 output TPC 100 107 B PB1 I O port TIOCB2 I O ITU TP1 output TPC 98 105 B PB0 I O port TIOCA2 I O ITU TP0 output TPC 97 103 C PC7 input port AN7 input A D 95 2 101 2 C ...

Page 462: ...B control register 2 PBCR2 R W H 0000 H 5FFFFCE 8 16 32 Column address strobe pin control register CASCR R W H 5FFF H 5FFFFEE 8 16 32 Note Only the values of bits A27 A24 and A8 A0 are valid bits A23 A9 are ignored For details on the register addresses see section 8 3 5 Area Descriptions 15 3 Register Descriptions 15 3 1 Port A I O Register PAIOR The port A I O register PAIOR is a 16 bit read writ...

Page 463: ...s the function of the upper eight bits of port A PACR2 selects the function of the lower eight bits of port A PACR1 and PACR2 are initialized to H 3302 and H FF95 respectively by a power on reset but are not initialized by a manual reset or in standby mode or sleep mode PACR1 Bit 15 14 13 12 11 10 9 8 Bit name PA15 MD1 PA15 MD0 PA14 MD1 PA14 MD0 PA13 MD1 PA13 MD0 PA12 MD1 PA12 MD0 Initial value 0 ...

Page 464: ...put DACK1 Initial value Bits 11 and 10 PA13 Mode PA13MD1 and PA13MD0 PA13MD1 and PA13MD0 select the function of the PA13 IRQ1 DREQ0 TCLKB pin Bit 11 PA13MD1 Bit 10 PA13MD0 Function 0 0 Input output PA13 Initial value 1 Interrupt request input IRQ1 1 0 ITU timer clock input TCLKB 1 DMA transfer request input DREQ0 Bits 9 and 8 PA12 Mode PA12MD1 and PA12MD0 PA12MD1 and PA12MD0 select the function of...

Page 465: ... 0 Input output PA10 Initial value 1 Lower data bus parity input output DPL 1 0 ITU input capture output compare TIOCA1 1 Reserved Bits 3 and 2 PA9 Mode PA9MD1 and PA9MD0 PA9MD1 and PA9MD0 select the function of the PA9 AH IRQOUT ADTRG pin Bit 3 PA9MD1 Bit 2 PA9MD0 Function 0 0 Input output PA9 Initial value 1 Address hold output AH 1 0 A D conversion trigger input ADTRG 1 Interrupt request output...

Page 466: ...ction 0 Input output PA7 1 Bus request acknowledge output BACK Initial value Bit 13 Reserved This bit is always read as 1 The write value should always be 1 Bit 12 PA6 Mode PA6MD PA6MD selects the function of the PA6 RD pin Bit 12 PA6MD Function 0 Input output PA6 1 Read output RD Initial value Bit 11 Reserved This bit is always read as 1 The write value should always be 1 Bit 10 PA5 Mode PA5MD PA...

Page 467: ...There is no pull up when it functions as PA3 or CS7 Bit 7 PA3MD1 Bit 6 PA3MD0 Function 0 0 Input output PA3 1 Chip select output CS7 1 0 Wait state input WAIT Initial value 1 Reserved Bits 5 and 4 PA2 Mode PA2MD1 and PA2MD0 PA2MD1 and PA2MD0 select the function of the PA2 CS6 TIOCB0 pin Bit 5 PA2MD1 Bit 4 PA2MD0 Function 0 0 Input output PA2 1 Chip select output CS6 Initial value 1 0 ITU input cap...

Page 468: ...TIOCA2 TIOCB4 TIOCB3 and TIOCB2 and as serial clocks SCK1 SCK0 For other functions they are disabled For port B pin functions PB15 PB0 and TIOCA4 TIOCA3 TIOCA2 TIOCB4 TIOCB3 and TIOCB2 and SCK1 SCK0 a given pin in port B is an output pin if its corresponding PBIOR bit is set to 1 and an input pin if the bit is cleared to 0 PBIOR is initialized to H 0000 by a power on reset however it is not initia...

Page 469: ...itial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 Bit name PB11 MD1 PB11 MD0 PB10 MD1 PB10 MD0 PB9 MD1 PB9 MD0 PB8 MD1 PB8 MD0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bits 15 and 14 PB15 Mode PB15MD1 and PB15MD0 PB15MD1 and PB15MD0 select the function of the PB15 TP15 IRQ7 pin Bit 15 PB15MD1 Bit 14 PB15MD0 Function 0 0 Input output PB15 I...

Page 470: ...tion 0 0 Input output PB12 Initial value 1 Interrupt request input IRQ4 1 0 Serial clock input output SCK0 1 Timing pattern output TP12 Bits 7 and 6 PB11 Mode PB11MD1 and PB11MD0 PB11MD1 and PB11MD0 select the function of the PB11 TP11 TxD1 pin Bit 7 PB11MD1 Bit 6 PB11MD0 Function 0 0 Input output PB11 Initial value 1 Reserved 1 0 Transmit data output TxD1 1 Timing pattern output TP11 Bits 5 and 4...

Page 471: ...8MD0 select the function of the PB8 TP8 RxD0 pin Bit 1 PB8MD1 Bit 0 PB8MD0 Function 0 0 Input output PB8 Initial value 1 Reserved 1 0 Receive data input RxD0 1 Timing pattern output TP8 PBCR2 Bit 15 14 13 12 11 10 9 8 Bit name PB7MD1 PB7MD0 PB6MD1 PB6MD0 PB5MD1 PB5MD0 PB4MD1 PB4MD0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 Bit name PB3MD1 PB3MD0 PB2MD1 P...

Page 472: ...ut output PB6 Initial value 1 ITU timer clock input TCLKC 1 0 ITU output compare TOCXA4 1 Timing pattern output TP6 Bits 11 and 10 PB5 Mode PB5MD1 and PB5MD0 PB5MD1 and PB5MD0 select the function of the PB5 TP5 TIOCB4 pin Bit 11 PB5MD1 Bit 10 PB5MD0 Function 0 0 Input output PB5 Initial value 1 Reserved 1 0 ITU input capture output compare TIOCB4 1 Timing pattern output TP5 Bits 9 and 8 PB4 Mode P...

Page 473: ...t PB2 Initial value 1 Reserved 1 0 ITU input capture output compare TIOCA3 1 Timing pattern output TP2 Bits 3 and 2 PB1 Mode PB1MD1 and PB1MD0 PB1MD1 and PB1MD0 select the function of the PB1 TP1 TIOCB2 pin Bit 3 PB1MD1 Bit 2 PB1MD0 Function 0 0 Input output PB1 Initial value 1 Reserved 1 0 ITU input capture output compare TIOCB2 1 Timing pattern output TP1 Bits 1 and 0 PB0 Mode PB0MD1 and PB0MD0 ...

Page 474: ... 6 5 4 3 2 1 0 Bit name Initial value 1 1 1 1 1 1 1 1 R W Bits 15 and 14 CASH Mode CASHMD1 and CASHMD0 CASHMD1 and CASHMD0 select the function of the CS1 CASH pin Bit 15 CASHMD1 Bit 14 CASHMD0 Function 0 0 Reserved 1 Chip select output CS1 Initial value 1 0 Column address strobe output CASH 1 Reserved Bits 13 and 12 CASL Mode CASLMD1 and CASLMD0 CASLMD1 and CASLMD0 select the function of the CS3 C...

Page 475: ...440 ...

Page 476: ...the WAIT pin or not It is not pulled up when the pin is functioning as either PA3 or CS7 Port A PA15 Input output IRQ3 Input DREQ1 Input PA14 Input output IRQ2 Input DACK1 Output PA13 Input output IRQ1 Input DREQ0 Input TCLKB Input PA12 Input output IRQ0 Input DACK0 Output TCLKA Input PA11 Input output DPH Input output TIOCB1 Input output PA10 Input output DPL Input output TIOCA1 Input output PA9 ...

Page 477: ... read When a value is written to PADR that value can be written into PADR but it will not affect the pin status Table 16 2 shows port A data register read write operations PADR is initialized by a power on reset However PADR is not initialized by a manual reset or in standby mode or sleep mode Bit 15 14 13 12 11 10 9 8 Bit name PA15DR PA14DR PA13DR PA12DR PA11DR PA10DR PA9DR PA8DR Initial value 0 ...

Page 478: ...6 Output TOCXA4 Output TCLKC Input PB5 Input output TP5 Output TIOCB4 Input output PB4 Input output TP4 Output TIOCA4 Input output PB3 Input output TP3 Output TIOCB3 Input output PB2 Input output TP2 Output TIOCA3 Input output PB1 Input output TP1 Output TIOCB2 Input output PB0 Input output TP0 Output TIOCA2 Input output Figure 16 2 Port B Configuration 16 3 1 Register Configuration Table 16 3 sum...

Page 479: ...o PBDR Table 16 4 shows port B data register read write operations PBDR is initialized by a power on reset However PBDR is not initialized by a manual reset or in standby mode or sleep mode Bit 15 14 13 12 11 10 9 8 Bit name PB15DR PB14DR PB13DR PB12DR PB11DR PB10DR PB9DR PB8DR Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 Bit name PB7DR PB6DR PB5DR PB4DR PB...

Page 480: ...Input PC0 Input AN0 Input Figure 16 3 Port C Configuration 16 4 1 Register Configuration Table 16 5 summarizes the port C register Table 16 5 Port C Register Name Abbreviation R W Initial Value Address Access Size Port C data register PCDR R W H 5FFFFD0 8 16 32 Note Only the values of bits A27 A24 and A8 A0 are valid bits A23 A9 are ignored For details on the register addresses see section 8 3 5 A...

Page 481: ...owever every bit is read as 1 Table 16 6 shows port C data register read write operations bits 7 0 PCDR is not initialized by a power on reset or manual reset or in standby mode or sleep mode bits 15 8 are always undefined bits 7 0 always reflect the pin status Bit 15 14 13 12 11 10 9 8 Bit name Initial value R W R R R R R R R R Bit 7 6 5 4 3 2 1 0 Bit name PC7DR PC6DR PC5DR PC4DR PC3DR PC2DR PC1D...

Page 482: ...FE H 000FFFF On chip ROM Internal data bus 32 bits Note The addresses shown in the figure are the uppermost shadow addresses in the on chip ROM space Figure 17 1 Block Diagram of ROM The operating mode determines whether the on chip ROM is valid or not The operating mode is selected using mode setting pins MD0 MD2 as shown in table 17 1 When using the on chip ROM select mode 2 otherwise select mod...

Page 483: ...he pins as shown in figure 17 2 and use the chip in PROM mode 17 2 2 Socket Adapter Pin Correspondence and Memory Map Mount the socket adapter on the SH7034 as shown in figure 17 2 This allows the on chip PROM to be programmed in exactly the same way as ordinary 32 pin EPROMs HN27C101 Figure 17 2 shows the correspondence between SH7034 pins and HN27C101 pins Figure 17 3 shows the memory map of the...

Page 484: ...7 A18 VCC MD0 MD1 MD2 AVCC AVref RES VSS PC0 AN0 PC3 AN3 PC4 AN4 PC7 AN7 AVSS NC leave open Pin Number 1 26 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 24 23 25 4 28 29 3 2 32 16 Pin Name VPP A9 I O0 I O1 I O2 I O3 I O4 I O5 I O6 I O7 A0 A1 A2 A3 A4 A5 A6 A7 A8 OE A10 A11 A12 A13 A14 A15 A16 PGM CE VCC VSS 31 22 SH7034 HN27C101 EPROM Socket Adapter VPP PROM program power adapter 12 5 V A16 A0 Ad...

Page 485: ... same as for the standard EPROM HN27C101 Page programming is not supported so do not set the PROM programmer to page programming mode Naturally PROM programmers that only support page programming mode cannot be used When selecting a PROM programmer check that the byte by byte high speed high reliability programming method is supported 17 3 1 Selecting the Programming Mode There are two on chip PRO...

Page 486: ...0 1 1 1 Legend 0 Low 1 High VPP VPP level VCC VCC level 17 3 2 Write Verify and Electrical Characteristics Write Verify Write verify can be accomplished by an efficient high speed high reliability programming method This method can write data quickly and accurately without placing voltage stress on the device The basic flowchart for this high speed high reliability programming method is shown in f...

Page 487: ...esult OK No Yes Final address No Yes Set EPROM programmer to read mode VCC 5 0 V 0 25 V VPP VCC Results of reading all address OK No Yes End No good No VCC Power supply VPP PROM program power supply tPW Initial programming pulse width tOPW Overprogramming pulse width n 25 Yes Address 1 Address Figure 17 4 Basic Flowchart of High Speed High Reliability Programming ...

Page 488: ...Ta 25 5 C Item Pins Symbol Min Typ Max Unit Test Conditions Input high voltage I O7 I O0 A16 A0 OE CE PGM VIH 2 4 VCC 0 3 V Input low voltage I O7 I O0 A16 A0 OE CE PGM VIL 0 3 0 8 V Output high voltage I O7 I O0 VOH 2 4 V IOH 200 µA Output low voltage I O7 I O0 VOL 0 45 V IOL 1 6 mA Input leakage current I O7 I O0 A16 A0 OE CE PGM ILI 2 µA VIN 5 25 V 0 5 V VCC current ICC 40 mA VPP current IPP 40...

Page 489: ... tVPS 2 µs PGM pulse width in initial programming tPW 0 19 0 20 0 21 ms PGM pulse width in overprogramming tOPW 3 0 19 5 25 ms VCC setup time tVCS 2 µs CE setup time tCES 2 µs Data output delay time tOE 0 150 ns Notes 1 Input pulse level 0 45 2 4 V Input rise fall time 20 ns Input timing reference levels 0 8 V 2 0 V Output timing reference levels 0 8 V 2 0 V 2 tDF is defined at the point where the...

Page 490: ...programmer is set to the Hitachi specifications for HN27C101 VPP is 12 5 V Applying a voltage in excess of the rated voltage may damage the device Pay particular attention to overshoot in the EPROM programmer 2 Before programming always check that the index marks on the EPROM programmer socket socket adapter and device are aligned with each other If they are not correctly aligned an overcurrent ma...

Page 491: ...ability of data retention Letting it stand at a high temperature is a type of screening method that can eliminate of initial data retention defects of the on chip PROM s memory cells within a short period of time Figure 17 6 shows the flow from programming of the on chip PROM including screening to mounting on the device board Writing and verification of program Mount on board Flowchart from figur...

Page 492: ...p RAM in byte word or longword units The DMAC can access byte or word data On chip RAM data can always be accessed in one state making the RAM ideal for use as a program area stack area or data area which require high speed access The contents of the on chip RAM are held in both the sleep and standby modes Memory area 7 addresses H FFFE000 to H FFFFFFF are allocated to the on chip RAM in the SH703...

Page 493: ...the figure are the lowest shadow addresses in on chip RAM space Note Addresses in the figure are the lowest shadow addresses in on chip RAM space Figure 18 1 Block Diagram of RAM 18 2 Operation Accesses to addresses H FFFE000 H FFFFFFF SH7032 or addresses H FFFF000 H FFFFFFF SH7034 are directed to the on chip RAM Memory area 7 H F000000 H FFFFFFF is divided into shadows in 8 kbyte units for the SH...

Page 494: ...LEEP instruction with SBY bit set to 0 in SBYCR Runs Halted Run Held Held Held Interrupt DMA address error Power on reset Manual reset Standby mode Execute SLEEP instruction with SBY bit set to 1 in SBYCR Halted Halted Halted 1 Held Held Held or high Z 2 NMI interrupt Power on reset Manual reset SBYCR Standby control register SBY Standby bit Notes 1 Some of the registers of the on chip supporting ...

Page 495: ... to 1 while the timer enable bit bit TME in timer control status register TCSR of the watchdog timer WDT is set to 1 To enter standby mode clear the TME bit to 0 to halt the WDT and then set the SBY bit SBY Description 0 Executing SLEEP instruction puts the chip into sleep mode Initial value 1 Executing SLEEP instruction puts the chip into standby mode Bit 6 Port High Impedance HIZ HIZ selects whe...

Page 496: ... high sleep mode is exited and the power on reset state is entered If the NMI signal is brought from low to high in order to set the chip for a power on reset an NMI interrupt will occur whenever the rising edge of NMI is selected as the valid edge with NMI edge select bit NMIE in the interrupt control register ICR of the interrupt controller When this occurs the NMI interrupt clears sleep mode Ex...

Page 497: ...ct memory access controller DMAC All registers Watchdog timer WDT Bits 7 5 OVF WT IT TME in timer control status register TCSR Reset control status register RSTCSR Bits 2 0 CKS2 CKS0 in timer control status register TCSR Timer counter TCNT 16 bit integrated timer pulse unit ITU All registers Programmable timing pattern controller TPC All registers Serial communication interface SCI Receive data re...

Page 498: ...standby mode is entered clock halted and high when the chip returns from standby mode clock starts up after the oscillator is stabilized Exit by Power On Reset If the RES signal goes low while the NMI signal is high standby mode is exited and the power on reset state is entered If the NMI signal is brought from low to high in order to set the chip for a power on reset standby mode will not be exit...

Page 499: ...MIE SSBY Clock setting time NMI exception handling Exception handling routine SBY 1 SLEEP instruction Standby mode Oscillation start time Time set in WDT NMI exception handling Figure 19 1 NMI Timing for Standby Mode Example ...

Page 500: ...r 20 to 75 C Storage temperature Tstg 55 to 125 C Caution Operating the chip in excess of the absolute maximum rating may result in permanent damage Note Regular specification products for wide temperature range products Topr 40 to 85 C 20 1 2 DC Characteristics Table 20 2 lists DC characteristics Table 20 3 lists the permissible output current values Usage Conditions Do not release AVCC AVref and...

Page 501: ...nput low level voltage RES NMI MD2 MD0 VIL 0 3 0 5 V Other input pins 0 3 0 8 V Schmidt trigger VT 4 0 V input voltage VT 1 0 V VT VT 0 4 V Input leakage current RES Iin 1 0 µA Vin 0 5 to VCC 0 5 V NMI MD2 MD0 1 0 µA Vin 0 5 to VCC 0 5 V Port C 1 0 µA Vin 0 5 to AVCC 0 5 V 3 state leakage current off state Ports A and B CS3 CS0 A21 A0 AD15 AD0 ITSI 1 0 µA Vin 0 5 to VCC 0 5 V Input pull up MOS cur...

Page 502: ...ut pins 20 pF Current Ordinary ICC 60 90 mA f 12 5 MHz consumption operation 100 130 mA f 20 MHz Sleep 40 70 mA f 12 5 MHz 60 90 mA f 20 MHz Standby 0 01 5 1 µA Ta 50 C 20 0 2 µA 50 C Ta Analog power supply current During A D conversion AICC 1 0 2 mA While A D converter is waiting 0 01 5 µA Reference power supply During A D conversion AIref 0 5 1 mA AVref 5 0 V current While A D converter is waiti...

Page 503: ...Input low level voltage RES NMI MD2 MD0 VIL 0 3 VCC 0 1 V Other input pins 0 3 VCC 0 2 V Schmidt trigger VT VCC 0 9 V input voltage VT VCC 0 2 V VT VT VCC 0 07 V Input leakage current RES Iin 1 0 µA Vin 0 5 to VCC 0 5 V NMI MD2 MD0 1 0 µA Vin 0 5 to VCC 0 5 V Port C 1 0 µA Vin 0 5 to AVCC 0 5 V 3 state leakage current off state Ports A and B CS3 CS0 A21 A0 AD15 AD0 ITSI 1 0 µA Vin 0 5 to VCC 0 5 V...

Page 504: ... 20 pF Current consumption Ordinary operation ICC 60 90 mA f 12 5 MHz Sleep 40 70 mA f 12 5 MHz Standby 0 01 5 0 1 µA Ta 50 C 20 0 2 µA 50 C Ta Analog power During A D AICC 0 5 1 5 mA AVCC 3 0 V supply current conversion 1 0 2 0 mA AVCC 5 0 V While A D converter is waiting 0 01 5 0 µA During A D AIref 0 4 0 8 mA AVref 3 0 V conversion 0 5 1 mA AVref 5 0 V While A D converter is waiting 0 01 5 0 µA...

Page 505: ...ax 1 0 mA 1 29 mA MHz V VCC f ordinary operation ICC max 1 0 mA 1 00 mA MHz V VCC f sleep 4 When the A D converter is not used and in standby mode AVCC and AVref must still be connected to the power supply VCC 5 The ZTAT and mask versions have the same functions and the electrical characteristics of both are within specification but characteristic related performance values operating margins noise...

Page 506: ...on products for wide temperature range products Ta 40 to 85 C Case A Case B 12 5 MHz 20 MHz Item Symbol Min Typ Max Min Typ Max Unit Output low level permissible current per pin IOL 10 10 mA Output low level permissible current total IOL 80 80 mA Output high level permissible current per pin IOH 2 0 2 0 mA Output high level permissible current total IOH 25 25 mA Caution To ensure reliability of th...

Page 507: ...lar specification products for wide temperature range products Ta 40 to 85 C Case A Case B Sym 12 5 MHz 20 MHz Item bol Min Max Min Max Unit Figures EXTAL input high level pulse width tEXH 20 10 ns 20 1 EXTAL input low level pulse width tEXL 20 10 ns EXTAL input rise time tEXr 10 5 ns EXTAL input fall time tEXf 10 5 ns Clock cycle time tcyc 80 500 50 500 ns 20 1 20 2 Clock high pulse width tCH 30 ...

Page 508: ...473 tcyc tEXH EXTAL tEXL tEXf VIH VIL tEXr 1 2 VCC Figure 20 1 EXTAL Input Timing tCYC tCH tCr CK tCL tCf Figure 20 2 System Clock Timing tOSC2 tOSC1 CK VCC RES Figure 20 3 Oscillation Settling Time ...

Page 509: ...Min Max Unit Figure RES setup time tRESS 320 200 ns 20 4 RES pulse width tRESW 20 20 tcyc NMI reset setup time tNMIRS 320 200 ns NMI reset hold time tNMIRH 320 200 ns NMI setup time tNMIS 160 100 ns 20 5 NMI hold time tNMIH 80 50 ns IRQ0 IRQ7 setup time edge detection tIRQES 160 100 ns IRQ0 IRQ7 setup time level detection tIRQLS 160 100 ns IRQ0 IRQ7 hold time tIRQEH 80 50 ns IRQOUT output delay ti...

Page 510: ...RESS tNMIRS tRESW tNMIRH Figure 20 4 Reset Input Timing IRQ edge NMI tNMIS CK tNMIH tIRQES tIRQEH IRQ level tIRQLS Figure 20 5 Interrupt Signal Input Timing IRQOUT CK tIRQOD tIRQOD Figure 20 6 Interrupt Signal Output Timing ...

Page 511: ...476 tBRQS tBRQS tBACD1 tBZD tBZD tBACD2 CK BREQ Input BACK Output A21 A0 RD WR RAS CAS CSn Figure 20 7 Bus Release Timing ...

Page 512: ...0 ns 20 8 from read strobe 50 duty tcyc 0 5 20 ns Access time 2 6 from read strobe 35 duty 2 tRDAC2 tcyc n 1 65 20 3 ns 20 9 20 10 50 duty tcyc n 1 5 20 3 ns Access time 3 6 from read strobe 35 duty 2 tRDAC3 tcyc n 0 65 20 3 ns 20 19 50 duty tcyc n 0 5 20 3 ns Read strobe delay time tRSD 20 ns 20 8 20 9 20 11 20 15 20 19 Read data setup time tRDS 15 ns 20 8 20 9 20 11 20 14 Read data hold time tRD...

Page 513: ...ata access time 1 6 tACC1 tcyc 30 4 ns 20 8 20 11 20 12 Read data access time 2 6 tACC2 tcyc n 2 30 3 ns 20 9 20 10 20 13 20 15 RAS delay time 1 tRASD1 20 ns 20 11 20 14 RAS delay time 2 tRASD2 30 ns 20 16 20 18 CAS delay time 1 tCASD1 20 ns 20 11 CAS delay time 2 7 tCASD2 20 ns 20 13 20 14 CAS delay time 3 7 tCASD3 20 ns 20 16 20 18 Column address setup time tASC 0 ns 20 11 20 12 Read data access...

Page 514: ...tDACD5 20 ns Read delay time 35 duty 2 tRDD tcyc 0 35 12 ns 20 8 20 9 20 11 50 duty tcyc 0 5 15 ns 20 15 20 19 Data setup time for CAS tDS 0 5 ns 20 11 20 13 CAS setup time for RAS tCSR 10 ns 20 16 20 18 Row address hold time tRAH 10 ns 20 11 20 13 Write command hold time tWCH 15 ns Write command 35 duty 2 tWCS 0 ns 20 11 setup time 50 duty tWCS 0 ns Access time from CAS precharge 6 tACP tcyc 20 n...

Page 515: ...1 2 tRDS tRDH 3 tDACD1 tDACD2 tRDD Notes 1 For tRDAC1 use tcyc 0 65 20 for 35 duty or tcyc 0 5 20 for 50 duty instead of tcyc tRDD tRDS 2 For tACC1 use tcyc 30 instead of tcyc tAD or tCSD1 tRDS 3 tRDH is measured from A21 A0 CSn or RD whichever is negated first Figure 20 8 Basic Bus Cycle One State Access ...

Page 516: ...WRL WR Write AD15 AD0 DPH DPL Read AD15 AD0 Write DPH DPL Write DACK0 DACK1 Write tCSD1 Notes 1 For tRDAC2 use tcyc n 1 65 20 for 35 duty or tcyc n 1 5 20 for 50 duty instead of tcyc n 2 tRDD tRDS 2 For tACC2 use tcyc n 2 30 instead of tcyc n 2 tAD or tCSD1 tRDH 3 tRDH is measured from A21 A0 CSn or RD whichever is negated first Figure 20 9 Basic Bus Cycle Two State Access ...

Page 517: ...0 DPH DPL Write WRH WRL WR Write T1 TW T2 tWTS tWTH tWTS tWTH tRDAC2 1 tACC2 2 Notes 1 For tRDAC2 use tcyc n 1 65 20 for 35 duty or tcyc n 1 5 20 for 50 duty instead of tcyc n 2 tRDD tRDS 2 For tACC2 use tcyc n 2 30 instead of tcyc n 2 tAD or tCSD1 tRDS Figure 20 10 Basic Bus Cycle Two States Wait State ...

Page 518: ...tDACD4 tDACD5 tACC1 2 tRAH tDACD2 tWSD4 tWCH tASC tDS Row Column tWCS tRAC1 3 RD Write RD Read tRSD tRDD Notes 1 For tCAC1 use tcyc 0 65 19 for 35 duty or tcyc 0 5 19 for 50 duty instead of tcyc tAD tASC tRDS 2 For tACC1 use tcyc 30 instead of tcyc tAD tRDS 3 For tRAC1 use tcyc 1 5 20 instead of tcyc 1 5 tRASD1 tRDS 4 tRDH is measured from A21 A0 RAS or CAS whichever is negated first Figure 20 11 ...

Page 519: ... is not necessary to meet the tRDS specification as long as the tCAC1 specification is met 2 For tACC1 use tcyc 30 instead of tcyc tAD tRDS It is not necessary to meet the tRDS specification as long as the tACC1 specification is met 3 For tRAC1 use tcyc 1 5 20 instead of tcyc 1 5 tRASD1 tRDS It is not necessary to meet the tRDS specification as long as the tRAC1 specification is met 4 tRDH is meas...

Page 520: ...D Tp Tr Tc Silent cycle Tc tAD tRASD1 tRASD2 tASC tDACD4 tDACD5 tDACD5 RD Write tWSD4 tWSD3 tWDD2 tWDH tWPDD2 tWPDH Column address Column address Row address Figure 20 12 b DRAM Bus Cycle Short Pitch High Speed Page Mode Write Note For details of the silent cycle see section 8 5 5 DRAM Burst Mode ...

Page 521: ...1 tWSD2 tWDD1 tWDH tWPDH tWPDD1 tDACD3 tDACD3 tRAC2 3 tDS tCASD2 tWCH tCAC2 1 RD Write RD Read tRDD tRSD Row tRAH tRDS Notes 1 For tCAC2 use tcyc n 1 25 instead of tcyc n 1 tCASD2 tRDS 2 For tACC2 use tcyc n 2 30 instead of tcyc n 2 tAD tRDS 3 For tRAC2 use tcyc n 2 5 20 instead of tcyc n 2 5 tRASD1 tRDS 4 tRDH is measured from A21 A0 CAS or RAS whichever is negated first Figure 20 13 DRAM Bus Cyc...

Page 522: ... tWDD1 tWDH tWDD1 tWDH tWPDD1 tWPDD1 tWPDH tWPDH tDACD3 tDACD3 tDACD3 tDACD3 Column Column RD Write RD Read tRDD tRSD Row Notes 1 For tCAC2 use tcyc n 1 25 instead of tcyc n 1 tCASD2 tRDS 2 For tACC2 use tcyc n 2 30 instead of tcyc n 2 tAD tRDS 3 For tRAC2 use tcyc n 2 5 20 instead of tcyc n 2 5 tRASD2 tRDS 4 tRDH is measured from A21 A0 or CAS whichever is negated first 5 tRDH is measured from A2...

Page 523: ...r Tc1 Tw Tc2 Row Column tWTS tWTH tWTS tWTH tACC2 2 tRAC2 3 tCAC2 1 RD Write RD Read tRSD tRDD Notes 1 For tCAC2 use tcyc n 1 25 instead of tcyc n 1 tCASD2 tRDS 2 For tACC2 use tcyc n 2 30 instead of tcyc n 2 tAD tRDS 3 For tRAC2 use tcyc n 2 5 20 instead of tcyc n 2 5 tRASD1 tRDS Figure 20 15 DRAM Bus Cycle Long Pitch High Speed Page Mode Wait State ...

Page 524: ...H WRL WR TRp TRr TRc tRASD1 tRASD2 tCASD3 tCASD2 tCSR Figure 20 16 CAS before RAS Refresh Short Pitch CK RAS CAS WRH WRL WR TRp TRc TRc tRASD1 tRASD2 tCASD3 tCASD2 TRr tCSR Figure 20 17 CAS before RAS Refresh Long Pitch ...

Page 525: ...490 CK RAS CAS TRp TRc TRcc tRASD1 tRASD2 tCASD3 tCASD2 TRr tCSR Figure 20 18 Self Refresh ...

Page 526: ...WR Write AD15 AD0 Write DACK0 DACK1 Write WAIT T1 T2 T3 T4 tCSD4 tCSD3 tAD tAHD1 tAHD2 tRSD tRDH tMAH tMAD tRDAC3 tDACD2 tDACD1 tWSD1 tWSD2 tMAD tMAH tWDD1 tDACD3 tDACD3 tWTH tWTS Address Address Data output tRDD tWDH Data input Figure 20 19 Address Data Multiplex I O Bus Cycle ...

Page 527: ...492 CK A21 A0 HBS LBS CSn DACK0 DACK1 Write WRH WRL WR Write T1 tAD tCSD1 tCSD2 tWSD4 tDACD1 tDACD2 tWSD1 Figure 20 20 DMA Single Transfer One State Access Write ...

Page 528: ...duty tcyc n 1 5 35 2 ns Access time 3 4 35 duty 1 tRDAC3 tcyc n 0 65 35 2 ns 20 32 from read strobe 50 duty tcyc n 0 5 35 2 ns Read strobe delay time tRSD 40 ns 20 21 20 22 20 24 20 28 20 32 Read data setup time tRDS 25 ns 20 21 20 22 Read data hold time tRDH 0 ns 20 24 20 27 20 32 Write strobe delay time 1 tWSD1 40 ns 20 22 20 26 20 27 20 32 20 33 Write strobe delay time 2 tWSD2 30 ns 20 22 20 26...

Page 529: ... 29 RAS delay time 2 tRASD2 40 ns 20 31 CAS delay time 1 tCASD1 40 ns 20 24 CAS delay time 2 5 tCASD2 40 ns 20 26 20 27 20 29 CAS delay time 3 5 tCASD3 40 ns 20 31 Column address setup time tASC 0 ns 20 24 20 25 Read data 35 duty 1 tCAC1 tcyc 0 65 35 ns access time from CAS 1 4 50 duty tcyc 0 5 35 ns Read data access time from CAS 2 4 tCAC2 tcyc n 1 35 2 ns 20 26 20 28 Read data access time from R...

Page 530: ...time 35 duty 1 tRDD tcyc 0 35 35 ns 20 21 20 22 20 24 50 duty tcyc 0 5 35 ns 20 28 20 32 Data setup time for CAS tDS 0 3 ns 20 24 20 26 CAS setup time for RAS tCSR 10 ns 20 29 20 31 Row address hold time tRAH 10 ns 20 24 20 26 Write command hold time tWCH 15 ns Write command 35 duty 1 tWCS 0 ns 20 24 setup time 50 duty tWCS 0 ns Access time from CAS precharge 4 tACP tcyc 20 ns 20 25 Notes 1 When f...

Page 531: ...1 2 tRDS tRDH 3 tDACD1 tDACD2 tRDD Notes 1 For tRDAC1 use tcyc 0 65 35 for 35 duty or tcyc 0 5 35 for 50 duty instead of tcyc tRDD tRDS 2 For tACC1 use tcyc 44 instead of tcyc tAD or tCSD1 tRDS 3 tRDH is measured from A21 A0 CSn or RD whichever is negated first Figure 20 21 Basic Bus Cycle One State Access ...

Page 532: ...L WR Write AD15 AD0 DPH DPL Read AD15 AD0 Write DPH DPL Write DACK0 DACK1 Write tCSD1 Notes 1 For tRDAC2 use tcyc n 1 65 35 for 35 duty or tcyc n 1 5 35 for 50 duty instead of tcyc n 2 tRDD tRDS 2 For tACC2 use tcyc n 2 44 instead of tcyc n 2 tAD or tCSD1 tRDS480 3 tRDH is measured from A21 A0 CSn or RD whichever is negated first Figure 20 22 Basic Bus Cycle Two State Access ...

Page 533: ...0 DPH DPL Write WRH WRL WR Write T1 TW T2 tWTS tWTH tWTS tWTH tRDAC2 1 tACC2 2 Notes 1 For tRDAC2 use tcyc n 1 65 35 for 35 duty or tcyc n 1 5 35 for 50 duty instead of tcyc n 2 tRDD tRDS 2 For tACC2 use tcyc n 2 44 instead of tcyc n 2 tAD or tCSD1 tRDS Figure 20 23 Basic Bus Cycle Two States Wait State ...

Page 534: ...D2 tWPDH tDACD4 tDACD5 tACC1 2 tRAH tWCS Row Column tASC tDS tDACD2 tRDS RD Write RD Read tRSD tRDD tWCH Notes 1 For tCAC1 use tcyc 0 65 35 for 35 duty or tcyc 0 5 35 for 50 duty instead of tcyc tAD tASC tRDS 2 For tACC1 use tcyc 44 instead of tcyc tAD tRDS 3 For tRAC1 use tcyc 1 5 35 instead of tcyc 1 5 tRASD1 tRDS 4 tRDH is measured from A21 A0 RAS or CAS whichever is negated first Figure 20 24 ...

Page 535: ...is not necessary to meet the tRDS specification as long as the tCAC1 specification is met 2 For tACC1 use tcyc 44 instead of tcyc tAD tRDS It is not necessary to meet the tRDS specification as long as the tACC1 specification is met 3 For tRAC1 use tcyc 1 5 35 instead of tcyc 1 5 tRASD1 tRDS It is not necessary to meet the tRDS specification as long as the tRAC1 specification is met 4 tRDH is measu...

Page 536: ...D Tp Tr Tc Silent cycle Tc tAD tRASD1 tRASD2 tASC tDACD4 tDACD5 tDACD5 Row address Column address Column address RD Write tWSD4 tWSD3 tWDD2 tWDH tWPDD2 tWPDH Figure 20 25 b DRAM Bus Cycle Short Pitch High Speed Page Mode Write Note For details of the silent cycle see section 8 5 5 DRAM Burst Mode ...

Page 537: ...WSD2 tWDD1 tWDH tWPDH tWPDD1 tDACD3 tDACD3 tRAH tACC2 2 tRAC2 3 tCASD2 tDS tCAC2 1 tWCH RD Write RD Read tRDD tRSD Row Notes 1 For tCAC2 use tcyc n 1 35 instead of tcyc n 1 tCASD2 tRDS 2 For tACC2 use tcyc n 2 44 instead of tcyc n 2 tAD tRDS 3 For tRAC2 use tcyc n 2 5 35 instead of tcyc n 2 5 tRASD1 tRDS 4 tRDH is measured from A21 A0 CAS or RAS whichever is negated first Figure 20 26 DRAM Bus Cyc...

Page 538: ...tWDH tWDD1 tWDH tWPDD1 tWPDD1 tWPDH tWPDH tDACD3 tDACD3 tDACD3 tDACD3 Column Column RD Write RD Read tRDD tRASD1 Row tRSD Notes 1 For tCAC2 use tcyc n 1 35 instead of tcyc n 1 tCASD2 tRDS 2 For tACC2 use tcyc n 2 44 instead of tcyc n 2 tAD tRDS 3 For tRAC2 use tcyc n 2 5 35 instead of tcyc n 2 5 tRASD2 tRDS 4 tRDH is measured from A21 A0 or CAS whichever is negated first 5 tRDH is measured from A2...

Page 539: ...r Tc1 Tw Tc2 Row Column tWTS tWTH tWTS tWTH tRAC2 3 tACC2 2 tCAC2 1 RD Write RD Read tRSD tRDD Notes 1 For tCAC2 use tcyc n 1 35 instead of tcyc n 1 tCASD2 tRDS 2 For tACC2 use tcyc n 2 44 instead of tcyc n 2 tAD tRDS 3 For tRAC2 use tcyc n 2 5 35 instead of tcyc n 2 5 tRASD1 tRDS Figure 20 28 DRAM Bus Cycle Long Pitch High Speed Page Mode Wait State ...

Page 540: ...ASD2 tCSR Figure 20 29 CAS before RAS Refresh Short Pitch CK RAS CAS WRH WRL WR TRp TRc TRc tRASD1 tRASD2 tCASD3 tCASD2 TRr tCSR Figure 20 30 CAS before RAS Refresh Long Pitch CK RAS CAS TRp TRc TRcc tRASD1 tCASD3 tCASD2 TRr tCSR tRASD2 Figure 20 31 Self Refresh ...

Page 541: ...WR Write AD15 AD0 Write DACK0 DACK1 Write WAIT T1 T2 T3 T4 tCSD4 tCSD3 tAD tAHD1 tAHD2 tRSD tRDH tMAH tMAD tRDAC3 tDACD2 tDACD1 tWSD1 tWSD2 tMAD tMAH tWDD1 tDACD3 tDACD3 tWTH tWTS Address Address Data output tRDD tWDH Data input Figure 20 32 Address Data Multiplex I O Bus Cycle ...

Page 542: ... V AVCC VCC 10 AVref 3 0 V to AVCC VSS AVSS 0 V Ta 20 to 75 C Case B VCC 5 0 V 10 AVCC 5 0 V 10 AVCC VCC 10 AVref 4 5 V to AVCC VSS AVSS 0 V Ta 20 to 75 C Note Regular specification products for wide temperature range products Ta 40 to 85 C Case A Case B 12 5 MHz 20 MHz Item Symbol Min Max Min Max Unit Figure DREQ0 DREQ1 setup time tDRQS 80 27 ns 20 34 DREQ0 DREQ1 hold time tDRQH 30 30 ns DREQ0 DR...

Page 543: ...508 tDRQS tDRQS CK DREQ0 DREQ1 level DREQ0 DREQ1 edge tDRQS tDRQH DREQ0 DREQ1 level release Figure 20 34 DREQ0 DREQ1 Input Timing 1 CK tDRQW DREQ0 DREQ1 edge Figure 20 35 DREQ0 DREQ1 Input Timing 2 ...

Page 544: ... wide temperature range products Ta 40 to 85 C Case A Case B 12 5 MHz 20 MHz Item Symbol Min Max Min Max Unit Figure Output compare delay time tTOCD 100 100 ns 20 36 Input capture setup time tTICS 50 35 ns Timer clock input setup time tTCKS 50 50 ns 20 37 Timer clock pulse width single edge tTCKWH L 1 5 1 5 tcyc Timer clock pulse width both edges tTCKWL L 2 5 2 5 tcyc tTOCD CK tTICS Output compare...

Page 545: ...5 5 V AVCC 3 0 to 5 5 V AVCC VCC 10 AVref 3 0 V to AVCC VSS AVSS 0 V φ 12 5 MHz Ta 20 to 75 C Case B VCC 5 0 V 10 AVCC 5 0 V 10 AVCC VCC 10 AVref 4 5 V to AVCC VSS AVSS 0 V φ 20 MHz Ta 20 to 75 C Note Regular specification products for wide temperature range products Ta 40 to 85 C Cases A and B Item Symbol Min Max Unit Figure Port output delay time tPWD 100 ns 20 38 Port input hold time tPRH 50 ns...

Page 546: ...3 0 to 5 5 V AVCC VCC 10 AVref 3 0 V to AVCC VSS AVSS 0 V φ 12 5 MHz Ta 20 to 75 C Case B VCC 5 0 V 10 AVCC 5 0 V 10 AVCC VCC 10 AVref 4 5 V to AVCC VSS AVSS 0 V φ 20 MHz Ta 20 to 75 C Note Regular specification products for wide temperature range products Ta 40 to 85 C Cases A and B Item Symbol Min Max Unit Figure WDTOVF delay time tWOVD 100 ns 20 39 tWOVD CK tWOVD WDTOVF Figure 20 39 Watchdog Ti...

Page 547: ...roducts for wide temperature range products Ta 40 to 85 C Cases A and B Item Symbol Min Max Unit Figure Input clock cycle tscyc 4 tcyc 20 40 Input clock cycle synchronous mode tscyc 6 tcyc Input clock pulse width tsckw 0 4 0 6 tscyc Input clock rise time tsckr 1 5 tcyc Input clock fall time tsckf 1 5 tcyc Transmit data delay time synchronous mode tTXD 100 ns 20 41 Receive data setup time synchrono...

Page 548: ... AVCC 5 0 V 10 AVCC VCC 10 AVref 4 5 V to AVCC VSS AVSS 0 V φ 20 MHz Ta 20 to 75 C Note Regular specification products for wide temperature range products Ta 40 to 85 C Cases A and B Item Symbol Min typ Max Unit Figure External trigger input pulse width tTRGW 2 0 tcyc 20 42 External trigger input start delay time tTRGS 50 ns A D conversion start delay time CKS 0 tD 10 17 tcyc 20 43 CKS 1 6 9 tcyc ...

Page 549: ...K 1 state tTRGS tTRGW tTRGW ADTRG input ADST Figure 20 42 External Trigger Input Timing tSPL Max 14 states tD 3 states tCONV CK Address Analog input sampling signal ADF Figure 20 43 Analog Conversion Timing ...

Page 550: ...pin 30pF CK CASH CASL CS0 CS7 BREQ BACK AH IRQOUT RAS DACK0 DACK1 50pF A21 A0 AD15 AD0 DPH DPL RD WRH WRL HBS LBS WR 70pF All port outputs and supporting module output pins other than the above IOL and IOH values are as shown in section 20 1 2 DC Characteristics and table 20 3 Permitted Output Current Values Figure 20 44 Output Load Circuit ...

Page 551: ... 3 kΩ Nonlinearity error 3 3 LSB Offset error 3 3 LSB Full scale error 3 3 LSB Quantization error 0 5 0 5 LSB Absolute accuracy 4 4 LSB Table 20 14 A D Converter Characteristics cont Conditions VCC 3 0 to 5 5 V AVCC 3 0 to 5 5 V AVCC VCC 10 AVref 3 0 V to AVCC VSS AVSS 0 V Ta 20 to 75 C Note Regular specification products for wide temperature range products Ta 40 to 85 C 12 5 MHz Item Min Typ Max ...

Page 552: ...to 125 C Caution Operating the chip in excess of the absolute maximum rating may result in permanent damage Notes 1 ROMless products only for 20 MHz version 2 Regular specification products for wide temperature range products Topr 40 to 85 C 20 2 2 DC Characteristics Table 20 16 lists DC characteristics Table 20 18 lists the permissible output current values Usage Conditions Do not release AVCC AV...

Page 553: ...0 3 V Input low level voltage Other Schmidt trigger input pins VIL 0 3 VCC 0 2 V Schmidt trigger VT VCC 0 9 V input voltage VT VCC 0 1 V VT VT VCC 0 07 V Input leakage current RES Iin 1 0 µA Vin 0 5 to VCC 0 5 V NMI MD2 MD0 1 0 µA Vin 0 5 to VCC 0 5 V Port C 1 0 µA Vin 0 5 to AVCC 0 5 V 3 state leakage current off state Ports A and B CS3 CS0 A21 A0 AD15 AD0 ITSI 1 0 µA Vin 0 5 to VCC 0 5 V Input p...

Page 554: ...mbol Min Typ Max Unit Test Conditions Input RES Cin 30 pF capacitance NMI 30 pF All other input pins 20 pF Current Ordinary ICC 25 mA f 12 5 MHz consumption operation 35 60 mA f 20 MHz Sleep 20 mA f 12 5 MHz 30 40 mA f 20 MHz Standby 0 1 5 µA Ta 50 C 10 µA 50 C Ta Analog power supply current Ordinary operation Sleep AICC 0 5 1 mA Standby 0 1 5 µA Reference power supply current Ordinary operation S...

Page 555: ... output pins unloaded and the on chip pull up transistors in the off state 3 When the A D converter is not used and in standby mode AVCC and AVref must still be connected to the power supply VCC 4 The Characteristic related performance values operating margins noise margins noise emissions etc of this LSI are different from HD6417034A etc Caution is therefore required in carrying out system design...

Page 556: ... products Ta 40 to 85 C 12 5 MHz 20 MHz Item Symbol Min Typ Max Min Typ Max Unit Output low level permissible current per pin IOL 10 10 mA Output low level permissible current total IOL 80 80 mA Output high level permissible current per pin IOH 2 0 2 0 mA Output high level permissible current total IOH 25 25 mA Caution To ensure reliability of the chip do not exceed the output current values given...

Page 557: ...erature range products Ta 40 to 85 C 12 5 MHz 20 MHz Item Symbol Min Max Min Max Unit Figures EXTAL input high level pulse width tEXH 22 15 ns 20 45 EXTAL input low level pulse width tEXL 22 15 ns EXTAL input rise time tEXr 10 5 ns EXTAL input fall time tEXf 10 5 ns Clock cycle time tcyc 80 500 50 250 ns 20 45 20 46 Clock high pulse width tCH 30 20 ns 20 46 Clock low pulse width tCL 30 20 ns Clock...

Page 558: ...523 tcyc tEXH EXTAL tEXL tEXf VIH VIL tEXr 1 2 VCC Figure 20 45 EXTAL Input Timing tCYC tCH tCr CK tCL tCf Figure 20 46 System Clock Timing tOSC2 tOSC1 CK VCC RES Figure 20 47 Oscillation Settling Time ...

Page 559: ... 48 RES pulse width tRESW 20 20 tcyc NMI reset setup time tNMIRS 320 200 ns NMI reset hold time tNMIRH 320 200 ns NMI setup time tNMIS 160 100 ns 20 49 NMI hold time tNMIH 80 50 ns IRQ0 IRQ7 setup time edge detection tIRQES 160 100 ns IRQ0 IRQ7 setup time level detection tIRQLS 160 100 ns IRQ0 IRQ7 hold time tIRQEH 80 50 ns IRQOUT output delay time tIRQOD 80 50 ns 20 50 Bus request setup time tBRQ...

Page 560: ...ESS tNMIRS tRESW tNMIRH Figure 20 48 Reset Input Timing IRQ edge NMI tNMIS CK tNMIH tIRQES tIRQEH IRQ level tIRQLS Figure 20 49 Interrupt Signal Input Timing IRQOUT CK tIRQOD tIRQOD Figure 20 50 Interrupt Signal Output Timing ...

Page 561: ...526 tBRQS tBRQS tBACD1 tBZD tBZD tBACD2 CK BREQ Input BACK Output A21 A0 RD WR RAS CAS CSn Figure 20 51 Bus Release Timing ...

Page 562: ...time 4 tCSD4 25 ns Access time 1 6 35 duty 2 tRDAC1 tcyc 0 65 20 ns 20 52 from read strobe 50 duty tcyc 0 5 20 ns Access time 2 6 from read strobe 35 duty 2 tRDAC2 tcyc n 1 65 20 3 ns 20 53 20 54 50 duty tcyc n 1 5 20 3 ns Access time 3 6 from read strobe 35 duty 2 tRDAC3 tcyc n 0 65 20 3 ns 20 63 50 duty tcyc n 0 5 20 3 ns Read strobe delay time tRSD 20 ns 20 52 20 53 20 55 20 59 20 63 Read data ...

Page 563: ...etup time tWTS 10 ns 20 54 20 59 20 63 Wait hold time tWTH 6 ns Read data access time 1 6 tACC1 tcyc 30 4 ns 20 52 20 55 20 56 Read data access time 2 6 tACC2 tcyc n 2 30 3 ns 20 53 20 54 20 57 20 59 RAS delay time 1 tRASD1 20 ns 20 55 20 58 RAS delay time 2 tRASD2 30 ns 20 60 20 62 CAS delay time 1 tCASD1 20 ns 20 55 CAS delay time 2 7 tCASD2 20 ns 20 57 20 58 CAS delay time 3 7 tCASD3 20 ns 20 6...

Page 564: ...CK1 delay time 5 tDACD5 20 ns Read delay time 35 duty 2 tRDD tcyc 0 35 12 ns 20 52 20 53 20 55 50 duty tcyc 0 5 15 ns 20 59 20 63 Data setup time for CAS tDS 0 5 ns 20 55 20 57 CAS setup time for RAS tCSR 10 ns 20 60 20 62 Row address hold time tRAH 10 ns 20 55 20 57 Write command hold time tWCH 15 ns Write command 35 duty 2 tWCS 0 ns 20 55 setup time 50 duty tWCS 0 ns Access time from CAS prechar...

Page 565: ...5 duty 1 tRDAC1 tcyc 0 65 35 ns 20 52 from read strobe 50 duty tcyc 0 5 35 ns Access time 2 4 from read strobe 35 duty 1 tRDAC2 tcyc n 1 65 35 2 ns 20 53 20 54 50 duty tcyc n 1 5 35 2 ns Access time 3 4 from read strobe 35 duty 1 tRDAC3 tcyc n 0 65 35 2 ns 20 63 50 duty tcyc n 0 5 35 2 ns Read strobe delay time tRSD 40 ns 20 52 20 53 20 55 20 59 20 63 Read data setup time tRDS 25 ns 20 52 20 53 20...

Page 566: ...me tWTS 40 ns 20 54 20 59 20 63 Wait hold time tWTH 10 ns Read data access time 1 4 tACC1 tcyc 44 ns 20 52 20 55 20 56 Read data access time 2 4 tACC2 tcyc n 2 44 2 ns 20 53 20 54 20 57 20 59 RAS delay time 1 tRASD1 40 ns 20 55 20 58 RAS delay time 2 tRASD2 40 ns 20 60 20 62 CAS delay time 1 tCASD1 40 ns 20 55 CAS delay time 2 5 tCASD2 40 ns 20 57 20 58 CAS delay time 3 5 tCASD3 40 ns 20 60 20 62 ...

Page 567: ... 63 DACK0 DACK1 delay time 4 tDACD4 40 ns 20 55 20 56 DACK0 DACK1 delay time 5 tDACD5 40 ns Read delay time 35 duty 1 tRDD tcyc 0 35 35 ns 20 52 20 53 20 55 50 duty tcyc 0 5 35 ns 20 59 20 63 Data setup time for CAS tDS 0 3 ns 20 55 20 57 CAS setup time for RAS tCSR 10 ns 20 60 20 62 Row address hold time tRAH 10 ns 20 55 20 57 Write command hold time tWCH 15 ns Write command 35 duty 1 tWCS 0 ns 2...

Page 568: ...1 2 tRDS tRDH 3 tDACD1 tDACD2 tRDD Notes 1 For tRDAC1 use tcyc 0 65 20 for 35 duty or tcyc 0 5 20 for 50 duty instead of tcyc tRDD tRDS 2 For tACC1 use tcyc 30 instead of tcyc tAD or tCSD1 tRDS 3 tRDH is measured from A21 A0 CSn or RD whichever is negated first Figure 20 52 Basic Bus Cycle One State Access ...

Page 569: ...WRL WR Write AD15 AD0 DPH DPL Read AD15 AD0 Write DPH DPL Write DACK0 DACK1 Write tCSD1 Notes 1 For tRDAC2 use tcyc n 1 65 20 for 35 duty or tcyc n 1 5 20 for 50 duty instead of tcyc n 2 tRDD tRDS 2 For tACC2 use tcyc n 2 30 instead of tcyc n 2 tAD or tCSD1 tRDH 3 tRDH is measured from A21 A0 CSn or RD whichever is negated first Figure 20 53 Basic Bus Cycle Two State Access ...

Page 570: ...0 DPH DPL Write WRH WRL WR Write T1 TW T2 tWTS tWTH tWTS tWTH tRDAC2 1 tACC2 2 Notes 1 For tRDAC2 use tcyc n 1 65 20 for 35 duty or tcyc n 1 5 20 for 50 duty instead of tcyc n 2 tRDD tRDS 2 For tACC2 use tcyc n 2 30 instead of tcyc n 2 tAD or tCSD1 tRDS Figure 20 54 Basic Bus Cycle Two States Wait State ...

Page 571: ...tDACD4 tDACD5 tACC1 2 tRAH tDACD2 tWSD4 tWCH tASC tDS Row Column tWCS tRAC1 3 RD Write RD Read tRSD tRDD Notes 1 For tCAC1 use tcyc 0 65 19 for 35 duty or tcyc 0 5 19 for 50 duty instead of tcyc tAD tASC tRDS 2 For tACC1 use tcyc 30 instead of tcyc tAD tRDS 3 For tRAC1 use tcyc 1 5 20 instead of tcyc 1 5 tRASD1 tRDS 4 tRDH is measured from A21 A0 RAS or CAS whichever is negated first Figure 20 55 ...

Page 572: ... is not necessary to meet the tRDS specification as long as the tCAC1 specification is met 2 For tACC1 use tcyc 30 instead of tcyc tAD tRDS It is not necessary to meet the tRDS specification as long as the tACC1 specification is met 3 For tRAC1 use tcyc 1 5 20 instead of tcyc 1 5 tRASD1 tRDS It is not necessary to meet the tRDS specification as long as the tRAC1 specification is met 4 tRDH is meas...

Page 573: ...D Tp Tr Tc Silent cycle Tc tAD tRASD1 tRASD2 tASC tDACD4 tDACD5 tDACD5 RD Write tWSD4 tWSD3 tWDD2 tWDH tWPDD2 tWPDH Column address Column address Row address Figure 20 56 b DRAM Bus Cycle Short Pitch High Speed Page Mode Write Note For details of the silent cycle see section 8 5 5 DRAM Burst Mode ...

Page 574: ...1 tWSD2 tWDD1 tWDH tWPDH tWPDD1 tDACD3 tDACD3 tRAC2 3 tDS tCASD2 tWCH tCAC2 1 RD Write RD Read tRDD tRSD Row tRAH tRDS Notes 1 For tCAC2 use tcyc n 1 25 instead of tcyc n 1 tCASD2 tRDS 2 For tACC2 use tcyc n 2 30 instead of tcyc n 2 tAD tRDS 3 For tRAC2 use tcyc n 2 5 20 instead of tcyc n 2 5 tRASD1 tRDS 4 tRDH is measured from A21 A0 CAS or RAS whichever is negated first Figure 20 57 DRAM Bus Cyc...

Page 575: ... tWDD1 tWDH tWDD1 tWDH tWPDD1 tWPDD1 tWPDH tWPDH tDACD3 tDACD3 tDACD3 tDACD3 Column Column RD Write RD Read tRDD tRSD Row Notes 1 For tCAC2 use tcyc n 1 25 instead of tcyc n 1 tCASD2 tRDS 2 For tACC2 use tcyc n 2 30 instead of tcyc n 2 tAD tRDS 3 For tRAC2 use tcyc n 2 5 20 instead of tcyc n 2 5 tRASD2 tRDS 4 tRDH is measured from A21 A0 or CAS whichever is negated first 5 tRDH is measured from A2...

Page 576: ...r Tc1 Tw Tc2 Row Column tWTS tWTH tWTS tWTH tACC2 2 tRAC2 3 tCAC2 1 RD Write RD Read tRSD tRDD Notes 1 For tCAC2 use tcyc n 1 25 instead of tcyc n 1 tCASD2 tRDS 2 For tACC2 use tcyc n 2 30 instead of tcyc n 2 tAD tRDS 3 For tRAC2 use tcyc n 2 5 20 instead of tcyc n 2 5 tRASD1 tRDS Figure 20 59 DRAM Bus Cycle Long Pitch High Speed Page Mode Wait State ...

Page 577: ...H WRL WR TRp TRr TRc tRASD1 tRASD2 tCASD3 tCASD2 tCSR Figure 20 60 CAS before RAS Refresh Short Pitch CK RAS CAS WRH WRL WR TRp TRc TRc tRASD1 tRASD2 tCASD3 tCASD2 TRr tCSR Figure 20 61 CAS before RAS Refresh Long Pitch ...

Page 578: ...543 CK RAS CAS TRp TRc TRcc tRASD1 tRASD2 tCASD3 tCASD2 TRr tCSR Figure 20 62 Self Refresh ...

Page 579: ...WR Write AD15 AD0 Write DACK0 DACK1 Write WAIT T1 T2 T3 T4 tCSD4 tCSD3 tAD tAHD1 tAHD2 tRSD tRDH tMAH tMAD tRDAC3 tDACD2 tDACD1 tWSD1 tWSD2 tMAD tMAH tWDD1 tDACD3 tDACD3 tWTH tWTS Address Address Data output tRDD tWDH Data input Figure 20 63 Address Data Multiplex I O Bus Cycle ...

Page 580: ...545 CK A21 A0 HBS LBS CSn DACK0 DACK1 Write WRH WRL WR Write T1 tAD tCSD1 tCSD2 tWSD4 tDACD1 tDACD2 tWSD1 Figure 20 64 DMA Single Transfer One State Access Write ...

Page 581: ... products for wide temperature range products Ta 40 to 85 C 12 5 MHz 20 MHz Item Symbol Min Max Min Max Unit Figure DREQ0 DREQ1 setup time tDRQS 80 27 ns 20 65 DREQ0 DREQ1 hold time tDRQH 30 30 ns DREQ0 DREQ1 Pulse width tDRQW 1 5 1 5 tcyc 20 66 tDRQS tDRQS CK DREQ0 DREQ1 level DREQ0 DREQ1 edge tDRQS tDRQH DREQ0 DREQ1 level release Figure 20 65 DREQ0 DREQ1 Input Timing 1 ...

Page 582: ...e temperature range products Ta 40 to 85 C 12 5 MHz 20 MHz Item Symbol Min Max Min Max Unit Figure Output compare delay time tTOCD 100 100 ns 20 67 Input capture setup time tTICS 50 35 ns Timer clock input setup time tTCKS 50 50 ns 20 68 Timer clock pulse width single edge tTCKWH L 1 5 1 5 tcyc Timer clock pulse width both edges tTCKWL L 2 5 2 5 tcyc tTOCD CK tTICS Output compare 1 Input capture 2...

Page 583: ...0 3V AVref 3 0 V to AVCC VSS AVSS 0 V φ 12 5 to 20 MHz 1 Ta 20 to 75 C 2 Notes 1 ROMless products only for 20 MHz version 2 Regular specification products for wide temperature range products Ta 40 to 85 C Item Symbol Min Max Unit Figure Port output delay time tPWD 100 ns 20 69 Port input hold time tPRH 50 ns Port input setup time tPRS 50 ns tPRS CK tPWD Ports A C Read Ports A C Write T1 T2 T3 tPRH...

Page 584: ...3 0 V to AVCC VSS AVSS 0 V φ 12 5 to 20 MHz 1 Ta 20 to 75 C 2 Notes 1 ROMless products only for 20 MHz version 2 Regular specification products for wide temperature range products Ta 40 to 85 C Item Symbol Min Max Unit Figure WDTOVF delay time tWOVD 100 ns 20 70 tWOVD CK tWOVD WDTOVF Figure 20 70 Watchdog Timer Output Timing ...

Page 585: ...e temperature range products Ta 40 to 85 C Item Symbol Min Max Unit Figure Input clock cycle tscyc 4 tcyc 20 71 Input clock cycle synchronous mode tscyc 6 tcyc Input clock pulse width tSCKW 0 4 0 6 tscyc Input clock rise time tSCKr 1 5 tcyc Input clock fall time tSCKf 1 5 tcyc Transmit data delay time synchronous mode tTXD 100 ns 20 72 Receive data setup time synchronous mode tRXS 100 ns Receive d...

Page 586: ...MHz 1 Ta 20 to 75 C 2 Notes 1 ROMless products only for 20 MHz version 2 Regular specification products for wide temperature range products Ta 40 to 85 C Item Symbol Min typ Max Unit Figure External trigger input pulse width tTRGW 2 0 tcyc 20 73 External trigger input start delay time tTRGS 50 ns A D conversion start delay time CKS 0 tD 10 17 tcyc 20 74 CKS 1 6 9 tcyc Input sampling time CKS 0 tSP...

Page 587: ...K 1 state tTRGS tTRGW tTRGW ADTRG input ADST Figure 20 73 External Trigger Input Timing tSPL Max 14 states tD 3 states tCONV CK Address Analog input sampling signal ADF Figure 20 74 Analog Conversion Timing ...

Page 588: ...in 30pF CK CASH CASL CS0 CS7 BREQ BACK AH IRQOUT RAS DACK0 DACK1 50pF A21 A0 AD15 AD0 DPH DPL RD WRH WRL HBS LBS WR 70pF All port outputs and supporting module output pins other than the above IOL and IOH values are as shown in section 20 2 2 DC Characteristics and table 20 18 Permitted Output Current Values Figure 20 75 Output Load Circuit ...

Page 589: ... products for wide temperature range products Ta 40 to 85 C 12 5 MHz 20 MHz Item Min Typ Max Min Typ Max Unit Resolution 10 10 10 10 10 10 bit Conversion time 11 2 6 7 µS Analog input capacitance 20 20 pF Permissible signal source impedance 1 1 kΩ Nonlinearity error 4 0 4 0 LSB Offset error 4 0 4 0 LSB Full scale error 4 0 4 0 LSB Quantization error 0 5 0 5 LSB Absolute accuracy 6 0 6 0 LSB Note R...

Page 590: ...On Chip Supporting Module Registers A 1 List of Registers The addresses and bit names of the on chip supporting module registers are listed below 16 and 32 bit registers are shown as two or four levels of 8 bits each ...

Page 591: ... CHR PE O E STOP MP CKS1 CKS0 SCI H 5FFFEC9 BRR1 channel 1 H 5FFFECA SCR1 TIE RIE TE RE MPIE TEIE CKE1 CKE0 H 5FFFECB TDR1 H 5FFFECC SSR1 TDRE RDRF ORER FER PER TEND MPB MPBT H 5FFFECD RDR1 H 5FFFECE H 5FFFEDF H 5FFFEE0 ADDRAH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 A D H 5FFFEE1 ADDRAL AD1 AD0 H 5FFFEE2 ADDRBH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 H 5FFFEE3 ADDRBL AD1 AD0 H 5FFFEE4 ADDRCH AD9 AD8 AD7 AD6 AD5 A...

Page 592: ...F07 TSR0 1 OVF IMFB IMFA H 5FFFF08 TCNT0 H 5FFFF09 H 5FFFF0A GRA0 H 5FFFF0B H 5FFFF0C GRB0 H 5FFFF0D H 5FFFF0E TCR1 1 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 H 5FFFF0F TIORL 1 IOB2 IOB1 IOB0 IOA2 IOA1 IOA0 H 5FFFF10 TIERl 1 OVIE IMIEB IMIEA H 5FFFF11 TSR1 1 OVF IMFB IMFA H 5FFFF12 TCNT1 H 5FFFF13 H 5FFFF14 GRA1 H 5FFFF15 H SFFFF16 GRB1 H 5FFFF17 H 5FFFF18 TCR2 1 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPS...

Page 593: ... 1 OVF IMFB IMFA H 5FFFF26 TCNT3 H 5FFFF27 H 5FFFF28 GRA3 H 5FFFF29 H 5FFFF2A GRB3 H 5FFFF2B H 5FFFF2C BRA3 H 5FFFF2D H 5FFFF2E BRB3 H 5FFFF2F H 5FFFF31 TOCR 1 OLS4 OLS3 ITU chan nels 0 4 shared H 5FFFF32 TCR4 1 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 ITU chan H 5FFFF33 TIOR4 1 IOB2 IOB1 IOB0 IOA2 IOA1 IOA0 nel 4 H 5FFFF34 TIER4 1 OVIE IMIEB IMIEA H 5FFFF35 TSR4 1 OVF IMFB IMFA H 5FFFF36 TCNT4 H...

Page 594: ...FFF47 H 5FFFF48 DMAOR 2 PR1 PR0 H 5FFFF49 AE NMIF DME H 5FFFF4A TCR0 5 H 5FFFF4B H 5FFFF4C H 5FFFF4D H 5FFFF4E CHCR0 DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0 H 5FFFF4F AM AL DS TM TS IE TE DE H 5FFFF50 SAR1 5 DMAC H 5FFFF51 channel 1 H 5FFFF52 H 5FFFF53 H 5FFFF54 DAR1 5 H 5FFFF55 H 5FFFF56 H 5FFFF57 H 5FFFF58 H 5FFFF59 H 5FFFF5A TCR1 5 H 5FFFF5B H 5FFFF5C H 5FFFF5D H 5FFFF5E CHCR1 DM1 DM0 SM1 SM0 RS3 RS2 R...

Page 595: ... H 5FFFF66 H 5FFFF67 H 5FFFF68 H 5FFFF69 H 5FFFF6A TCR2 5 H 5FFFF6B H 5FFFF6C H 5FFFF6D H 5FFFF6E CHCR2 DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0 H 5FFFF6F AM AL DS TM TS IE TE DE H 5FFFF70 SAR3 5 DMAC H 5FFFF71 channel 3 H 5FFFF72 H 5FFFF73 H 5FFFF74 DAR3 5 H 5FFFF75 H 5FFFF76 H 5FFFF77 H 5FFFF78 H 5FFFF79 H 5FFFF7A TCR3 5 H 5FFFF7B H 5FFFF7C H 5FFFF7D H 5FFFF7E CHCR3 DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0 H5FFFF...

Page 596: ...Q3S IRQ4S IRQ5S IRQ6S IRQ7S H 5FFFF90 BARH BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 UBC H 5FFFF91 BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16 H 5FFFF92 BARL BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8 H 5FFFF93 BA7 BA6 BA5 BA4 BA3 BA2 BA1 BA0 H 5FFFF94 BAMRH BAM31 BAM30 BAM29 BAM28 BAM27 BAM26 BAM25 BAM24 H 5FFFF95 BAM23 BAM22 BAM21 BAM20 BAM19 BAM18 BAM17 BAM16 H 5FFFF96 BAMRL BAM15 BAM14 BAM13 BAM12 BAM11 ...

Page 597: ...5 DWW4 DWW3 DWW2 DWW1 DWW0 H 5FFFFA6 WCR3 WPU A02LW1 A02LW0 A6LW1 A6LW0 H 5FFFFA7 H 5FFFFA8 DCR CW2 RASD TPC BE CDTY MXE MXC1 MXC0 H 5FFFFA9 H 5FFFFAA PCR PEF PFRC PEO PCHK1 PCHK0 H 5FFFFAB H 5FFFFAC RCR H 5FFFFAD RFSHE RMODE RLW1 RLW0 H 5FFFFAE RTCSR H 5FFFFAF CMF CMIE CKS2 CKS1 CKS0 H 5FFFFB0 RTCNT H 5FFFFB1 H 5FFFFB2 RTCOR H 5FFFFB3 H 5FFFFB4 H 5FFFFB7 H 5FFFFB8 TCSR 3 OVF WT lT TME CKS2 CKS1 C...

Page 598: ... IOR PB14 IOR PB13 IOR PB12 IOR PB11 IOR PB10 IOR PB9 IOR PB8 IOR H SFFFFC7 PB7 IOR PB6 IOR PB5 IOR PB4 IOR PB3 IOR PB2 IOR PB1 IOR PB0 IOR H 5FFFFC8 PACR1 PA15 MD1 PA15 MD0 PA14 MD1 PA14 MD0 PA13 MD1 PA13 MD0 PA12 MD1 PA12 MD0 H 5FFFFC9 PA11 MD1 PA11 MD0 PA10 MD1 PA10 MD0 PA9 MD1 PA9 MD0 PA8 MD H 5FFFFCA PACR2 PA7 MD PA6 MD PA5 MD PA4 MD H 5FFFFCB PA3 MD1 PA3 MD0 PA2 MD1 PA2 MD0 PA1 MD1 PA1 MD0 P...

Page 599: ...tes 1 Only 8 bit accessible 16 bit and 32 bit access disabled 2 Register shared by all channels 3 Address for read For writing the addresses are H 5FFFFB8 for TCR and TCNT and H 5FFFFBA for RSTCSR For more information see section 12 Watchdog Timer WDT particularly section 12 2 4 Notes on Register Access 4 When the output triggers for TPC output group 0 and TPC output group 1 set by TPCR are the sa...

Page 600: ... Character length CHR 0 8 bit data Initial value 1 7 bit data 5 Parity enable PE 0 Parity bit addition and check disable Initial value 1 Parity bit addition and check enable 4 Parity mode O E 0 Even parity Initial value 1 Odd parity 3 Stop bit length STOP 0 1 stop bit Initial value 1 2 stop bits 2 Multiprocessor mode MP 0 Multiprocessor function disabled Initial value 1 Multiprocessor function sel...

Page 601: ... R W R W R W R W R W R W Table A 4 BBR Bit Functions Bit Bit name Description 7 0 Bit rate setting Set serial transmission reception bit rate A 2 3 Serial Control Register SCR SCI Start Address H 5FFFEC2 channel 0 H 5FFFECA channel 1 Bus Width 8 16 Register Overview Bit 7 6 5 4 3 2 1 0 Bit name TIE RIE TE RE MPIE TEIE CKE1 CKE0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ...

Page 602: ...1 is received 1 Multiprocessor interrupts enabled Disables receive interrupts RXI receive error interrupts ERI and setting of RDRF FER and ORER flags in SSR until data with a 1 multiprocessor bit is received 2 Transmit end inter 0 Transmit interrupt requests TEI disabled Initial value rupt enable TEIE 1 Transmit interrupt requests TEI enabled 1 Clock enable 1 CKE1 0 0 Asynchronous mode Internal cl...

Page 603: ... W R W Table A 6 TDR Bit Functions Bit Bit name Description 7 0 Transmit data storage Store data for serial transmission A 2 5 Serial Status Register SSR SCI Start Address H 5FFFEC4 channel 0 H 5FFFECC channel 1 Bus Width 8 16 Register Overview Bit 7 6 5 4 3 2 1 0 Bit name TDRE RDRF ORER FER PER TEND MPB MPBT Initial value 1 0 0 0 0 1 0 0 R W R W R W R W R W R W R R R W Note Only 0 can be written ...

Page 604: ... progress or has ended normally Initial value Clear Conditions 1 Reset or standby mode 2 0 written in ORER after reading ORER 1 1 Indicates that an overrun error occurred in reception Set Conditions The next serial reception ends while RDRF 1 4 Framing error FER 0 Indicates that reception is in progress or has ended normally Initial value Clear Conditions 1 Reset or standby mode 2 0 written in FER...

Page 605: ... transmitted 1 Multiprocessor bit MPB 0 Indicates that data with multiprocessor bit 0 has been received Initial value 1 Indicates that data with multiprocessor bit 1 has been received 0 Multiprocessor 0 0 transmitted as the multiprocessor bit Initial value bit transfer MPBT 1 1 transmitted as the multiprocessor bit A 2 6 Receive Data Register RDR SCI Start Address H 5FFFEC5 channel 0 H 5FFFECD cha...

Page 606: ...me AD1 AD0 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R Table A 8 ADDRAH ADDRL Bit Functions Bit Bit name Description 15 8 A D data 9 2 Stores upper 8 bits of A D conversion result 7 6 A D data 1 0 Stores upper 2 bits of A D conversion result A 2 8 A D Control Status Register ADCSR A D Start Address H 5FFFEF8 Bus Width 8 16 Register Overview Bit 7 6 5 4 3 2 1 0 Bit name ADF ADIE ADST SCAN CKS...

Page 607: ...sion ADI enabled 5 A D start ADST 0 Disable A D conversion Initial value 1 1 Single mode Start A D conversion and when conversion ends automatically cleared to zero 2 Scan mode Start A D conversion and sequentially continue converting the selected channels until cleared to 0 by software reset or standby mode 4 Scan mode SCAN 0 Single mode Initial value 1 Scan mode 3 Clock select CKS 0 Conversion t...

Page 608: ...me Value Description 7 Trigger enable bit TRGE 0 Start of A D conversion by external trigger disabled Initial value 1 Start of A D conversion by rising edge of external conversion trigger input pin ADTRG enabled A 2 10 Timer Start Register TSTR ITU Start Address H 5FFFF00 Bus Width 8 Register Overview Bit 7 6 5 4 3 2 1 0 Bit name STR4 STR3 STR2 STR1 STR0 Initial value 1 1 1 0 0 0 0 0 R W R W R W R...

Page 609: ...Count operation of TCNT 2 stops Initial value 1 TCNT2 counts 1 Counter start 1 STR1 0 Count operation of TCNT 1 stops Initial value 1 TCNT1 counts 0 Counter start 0 STR0 0 Count operation of TCNT 0 stops Initial value 1 TCNT0 counts A 2 11 Timer Synchronization Register TSNC ITU Start Address H 5FFFF01 Bus Width 8 Register Overview Bit 7 6 5 4 3 2 1 0 Bit name SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 Initial...

Page 610: ...eset sync clear enabled 2 Timer sync 2 SYNC2 0 Independent operation of channel 2 timer counter TCNT2 Initial value Preset clear of TCNT2 is unrelated to other channels 1 Channel 2 operation is synchronous TCNT2 sync preset sync clear enabled 1 Timer sync 1 SYNC1 0 Independent operation of channel 1 timer counter TCNT1 Initial value Preset clear of TCNT1 is unrelated to other channels 1 Channel 1 ...

Page 611: ...hase count mode 5 Flag direction FDIR 0 OVF of TSR2 set to 1 when TCNT2 overflows or underflows Initial value 1 OVF in TSR2 set to 1 when TCNT2 overflows 4 PWM mode 4 PWM4 0 Channel 4 operates normally Initial value 1 Channel 4 in PWM mode 3 PWM mode 3 PWM3 0 Channel 3 operates normally Initial value 1 Channel 3 in PWM mode 2 PWM mode 2 PWM2 0 Channel 2 operates normally Initial value 1 Channel 2 ...

Page 612: ...al value 0 1 Channel 3 and 4 operate normally 1 0 Channels 3 and 4 are combined to operate in complementary PWM mode 1 1 Channels 3 and 4 are combined to operate in reset synchronized PWM mode 3 Buffer mode B4 BFB4 0 GRB4 operates normally Initial value 1 Buffer operation of GRB4 and BRB4 2 Buffer mode A4 BFA4 0 GRA4 operates normally Initial value 1 Buffer operation of GRA4 and BRA4 1 Buffer mode...

Page 613: ...ompare match input capture 1 0 TCNT cleared upon GRB compare match input capture 1 1 Synchronized clear TCNT cleared in synchronization with counter clear of other timers operating in sync 4 3 Clock edge 1 0 CKEG1 0 0 Count on rising edge Initial value CKEG0 0 1 Count on falling edge 1 Count on both rising and falling edges 2 0 Timer prescaler 2 0 0 0 0 Internal clock Count on φ Initial value TPSC...

Page 614: ...tput on GRB compare match 0 1 0 1 output on GRB compare match 0 1 1 Toggle output on GRB compare match 1 output on channel 2 only 1 0 0 GRB is input Input capture to GRB on rising edge 1 0 1 capture register Input capture to GRB on falling edge 1 1 Input capture on both rising and falling edges 2 0 I O control A2 0 IOA2 IOA0 0 0 0 GRA is output compare register Pin output due to compare match disa...

Page 615: ...etermined Table A 17 TIER0 TIER4 Bit Functions Bit Bit name Value Description 2 Overflow interrupt enable OVIE 0 Interrupt request by OVF OVI disabled Initial value 1 Interrupt request by OVF OVI enabled 1 Input capture compare match interrupt enable B IMIEB 0 Interrupt request by IMFB IMIB disabled Initial value 1 Interrupt request by IMFB IMIB enabled 0 Input capture compare match interrupt enab...

Page 616: ...tions TCNT value overflows H FFFF H 0000 or underflows H FFFF H 0000 1 Input capture compare match flag B IMFB 0 Clear conditions 0 is written in IMFB after reading IMFB 1 Initial value 1 Set conditions 1 When GRB is functioning as the output compare register and TCNT GRB 2 When GRB is functioning as the input capture register and the TCNT value is transferred to GRB by the input capture signal 0 ...

Page 617: ...FFF36 channel 4 Bus Width 8 16 32 Register Overview Bit 15 14 13 12 11 10 9 8 Bit name Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 Bit name Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Table A 19 TCNT0 TCNT4 Bit Functions Bit Bit name Description 15 0 Count value Count input clocks ...

Page 618: ...name Initial value 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 Bit name Initial value 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W Table A 20 GRA0 GRA4 Bit Functions Bit Bit name Description 15 0 Registers used for both output compare and input capture Output compare register Set with compare match output Input capture register Stores the TCNT value when the inpu...

Page 619: ...name Initial value 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 Bit name Initial value 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W Table A 21 GRB0 GRB4 Bit Functions Bit Bit name Description 15 0 Registers used for both output compare and input capture Output compare register Set with compare match output Input capture register Stores the TCNT value when the inpu...

Page 620: ...W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 Bit name Initial value 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W Table A 22 BRA3 BRA4 Bit Functions Bit Bit name Description 15 0 Buffer registers used for output compare input capture Output compare register Transfers to GRA the value stored up to compare match generation Input capture register Stores the value stored in GRA up to input capture ...

Page 621: ...W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 Bit name Initial value 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W Table A 23 BRB3 BRB4 Bit Functions Bit Bit name Description 15 0 Buffer registers used for output compare input capture Output compare register Transfers to GRB the value stored up to compare match generation Input capture register Stores the value stored in GRB up to input capture ...

Page 622: ...ue 1 1 1 1 1 1 1 R W R W R W Note Undetermined Table A 24 TOCR Bit Functions Bit Bit name Value Description 1 Output level select 4 OLS4 0 Reverse output of TIOCA3 TIOCA4 TIOCB4 1 Direct output of TIOCA3 TIOCA4 TIOCB4 Initial value 0 Output level select 3 OLS3 0 Reverse output of TIOCB3 TOCXA4 TOCXB4 1 Direct output of TIOCB3 TOCXA4 TOCXB4 Initial value ...

Page 623: ...W R W R W R W R W R W R W R W Bit 23 22 21 20 19 18 17 16 Bit name Initial value R W R W R W R W R W R W R W R W R W Bit 15 14 13 12 11 10 9 8 Bit name Initial value R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 Bit name Initial value R W R W R W R W R W R W R W R W R W Note Undetermined Table A 25 SAR0 SAR3 Bit Functions Bit Bit name Description 31 0 Specifies transfer source address Sp...

Page 624: ... W R W R W R W R W R W R W Bit 23 22 21 20 19 18 17 16 Bit name Initial value R W R W R W R W R W R W R W R W R W Bit 15 14 13 12 11 10 9 8 Bit name Initial value R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 Bit name Initial value R W R W R W R W R W R W R W R W R W Note Undetermined Table A 26 DAR0 DAR3 Bit Functions Bit Bit name Description 31 0 Specifies transfer destination address ...

Page 625: ...15 14 13 12 11 10 9 8 Bit name Initial value R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 Bit name Initial value R W R W R W R W R W R W R W R W R W Note Undetermined Table A 27 TCR0 TCR3 Bit Functions Bit Bit name Description 15 0 Specifies number of DMA transfers Specifies the number of DMA transfers bytes or words During DMA transfer indicates the number of transfers remaining ...

Page 626: ...32 Register Overview Bit 15 14 13 12 11 10 9 8 Bit name DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 Bit name AM AL DS TM TS IE TE DE Initial value 0 0 0 0 0 0 0 0 R W R W 2 R W 2 R W 2 R W R W R W R W 1 R W Notes 1 Only 0 can be written to clear the flag 2 Writing is valid only for CHCR0 and CHCR1 ...

Page 627: ... 8 Resource select bits 3 0 RS3 RS0 0 0 0 0 DREQ external request 1 Initial value Dual address mode 0 0 0 1 Reserved cannot be set 0 0 1 0 DREQ external request 1 Single address mode 2 0 0 1 1 DREQ external request 1 Single address mode 3 0 1 0 0 RXIO transfer request by receive data full interrupt of on chip SCI0 4 0 1 0 1 TXIO transfer request by transmit data empty interrupt of on chip SCI0 4 0...

Page 628: ...REQ select bit 0 DREQ detected at low Initial value DS 1 1 DREQ detected on falling edge 4 Transfer bus mode bit 0 Cycle steal mode Initial value TM 1 Burst mode 3 Transfer size bit TS 0 Byte 8 bits Initial value 1 Word 16 bits 2 Interrupt enable bit 0 Interrupt request disabled Initial value IE 1 Interrupt request enabled 1 Transfer end flag bit TE 0 DMA transferring or DMA transfer halted Initia...

Page 629: ...l 2 channel 1 0 1 Priority order is fixed Channel 1 channel 3 channel 2 channel 0 1 0 Round robin priority order Immediately after reset Channel 0 channel 3 channel 2 channel 1 1 1 External pin alternating mode priority order Immediately after reset Channel 3 channel 2 channel 1 channel 0 2 Address error flag bit AE 0 No errors caused by DMAC Initial value Clear Condition Write 0 in AE after readi...

Page 630: ... R W R W Bit 7 6 5 4 3 2 1 0 Bit name Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Table A 30 IPRA Bit Functions Bit Bit name Description 15 12 Set IRQ0 priority level Sets the IRQ0 priority level value 11 8 Set IRQ1 priority level Sets the IRQ1 priority level value 7 4 Set IRQ2 priority level Sets the IRQ2 priority level value 3 0 Set IRQ3 priority level Sets the IRQ3 priorit...

Page 631: ... R W R W Bit 7 6 5 4 3 2 1 0 Bit name Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Table A 31 IPRB Bit Functions Bit Bit name Description 15 12 Set IRQ4 priority level Sets the IRQ4 priority level value 11 8 Set IRQ5 priority level Sets the IRQ5 priority level value 7 4 Set IRQ6 priority level Sets the IRQ6 priority level value 3 0 Set IRQ7 priority level Sets the IRQ7 priorit...

Page 632: ... 1 0 Bit name Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Table A 32 IPRC Bit Functions Bit Bit name Description 15 12 Set DMAC0 and DMAC1 priority levels Sets the DMAC0 and DMAC1 priority level values 11 8 Set DMAC2 and DMAC3 priority levels Sets the DMAC2 and DMAC3 priority level values 7 4 Set ITU0 priority level Sets the ITU0 priority level value 3 0 Set ITU1 priority lev...

Page 633: ... R W R W Bit 7 6 5 4 3 2 1 0 Bit name Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Table A 33 IPRD Bit Functions Bit Bit name Description 15 12 Set ITU2 priority level Sets the ITU2 priority level value 11 8 Set ITU3 priority level Sets the ITU3 priority level value 7 4 Set ITU4 priority level Sets the ITU4 priority level value 3 0 Set SCI0 priority level Sets the SCI0 priorit...

Page 634: ... Functions Bit Bit name Description 15 12 Set SCI1 priority level Sets the SC1 priority level value 11 8 Set PRT 1 and A D priority levels Sets the PRT 1 and A D priority level values 7 4 Set WDT and REF 2 priority levels Sets the WDT and REF 2 priority level value Notes 1 PRT Parity control section within the bus state controller See section 8 Bus State Controller BSC for more information 2 REF D...

Page 635: ...W R W R W R W R W R W R W R W Note NMI pin input high 1 NMI pin input low 0 Table A 35 ICR Bit Functions Bit Bit Name Value Description 15 NMI input level NMIL 0 Low input to NMI pin 1 High input to NMI pin 8 NMI edge select NMIE 0 Interrupt request sensed at falling edge of NMI input Initial value 1 Interrupt request sensed at rising edge of NMI input 7 0 IRQ0 7 sense select IRQ0 IRQ7 0 Interrupt...

Page 636: ...4 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 Bit name BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Table A 36 BARH Bit Functions Bit Bit name Description 15 0 Set break address bits 31 16 BA31 BA16 Specifies the upper end bits 31 16 of the address which is the break condition ...

Page 637: ...9 BA8 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 Bit name BA7 BA6 BA5 BA4 BA3 BA2 BA1 BA0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Table A 37 BARL Bit Functions Bit Bit name Description 15 0 Set break address bits 15 0 BA15 BA0 Specifies the lower end bits 15 0 of the address which is the break condition ...

Page 638: ...25 BAM24 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 Bit name BAM23 BAM22 BAM21 BAM20 BAM19 BAM18 BAM17 BAM16 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Table A 38 BAMRH Bit Functions Bit Bit name Description 15 0 Break address masks 31 16 BAM31 BAM16 Specifies the bits to be masked in the break address specified in BARH ...

Page 639: ...10 BAM9 BAM8 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 Bit name BAM7 BAM6 BAM5 BAM4 BAM3 BAM2 BAM1 BAM0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Table A 39 BAMRL Bit Functions Bit Bit name Description 15 0 Break address masks 15 0 BAM15 BAM0 Specifies the bits to be masked in the break address specified in BARL ...

Page 640: ...ycle and DMA cycle are both break conditions 5 4 0 0 User break interrupt not generated Initial value 0 1 Instruction fetch cycle is break condition 1 0 Data access cycle is break condition 1 1 Instruction fetch cycle and data access cycle are both break conditions 3 2 Read write select 0 0 User break interrupt not generated Initial value RW1 RW0 0 1 Read cycle is break condition 1 0 Write cycle i...

Page 641: ...rnal memory space Initial value 1 Area 1 is DRAM space 14 Multiplex I O enable IOE 0 Area 6 is external memory space Initial value 1 Area 6 is address data multiplex I O space 13 Warp mode WARP 0 Normal mode External access and internal access not performed simultaneously Initial value 1 Warp mode External access and internal access performed simultaneously 12 RD duty RDDTY 0 RD signal high width ...

Page 642: ...tions Number of read cycles WAIT External Space Internal Space Bit Bit Name Value Pin Signal Input External Memory Space DRAM Space Multi plex I O On Chip Modules On Chip ROM RAM 15 8 Read wait state control RW7 RW0 0 Not sampled during read cycle Areas 1 3 5 7 fixed at 1 cycle Areas 0 2 6 1 cycle long wait state Column address cycle Fixed at 1 cycle short pitch Wait state is 4 cycles plus WAIT Fi...

Page 643: ...is 2 cycles WAIT Note During a CBR refresh the WAIT signal is ignored and the wait state inserted using the RLW1 and RLW0 bits A 2 42 Wait State Control Register 2 WCR2 BSC Start Address H 5FFFFA4 Bus Width 8 16 32 Register Overview Bit 15 14 13 12 11 10 9 8 Bit name DRW7 DRW6 DRW5 DRW4 DRW3 DRW2 DRW1 DRW0 Initial value 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 Bit na...

Page 644: ...d cycle Initial value Areas 1 3 5 7 wait state is 2 cycles plus WAIT Areas 0 2 6 1 cycle long wait state or wait state from WAIT Column address cycle Wait state is 2 cycles plus WAIT long pitch 7 0 Single mode DMA memory write wait state control DWW7 DWW0 0 Not sampled during single mode DMA memory write cycle Areas 1 3 5 7 fixed at 1 cycle Areas 0 2 6 1 cycle long wait state Column address cycle ...

Page 645: ... Value Description 15 Wait pin pull up control WPU 0 WAIT pin not pulled up 1 WAIT pin pulled up Initial value 14 13 Areas 0 and 2 long wait insert 1 0 A02LW1 A02LW0 0 0 1 cycle long wait state inserted 0 1 2 cycle long wait state inserted 1 0 3 cycle long wait state inserted 1 1 4 cycle long wait state inserted Initial value 12 11 Area 6 long wait insert 1 0 A6LW1 A6LW0 0 0 1 cycle long wait stat...

Page 646: ... Address H 5FFFFA8 Bus Width 8 16 32 Register Overview Bit 15 14 13 12 11 10 9 8 Bit name CW2 RASD TPC BE CDTY MXE MXC1 MXC0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 Bit name Initial value 0 0 0 0 0 0 0 0 R W ...

Page 647: ...serted Initial value cycles TPC 1 2 cycle pre charge cycle inserted 12 Burst operation enable BE 0 Normal mode Full access Initial value 1 High speed page mode Burst operation 11 CAS duty CDTY 0 CAS signal high width duty ratio is 50 Initial value 1 CAS signal high width duty ratio is 35 10 Multiplex enable MXE 0 Row address and column address not multiplexed Initial value 1 Row address and column...

Page 648: ...ame Value Description 15 Parity error flag PEF 0 No parity error Initial value Clear Condition PEF read then 0 written in PEF 1 Parity error occurred 14 Parity forced output 0 No forced parity output Initial value PFRC 1 Forced high level output 13 Parity polarity PEO 0 Even parity Initial value 1 Odd parity 12 11 Parity check enable 1 0 0 0 Parity not checked or generated Initial value PCHK1 PCHK...

Page 649: ... R W R W R W Table A 47 RCR Bit Functions Bit Bit Name Value Description 7 Refresh control RFSHE 0 No refresh control Initial value RTCNT can be used as an interval timer 1 Refresh control 6 Refresh mode RMODE 0 CAS before RAS refresh performed Initial value 1 Self refresh performed 5 4 Wait state insertion CBR 0 0 1 cycle wait state inserted Initial value refresh 1 0 RLW1 RLW0 0 1 2 cycle wait st...

Page 650: ...W R W Table A 48 RSTCR Bit Functions Bit Bit Name Value Description 7 Compare match flag CMF 0 RTCNT and RTCOR values do not match Initial value Clear Condition CMF read then 0 written in CMF 1 RTCNT and RTCOR values match 6 Compare match interrupt 0 Compare match interrupt CMI disabled Initial value enable CMIE 1 Compare match interrupt CMI enabled 5 3 Clock select 2 0 CKS2 0 0 0 Clock input disa...

Page 651: ...ad 16 write Register Overview Bit 15 14 13 12 11 10 9 8 Bit name Initial value 0 0 0 0 0 0 0 0 R W Bit 7 6 5 4 3 2 1 0 Bit name Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Table A 49 RTCNT Bit Functions Bit Bit Name Description 7 0 Count value Input clock count value ...

Page 652: ...ue 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W Table A 50 RTCOR Bit Functions Bit Bit Name Description 7 0 Compare match cycle Set with compare match cycle A 2 50 Timer Control Status Register TCSR WDT Start Address H 5FFFFB8 Bus Width 8 read 16 write Register Overview Bit 7 6 5 4 3 2 1 0 Bit name OVF WT IT TME CKS2 CKS1 CKS0 Initial value 0 0 0 1 1 0 0 0 R W R W R W R W R W R W R W Note O...

Page 653: ...signal is output externally 5 Timer enable TME 0 Timer disable TCNT initialized at H 00 and count up halted Initial value 1 Timer enable TCNT starts counting up When TCNT overflows a WDTOVF signal or interrupt is generated 2 0 Clock select 2 0 Clock Overflow cycle φ 20 MHz CKS2 CKS0 0 0 0 φ 2 Initial value 25 6 µs 0 0 1 φ 64 819 2 µs 0 1 0 φ 128 1 6 ms 0 1 1 φ 256 3 3 ms 0 0 0 φ 512 6 6 ms 0 0 1 φ...

Page 654: ... W R W R W R W R W R W R W Table A 52 TCNT Bit Functions Bit Bit Name Description 7 0 Count value Input clock count value A 2 52 Reset Control Status Register RSTCSR WDT Start Address H 5FFFFBB read H 5FFFFBA write Bus Width 8 read 16 write Register Overview Bit 7 6 5 4 3 2 1 0 Bit name WOVF RSTE RSTS Initial value 0 0 0 1 1 1 1 1 R W R W R W R W Note Only 0 can be written to clear the flag ...

Page 655: ...Manual reset Note The microprocessor is not reset internally but TCNT and TCSR within the WDT are reset A 2 53 Standby Control Register SBYCR Power Down State Start Address H 5FFFFBC Bus Width 8 16 32 Register Overview Bit 7 6 5 4 3 2 1 0 Bit name SBY HIZ Initial value 0 0 0 1 1 1 1 1 R W R W R W Table A 54 SBYCR Bit Functions Bit Bit Name Value Description 7 Standby SBY 0 Shift to sleep mode on e...

Page 656: ...1 0 Bit name PA7DR PA6DR PA5DR PA4DR PA3DR PA2DR PA1DR PA0DR Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Table A 55 PADR Bit Functions PAIOR Pin Function Read Write 0 General input Pin status Can write to PADR but this does not affect pin status All other Pin status Can write to PADR but this does not affect pin status 1 General input PADR value Value written is output from p...

Page 657: ...B5DR PB4DR PB3DR PB2DR PB1DR PB0DR Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Table A 56 Bit Functions PBIOR Pin Function Read Write 0 General input Pin status Can write to PBDR but this does not affect pin status TPn Pin status Cannot write All other Pin status Can write to PBDR but this does not affect pin status 1 General input PBDR value Value written is output from pin ...

Page 658: ... 10 9 8 Bit name Initial value R W R R R R R R R R Bit 7 6 5 4 3 2 1 0 Bit name PC7DR PC6DR PC5DR PC4DR PC3DR PC2DR PC1DR PC0DR Initial value R W R R R R R R R R Table A 57 PCDR Bit Functions Pin I O Pin Function Read Write Input General input Pin status Ignored no affect on pin status ANn 1 Ignored no affect on pin status ...

Page 659: ... IOR PA10 IOR PA9 IOR PA8 IOR Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 Bit name PA7 IOR PA6 IOR PA5 IOR PA4 IOR PA3 IOR PA2 IOR PA1 IOR PA0 IOR Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Table A 58 PAIOR Bit Functions Bit Bit Name Value Description 15 0 Port A I O PA15IOR 0 Input Initial value PA0IOR 1 Output ...

Page 660: ... IOR PB10 IOR PB9 IOR PB8 IOR Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 Bit name PB7 IOR PB6 IOR PB5 IOR PB4 IOR PB3 IOR PB2 IOR PB1 IOR PB0 IOR Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Table A 59 PBIOR Bit Functions Bit Bit Name Value Description 15 0 Port B I O PB15IOR PB0IOR 0 Input Initial value 1 Output ...

Page 661: ...14 13 12 11 10 9 8 Bit name PA15 MD1 PA15 MD0 PA14 MD1 PA14 MD0 PA13 MD1 PA13 MD0 PA12 MD1 PA12 MD0 Initial value 0 0 1 1 0 0 1 1 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 Bit name PA11 MD1 PA11 MD0 PA10 MD1 PA10 MD0 PA9 MD1 PA9 MD0 PA8 MD Initial value 0 0 0 0 0 0 1 0 R W R W R W R W R W R W R W R W ...

Page 662: ...l purpose input output PA12 PA12MD1 PA12MD0 0 1 Interrupt request input IRQ0 1 0 ITU timer clock input TCKLA 1 1 DMA transfer request acknowledge output DACK0 Initial value 7 6 PA11 mode bits 1 0 0 0 General purpose input output PA11 Initial value PA11MD1 PA11MD0 0 1 High data bus parity input output DPH 1 0 ITU input capture input output compare output TIOCB1 1 1 Reserved 5 4 PA10 mode bits 1 0 0...

Page 663: ... 16 32 Register Overview Bit 15 14 13 12 11 10 9 8 Bit name PA7MD PA6MD PA5MD PA4MD Initial value 1 1 1 1 1 1 1 1 R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 Bit name PA3MD1 PA3MD0 PA2MD1 PA2MD0 PA1MD1 PA1MD0 PA0MD1 PA0MD0 Initial value 1 0 0 1 0 1 0 1 R W R W R W R W R W R W R W R W R W ...

Page 664: ...ial value 7 6 PA3 mode bits 1 0 0 0 General purpose input output PA3 PA3MD1 PA3MD0 0 1 Chip select output CS7 1 0 Wait state input WAIT Initial value 1 1 Reserved 5 4 PA2 mode bits 1 0 0 0 General purpose input output PA2 PA2MD1 PA2MD0 0 1 Chip select output CS6 Initial value 1 0 ITU input capture input output compare output TIOCB0 1 1 Reserved 3 2 PA1 mode bits 1 0 0 0 General purpose input outpu...

Page 665: ...12 11 10 9 8 Bit name PB15 MD1 PB15 MD0 PB14 MD1 PB14 MD0 PB13 MD1 PB13 MD0 PB12 MD1 PB12 MD0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 Bit name PB11 MD1 PB11 MD0 PB10 MD1 PB10 MD0 PB9 MD1 PB9 MD0 PB8 MD1 PB8 MD0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ...

Page 666: ...s 1 0 0 0 General purpose input output PB12 Initial value PB12MD1 PB12MD0 0 1 Interrupt request input IRQ4 1 0 Serial clock input output SCK0 1 1 Timing pattern output TP12 7 6 PB11 mode bits 1 0 0 0 General purpose input output PB11 Initial value PB11MD1 PB11MD0 0 1 Reserved 1 0 Transmit data input TxD1 1 1 Timing pattern output TP11 5 4 PB10 mode bits 1 0 0 0 General purpose input output PB10 In...

Page 667: ... Bit 15 14 13 12 11 10 9 8 Bit name PB7MD1 PB7MD0 PB6MD1 PB6MD0 PB5MD1 PB5MD0 PB4MD1 PB4MD0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 Bit name PB3MD1 PB3MD0 PB2MD1 PB2MD0 PB1MD1 PB1MD0 PB0MD1 PB0MD0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ...

Page 668: ...put PB4 Initial value PB4MD1 PB4MD0 0 1 Reserved 1 0 ITU input capture input output compare output TIOCA4 1 1 Timing pattern output TP4 7 6 PB3 mode bits 1 0 0 0 General purpose input output PB3 Initial value PB3MD1 PB3MD0 0 1 Reserved 1 0 ITU input capture input output compare output TIOCB3 1 1 Timing pattern output TP3 5 4 PB2 mode bits 1 0 0 0 General purpose input output PB2 Initial value PB2M...

Page 669: ... W R W R W R W Bit 7 6 5 4 3 2 1 0 Bit name Initial value 1 1 1 1 1 1 1 1 R W Table A 64 CASCR Bit Functions Bit Bit Name Value Description 15 14 CASH mode bits 1 0 0 0 Reserved CASHMD1 CASHMD0 0 1 Chip select output CS1 Initial value 1 0 Column address strobe output CASH 1 1 Reserved 13 12 CASL mode bits 1 0 0 0 Reserved CASLMD1 CASLMD0 0 1 Chip select output CS3 Initial value 1 0 Column address ...

Page 670: ...utput value is updated at every compare match A of the selected ITU Initial value 1 TPC output group 2 operates in non overlap mode 1 output and 0 output can be performed independently upon compare matches A and B of the selected ITU 1 Group 1 non overlap G1NOV 0 TPC output group 1 operates normally the output value is updated at every compare match A of the selected ITU Initial value 1 TPC output...

Page 671: ...ol Register TPCR TPC Start Address H 5FFFFF1 Bus Width 8 16 Register Overview Bit 7 6 5 4 3 2 1 0 Bit name G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W ...

Page 672: ... is the ITU channel 2 compare match 1 1 The output trigger of TPC output group 2 pins TP11 TP8 is the ITU channel 3 compare match 3 2 Group 1 compare match sel ect 1 0 G1CMS1 G1CMS0 0 0 The output trigger of TPC output group 1 pins TP7 TP4 is the ITU channel 0 compare match 0 1 The output trigger of TPC output group 1 pins TP7 TP4 is the ITU channel 1 compare match 1 0 The output trigger of TPC ou...

Page 673: ...DR7 NDR0 to PB7 PB0 disabled 1 TPC output TP7 TP0 enabled Transfer from NDR7 NDR0 to PB7 PB0 enabled A 2 67 Next Data Enable Register B NDERB TPC Start Address H 5FFFFF2 Bus Width 8 16 Register Overview Bit 7 6 5 4 3 2 1 0 Bit name NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Table A 68 NDERB Bit Functions Bit Bit Name Valu...

Page 674: ...nctions Bit Bit Name Description 7 4 Next data 7 4 NDR7 NDR4 Stores the next output data for TPC output group 1 3 0 Next data 3 0 NDR3 NDR0 Stores the next output data for TPC output group 0 A 2 69 Next Data Register A NDRA TPC When the Output Triggers of TPC Output Groups 0 and 1 are the Same Start Address H 5FFFFF7 Bus Width 8 16 Register Overview Bit 7 6 5 4 3 2 1 0 Bit name Initial value 1 1 1...

Page 675: ...it Bit Name Description 7 4 Next data 7 4 NDR7 NDR4 Stores the next output data for TPC output group 1 A 2 71 Next Data Register A NDRA TPC When the Output Triggers of TPC Output Groups 0 and 1 are Different Start Address H 5FFFFF7 Bus Width 8 16 Register Overview Bit 7 6 5 4 3 2 1 0 Bit name NDR3 NDR2 NDR1 NDR0 Initial value 1 1 1 1 0 0 0 0 R W R W R W R W R W Table A 72 NDRA Bit Functions Bit Bi...

Page 676: ...ns Bit Bit Name Description 7 4 Next data 15 12 NDR15 NDR12 Stores the next output data for TPC output group 3 3 0 Next data 11 8 NDR11 NDR8 Stores the next output data for TPC output group 2 A 2 73 Next Data Register B NDRB TPC When the Output Triggers of TPC Output Groups 2 and 3 are the Same Start Address H 5FFFFF6 Bus Width 8 16 Module TPC Register Overview Bit 7 6 5 4 3 2 1 0 Bit name Initial...

Page 677: ... Bit Name Description 7 4 Next data 15 12 NDR15 NDR12 Stores the next output data for TPC output group 3 A 2 75 Next Data Register B NDRB TPC When the Output Triggers of TPC Output Groups 2 and 3 are Different Start Address H 5FFFFF6 Bus Width 8 16 Register Overview Bit 7 6 5 4 3 2 1 0 Bit name NDR11 NDR10 NDR9 NDR8 Initial value 1 1 1 1 0 0 0 0 R W R W R W R W R W Table A 76 NDRB Bit Functions Bi...

Page 678: ...lized Held Held SR GBR VBR MACH MACL PR PC Interrupt controller INTC IPRA IPRE Initialized Initialized Held Held ICR User break controller UBC BARH BARL Initialized Initialized Held Held BAMRH BAMRL BBR Bus state controller BSC BCR Initialized Held Held Held WCR1 WCR3 DCR RCR RTSCR RTCNT RTCOR PCR Direct memory access SAR0 SAR3 Initialized Initialized Initialized Held controller DMAC DAR0 DAR3 TCR...

Page 679: ...RB4 TCR0 TCR4 TIOR0 TIOR4 TIER0 TIER4 TSR0 TSR4 Programmable timing TPMR Initialized Initialized Held Held pattern controller TPC TPCR NDERA NDERB NDRA NDRB Watchdog timer WDT TCNT Initialized Initialized Held Held TCSR 1 RSTCR 2 Initialized Serial communication SMR Initialized Initialized Initialized Held interface SCI BRR SCR TDR TSR Held SSR Initialized RDR RSR Held Notes 1 Bits 7 5 OVF WT IT T...

Page 680: ...alized Initialized Initialized Held ADCSR ADCR Pin function controller PAIOR PBIOR Initialized Held Held Held PFC PACR1 PACR2 PBCR1 PBCR2 CASCR Parallel I O ports I O PADR PBDR Initialized Held Held Held PCDR 3 3 3 3 Power down state related SBYCR Initialized Initialized Held Held Note 3 Bits 15 8 are always undetermined bits 7 0 always reflect the state of the corresponding pin ...

Page 681: ... I Z I I IRQOUT O O 1 H O Address bus A21 A0 H O Z H Z Data bus AD15 AD0 Z Z Z Z Z DPH DPL Z Z Z Z Bus control WAIT I I 2 Z I 2 I 2 CS7 O Z H Z CS6 CS0 Z O Z H Z RD H O Z H Z WRH LBS WRL WR H O Z H Z RAS O O 1 O Z CASH CASL O O O Z AH O Z H Z Direct memory access DREQ0 DREQ1 I Z I I controller DMAC DACK0 DACK1 Z O K 1 O O 16 bit integrated timer TIOCA0 TIOCA4 I K 1 I O I O pulse unit ITU TIOCB0 TI...

Page 682: ...13 PA11 PA8 PB15 PB0 Z I O K 1 I O I O PC7 PC0 Z I Z I I One of the multiplexed pin functions is allocated but the pin functions in the reset state are different I Input O Output H High L Low Z High impedance K Input pins are high impedance output pins hold their state Notes 1 When the port high impedance bit HIZ in the standby control register SBYCR is set to 1 the output pins become high impedan...

Page 683: ...gh High High High High High CASL High High High High High High AH Low Low Low Low Low Low RD R High High High High High High W High High High High High WRH LBS R High High High High High High W High High High High High WRL WR R High High High High High High W High High High High High A0 HBS A0 A0 A0 A0 A0 A0 A21 A1 Address Address Address Address Address Address AD15 AD8 High Z High Z High Z High ...

Page 684: ...H RD R Low Low Low Low Low Low Low W High High High High High High High WRH LBS R High High High High Low Low W Low High Low High Low Low WRL WR R High High High High High High High W Low High Low Low Low Low Low A0 HBS A0 Low High Low Low High Low A21 A1 Address Address Address Address Address Address Address AD15 AD8 High Z Address data Address Address data Address data Address Address data AD7 ...

Page 685: ...dress Address Address Address Address AD15 AD8 High Z Data High Z Data Data High Z Data AD7 AD0 Data High Z Data Data High Z Data Data DPH High Z Parity High Z Parity Parity High Z Parity DPL Parity High Z Parity Parity High Z Parity Parity R Read W Write The CS1 pin is used as the CASH signal output pin RAS When a row address is output from A21 A0 an address strobe signal is output CAS When a col...

Page 686: ...igh Low High Low Low WRL WR R High High High High High High High W Low High Low Low Low Low Low A0 HBS A0 A0 A0 A0 Low High Low A21 A1 Address Address Address Address Address Address Address AD15 AD8 High Z Data High Z Data Data High Z Data AD7 AD0 Data High Z Data Data High Z Data Data DPH High Z Parity High Z Parity Parity High Z Parity DPL Parity High Z Parity Parity High Z Parity Parity R Read...

Page 687: ...Code JEDEC JEITA Mass reference value FP 112 Conforms 2 4 g Dimension including the plating thickness Base material dimension 0 10 23 2 0 3 0 32 0 08 0 65 1 6 0 8 0 3 0 17 0 05 3 05 Max 23 2 0 3 84 57 56 29 112 1 28 20 85 2 70 0 8 0 13 M 0 10 0 15 0 10 1 23 0 30 0 06 0 15 0 04 Unit mm Figure C 1 Package Dimensions FP 112 ...

Page 688: ...ms 0 5 g Dimension including the plating thickness Base material dimension 16 0 0 2 14 0 07 0 10 0 5 0 1 16 0 0 2 0 4 0 10 0 10 1 20 Max 0 17 0 05 0 8 90 61 1 30 91 120 31 60 M 0 17 0 05 1 0 1 00 1 2 0 15 0 04 0 15 0 04 Unit mm Figure C 2 Package Dimensions TFP 120 ...

Page 689: ...654 ...

Page 690: ...ptember 1994 6th Edition September 2002 Published by Business Operation Division Semiconductor Integrated Circuits Hitachi Ltd Edited by Technical Documentation Group Hitachi Kodaira Semiconductor Co Ltd Copyright Hitachi Ltd 1994 All rights reserved Printed in Japan ...

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