85
6.2.2
Break Address Mask Register (BAMR)
The two break address mask registers—break address mask register H (BAMRH) and break
address mask register L (BARML)—together form a single group. Both are 16-bit read/write
registers. BAMRH determines which of the bits in the break address set in BARH are masked.
BAMRL determines which of the bits in the break address set in BARL are masked. A reset
initializes BAMRH and BARML to H'0000. They are not initialized in standby mode.
BAMRH: Break address mask register H.
Bit:
15
14
13
12
11
10
9
8
Bit name:
BAM31
BAM30
BAM29
BAM28
BAM27
BAM26
BAM25
BAM24
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
Bit name:
BAM23
BAM22
BAM21
BAM20
BAM19
BAM18
BAM17
BAM16
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
•
BAMRH bits 15–0 (Break Address Mask 31–16 (BAM31–BAM16)): BAM31–BAM16
specify whether bits BA31–BA16 of the break address set in BARH are masked or not.
BAMRL: Break address mask register L.
Bit:
15
14
13
12
11
10
9
8
Bit name:
BAM15
BAM14
BAM13
BAM12
BAM11
BAM10
BAM9
BAM8
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
Bit name:
BAM7
BAM6
BAM5
BAM4
BAM3
BAM2
BAM1
BAM0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
•
BAMRL bits 15–0 (Break Address Mask 15–0 (BAM15–BAM0)): BAM15–BAM0 specify
whether bits BA15–BA0 of the break address set in BARH are masked or not.
Bits 15–0: BAMn
Description
0
Break address bit BAn is included in the break condition (Initial value)
1
Break address bit BAn is not included in the break condition
n = 31–0
Summary of Contents for HD6417032
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Page 525: ...490 CK RAS CAS TRp TRc TRcc tRASD1 tRASD2 tCASD3 tCASD2 TRr tCSR Figure 20 18 Self Refresh ...
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