GigaDevice Semiconductor GD32F20 Series, Руководство пользователя

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GD32F20x User Manual
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3. IO space: Both byte and half-word AHB access are supported, in IO space memory
access, EXMC_NIORD and EXMC_NIOWR act as the read and write enable signal
respectively.
25.3.6. SDRAM controller
Characteristics

Two independent SDRAM devices

8-,16- or 32-bit data bus width

Up to 13-bits Row Address, 11-bits Column Address and 2-bits internal banks address

Supported memory size: 4x16Mx32bit(256 MB), 4x16Mx16bit (128 MB) and 4x16Mx8bit
(64 MB)

AHB Word, half-word and byte access

Independent Chip Select control for each memory device

Independent configuration for each memory device

Write enable and byte lane select outputs

Automatic row and bank boundary management

Multi-device Ping-Pong access

SDRAM clock configured as fHCLK/2 or fHCLK /3

Programmable timing parameters

Automatic Refresh operation with programmable Refresh rate

SDRAM power-up initialization by software

CAS latency of 1,2,3

Write Data FIFO with 16 x35-bit depth

Write Address FIFO with 16x31-bit depth

Cacheable Read Data FIFO with 6 x32-bit depth

Cacheable Read address FIFO with 6 x14-bit depth

Adjustable read data sample clock

Self-refresh mode

Power-down mode