GigaDevice Semiconductor GD32F20 Series, Руководство пользователя

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GD32F20x User Manual
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sample read data from external memories. This clock can be helpful when the read data can
’t
be sampled correctly by HCLK. When this clock is enabled, the read data will be firstly stored
in an asynchronous FIFO before returned to the AHB bus. Additional delays of about 2~3
HCLK may be brought into the reading command process.
A clock delay chain module is added after the HCLK input to the signal generator, this delayed
clock is used as the sampling clock of the input data. The delay chain is controlled by the
EXMC_SDRSCTL register, RSEN bit select whether the HCLK output is delay at all, SSCR
bit select whether 1 additional HCLK cycle is added to the total delay, and SDSC select how
many delay cells is add, the number of delay cell could be added is within 0 and 15. The
following diagram shows how delay chain is added.
Figure 25-31. Data sampling clock delay chain
Delay
Cell 2 Delay
Cell 0 Delay
Cell 1 Delay
Cell 15
1 HCLK
Delay
SDSC
SSCR
RSEN
Data Input
Sample Clock
HCLK
SDRAMC can translate AHB single and burst write operation into single memory access.
Write protection must be disabled by resetting WPEN bit in EXMC_SDCTLx register.
SDRAMC always keeps track of the activated row number in order to perform consecutive
write access. If next write location is in the same row or another active row, write access is
proceeded without interruption, else a precharge command is issued to deactivate the current
row, followed by the activation of the row where the next write access is targeted, and then
the write access is performed.
The following diagram shows a write burst access to an inactive row, a row activation
command is issued before write access. If write operations were performed on an active row,
row address strobe is not necessary, only column address strobe is needed.