GD32F20x User Manual
529
Figure 20-12. Programming model for master receiving using Solution A
IDLE
START Condition
Master sends Address
Slave sends Acknowledge
Master sends Header
Slave sends Acknowledge
SCL stretched by master
Slave sends DATA(1)
Master sends Acknowledge
……
(
Data transmission
)
Slave sends DATA(N)
Master DON'T send Ack
Master generates STOP
condition
1) Software initialization
Set ADD10SEND
4) Clear ADD10SEND
Set ADDSEND
4) Clear ADDSEND
Set RBNE
Set RBNE
Read DATA(x)
Set RBNE
5) Read DATA(1)
Slave sends DATA(N-1)
Master sends Acknowledge
Set RBNE
8) Read DATA(N)
I2C Line State
Hardware
Action
Software Flow
2) Set START
Set SBSEND
SCL Strechd
3) Clear SBSEND
SCL stretched by master
4) Set START
Master generates repeated
START condition
Set SBSEND
4) Clear SBSEND
SCL stretched by master
Master sends Header
Slave sends Acknowledge
Set ADDSEND
4) Clear ADDSEND
SCL stretched by master
6) Read DATA(N-1)
7) Clear ACKEN
,
Set STOP
Solution B
1.
First of all, software should enable I2C peripheral clock as well as configure clock related
registers in I2C_CTL1 to make sure correct I2C timing. After enabled and configured,
I2C operates in its default slave state and waits for START condition followed by address
on I2C bus.
2.
Software set START bit requesting I2C to generate a START condition to I2C bus.
3.
After sending a START condition, the I2C hardware sets the SBSEND bit in I2C status
register and enters master mode. Now software should clear the SBSEND bit by reading
I2C_STAT0 and then writing a 7-bit address or header of a 10-bit address toI2C_DATA.
Содержание GD32F20 Series
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Страница 325: ...GD32F20x User Manual 325 15 0 ALRM 15 0 RTC alarm value low ...
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Страница 523: ...GD32F20x User Manual 523 clears AERR bit by writing 0 to it ...