VeEX MPA, User Manual

Page: 766 / 842

Misc Screen
766
LED Status area when selected.
There is no timing signal on the RJ-48 CLK-A Out
port.
The SMA CLB-B Out port is a 10 MHz 75 ohm TTL
clock.
RJ48 CLK A (BITS
1.544 Mbps In/Out) The transmit signals derive their data's timing source from
an external 1.544 Mbps BITS (Building Integrated Timing
Supply) clock input from the
RJ-48 CLK-A port.
Chassis (BITS) option appears in the Transmit Clock
Reference menus, and CLK:BITS displays in the Quick
LED Status area when selected.
RJ48 CLK A (SETS
2.048 Mbps In/Out) The transmit signals derive their data's timing source from
an external 2.048 Mbps SETS (Synchronous Equipment
Timing Source) clock input from the
RJ-48 CLK-A port.
Chassis (SETS) option appears in the Transmit Clock
Reference menus, and CLK:SETS displays in the Quick
LED Status area when selected.
SMA CLK B 1.544 MHz
In/Out The transmit signals derive their data's timing from an
external 1.544 MHz 75 ohm TTL timing source attached to
the
SMA CLK-B In connector.
Chassis (Ext 1.5 MHz) option appears in the Transmit
Clock Reference menus, and CLK:Ext 1.5 MHz displays
in the Quick LED Status area when selected.
The SMA CLB-B Out port is a 1.544 MHz 75 ohm TTL
clock.
SMA CLK B 2.048 MHz
In/Out The transmit signals derive their data's timing from an
external 2.048 MHz 75 Ohm TTL timing source attached
to the
SMA CLK-B In connector.
Chassis (Ext 2 MHz) option appears in the Transmit
Clock Reference menus, and CLK:Ext 2 MHz displays in
the Quick LED Status area when selected.
The SMA CLB-B Out port is a 2.048 MHz 75 ohm TTL
MPA_e_manual_D07-00-129P_RevA00