Renesas V850 Series, User Manual, Page: 383 / 1556

R01UH0336EJ0102 Rev.1.02 Page 383 of 1538
Jul 17, 2014
V850E2/PG4-L Section 11 Data CRC Function A (DCRA)
11.4.2 DCRA Registers Details
(1) DCRAnCIN
―
CRC Input Register
This register holds the input data for the CRC calculation. The effective bit
width used for CRC calculation must be set by DCRAnCTL.DCRAnISZ[1:0].
When data is written to this register, the CRC code is generated.
The CRC calculation is immediately started after the DCRAnCIN register is
written. The DCRAnCOUT register must be initialized, with the initial starting
value, before the first data of the data block is written to the DCRAnCIN
register.
Byte order The byte order in DCRAnCIN depends on the selected CRC generating
function.
• 32-bit Ethernet CRC polynomial generation (DCRAnCTL.DCRAnPOL = 0)
The byte order is LSB (least significant byte) first, means LSB at bit position
7...0 of the DCRAnCIN register.
• 16-bit CCITT CRC polynomial generation (DCRAnCTL.DCRAnPOL = 1)
The byte order is MSB (most significant byte) first, means MSB at bit
position 7...0 of the DCRAnCIN register.
Access This register can be read/written in 32-bit units.
Address <DCRAn_base0> + 00
H
Initial value 0000 0000
H
This register is initialized by any reset sources.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DCRAnCIN[31:16]
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCRAnCIN[15:0]
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Table 11-5 DCRAnCIN Register Contents
Bit Position Bit Name Function
31 to 0 DCRAn
CIN[31:0] Input data for CRC calculation.
The valid bits are:
• For 32-bit effective bit width: DCRAnCIN[31:0]
• For 16-bit effective bit width: DCRAnCIN[15:0]
• For 8-bit effective bit width: DCRAnCIN[7:0]