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R01UH0336EJ0102 Rev.1.02
Page 1437 of 1538
Jul 17, 2014
V850E2/PG4-L
Section 24 Peripheral Interconnection (PIC)
24.4.6.4
Example of Operation
By setting an arbitrary encoder count value to the compare value
(ENCA0CCR1) of the ENCA0 timer and enabling compare match interrupt
(INTENCA0I1) of the ENCA0 timer as the trigger of the pattern switch of timer
TSG20, the control of TSG20 output can be achieved.
In this control method, the encoder counter is cleared by a compare match of
ENCA0CCR0 with the ENCA0 timer value.
It is necessary to set compare value (ENCA0CCR1) at each pattern switch
(each INTENCA0I1 interrupt). It is necessary to match the initial output pattern
of timer TSG20 to the set value of the compare register (ENCA0CCR1) of the
ENCA0 timer before start because clear by Z phase input is not performed.
Switching between normal and reverse rotations of output patterns should be
set with the TS0PSC bit in TS0OPT0.
Figure 24-28
Operation Example of Control Method 1 at Up Count
Note
▲
: Write access with CPU
ENCAnE0 pin
ENCAnE1 pin
INTENCAnI1
interrupt
TSnOPCI0 signal
TSG2nO1 to
TSG2nO6 pins
ENCAnCCR0
register
ENCAnCCR1
register
Pattern 1
Offset
Offset
Offset
Offset
Offset
Offset
Offset
Offset
Offset
0º
60º
120º
180º
240º
300º
0º
60º
120º
Pattern 2
Pattern 3
Pattern 4
Pattern 5
Pattern 6
Pattern 1
Pattern 2
Pattern 3
16-bit
counter
INT
INT
INT
INT
INT
INT
INT
INT
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU