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Renesas V850 Series User Manual Download Page 229

R01UH0336EJ0102 Rev.1.02

Page 229 of 1538

Jul 17, 2014

V850E2/PG4-L

Section 5 DMA Module

5.6 DMAC Function Details

5.6.1

DMAC Transfer Setting Flow

The following figure shows the flow of DMAC transfer settings.

Figure  5-3

DMAC Transfer Setting Flow

Start

Set DTS

DTSnDTE

 ← 

0 (disable DMA transfer)

Set DTCT.

DTCTnMLE

 ← 

1 (multilink enable)

Y

N

N

Y

N 

Y

N

Y

N

Y

N

Y

N

Y

N

Y

Y

N

Y

N

N

Y

N

Y

Set DSA (transfer

source address)

Set DSC

(transfer source chip select)

Set DDA (transfer

destination address)

Set DDC (transfer

destination chip select)

Set DTC

(transfer count)

Set DTCT

(transfer data size, address count direction)

Set DTCC (transfer

count comparison)

Transfer

count match

interrupt

Transfer

count match

interrupt

Transfer

completed

Set DTRS

(software request)

Set DTRS

(except for software request)

Set DTS

DTSnDTE

 ← 

1 (DMA transfer enabled)

Hardware

DMA transfer

request

Software

DMA transfer

request

Set DTRS

(software request)

Set DTRS

(except for software request)

Set DTS

DTSnDTE

 ← 

1 (enable DMA transfer)

Set DTS

DTSnTC

 ← 

0 (TC clear)

Hardware

DMA transfer

request

Transfer

completed

Transfer

completed

Set DTS

DTSnDTE

 ← 

1 (enable DMA transfer)

DTSnSR

 ← 

1 (software request)

Set DTS

DTSnTC

 ← 

0 (TC clear)

Hardware

DMA transfer

request

Transfer

completed

Set DNSA

(next transfer source address)

Set DNSC

(next transfer source chip select)

Set DNDA

(next transfer destination address)

Set DNDC

(next transfer destination chip select)

Set DNTC

(next transfer count)

Set DTS

DTSnDTE

 ← 

1 (DMA transfer enabled)

DTSnSR

 ← 

1 (software request)

Set DNSA

(next transfer source address)

Set DNSC

(next transfer source chip select)

Set DNDC

(next transfer destination chip select)

Set DNTC

(next transfer count)

Set DNDA

(next transfer destination address)

Software DMA

transfer request

Use

Next address

Summary of Contents for V850 Series

Page 1: ...materials including products and product specifications represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp without notice Please review the latest information published by Renesas Electronics Corp through various means including the Renesas Electronics Corp website http www renesas com Cover ...

Page 2: ...e range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges 7 Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as t...

Page 3: ... tools including work benches and floors should be grounded The operator should be grounded using a wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with mounted semiconductor devices 4 Status before initialization Power on does not necessarily define the initial status of a MOS device Immediately after the power source is tur...

Page 4: ... to read this manual It is assumed that the readers of this manual have general knowledge in the fields of electrical engineering logic circuits and microcontrollers To understand the overall functions of the V850E2 PG4 L Read this manual according to the Contents To understand the details of an instruction function See V850E2M Architecture User s Manual available separately All trademarks and reg...

Page 5: ... Port Group Configuration Registers 46 2 3 1 Overview 46 2 3 2 Pin Function Configuration Registers 48 2 3 3 Pin Data Input Output Registers 55 2 3 4 Configuration of Electrical Characteristics Registers 59 2 3 5 Port Register Protection 61 2 4 Port Group Configuration 63 2 4 1 List of Ports and Pins 64 2 5 Functions of Pull Up and Pull Down Resistors 84 2 5 1 Details of Pull Up and Pull Down Resi...

Page 6: ...r 117 Section 3 CPU System Function 118 3 1 Overview 118 3 1 1 Peripheral Protection Unit 120 3 1 2 Important Reminders 124 3 1 3 Timing Supervision Unit 124 3 2 Operation Modes 125 3 2 1 Normal Operation Mode 125 3 2 2 Flash Programming Mode 125 3 2 3 HALT Mode 126 3 3 Address Space 127 3 3 1 CPU Data Address and Physical Program Address Space 127 3 3 2 Program and Data Space 127 3 4 Conditions f...

Page 7: ...terrupt Acknowledgment and Restoring 175 4 4 1 FE Level Non Maskable Interrupt Caused by FENMI Interrupt Request 175 4 4 2 Restore from FE Level Non Maskable Interrupt FENMI 177 4 4 3 FE Level Maskable Interrupt Caused by FEINT Interrupt Request 177 4 4 4 Restore from FE Level Maskable Interrupt FEINT Servicing 179 4 4 5 EI Level Maskable Interrupt Caused by EIINT Interrupt Request 180 4 4 6 Resto...

Page 8: ...ext Destination Address Register H 220 5 5 14 DNDCn n 0 to 7 DMA Next Destination Chip Select Register 221 5 5 15 DTCn n 0 to 7 DMA Transfer Count Register 222 5 5 16 DNTCn n 0 to 7 DMA Next Transfer Count Register 223 5 5 17 DTCCn n 0 to 7 DMA Transfer Count Compare Register 224 5 5 18 DTCTn n 0 to 7 DMA Transfer Control Register 225 5 5 19 DTSn n 0 to 7 DMA Transfer Status Register 227 5 6 DMAC ...

Page 9: ...GA Registers for CLKOUT Function 263 7 6 Single Pin Debugging Clock LPDCLK 267 7 7 WDTA0 Count Clock WDTCLKI 267 7 8 Clock Monitor A CLMAn Function 268 7 8 1 Features of the Clock Monitors CLMAn n 0 1 2 268 7 8 2 CLMA Enable and Start Up Options 270 7 8 3 Functional Overview 270 7 8 4 Functional Description 271 7 8 5 Clock Monitor A Registers 277 Section 8 Reset Controller 282 8 1 Functional Overv...

Page 10: ...elf Diagnostic BIST Skip Function 315 9 4 2 Output of a Toggled Signal during Execution of Self Diagnostic BIST 316 9 5 Self Diagnostic BIST Related Registers 318 9 5 1 Overview of Registers Related to Self Diagnostic BIST 318 9 5 2 Details of Registers Related to Self Diagnostic BIST 319 9 5 3 Procedure for Setting the BSEQ0STCHBT Register 329 9 6 ECC Related Registers 330 9 6 1 Overview of ECC R...

Page 11: ...Overview 394 12 4 2 WDTA Registers Details 395 Section 13 Timer Array Unit B TAUB 397 13 1 TAUB Features 397 13 2 Functional Overview 400 13 2 1 Terms 401 13 3 Functional Description 402 13 3 1 Functional List of Timer Operations 404 13 4 General Operating Procedures 405 13 5 Operation Modes 406 13 6 Concepts of Synchronous Channel Operation 407 13 6 1 Rules 407 13 6 2 Simultaneous Start and Stop ...

Page 12: ...Independent Channel Simultaneous Rewrite Functions 483 13 15 1 Simultaneous Rewrite Trigger Generation Function Type 1 484 13 16 Other Independent Channel Functions 490 13 16 1 External Event Count Function 491 13 16 2 Clock Divide Function 498 13 16 3 TAUBnTTINm Input Position Detection Function 505 13 17 Synchronous Channel Operation Functions 511 13 18 Synchronous PWM Signal Functions Triggered...

Page 13: ... Timing of Operating Modes 641 14 9 1 Interval Timer Mode and Capture Mode 641 14 9 2 Other Operating Modes 642 14 10 TAUJnTTOUTm Output and INTTAUJnIm Generation When Counter Starts or Restarts 643 14 11 TAUJnTTINm Edge Detection 644 14 12 Independent Channel Operation Functions 645 14 12 1 Interval Timer Function 645 14 12 2 TAUJnTTINm Input Interval Timer Function 652 14 12 3 TAUJnTTINm Input P...

Page 14: ...nPTSI0 Pin Abnormal Toggle Detection Flag TSnPTF 804 15 7 9 TSnOPCI0 and TSnOPCI1 Signal Simultaneous Trigger Detection Flag TSnTDF 805 15 7 10 Pattern Phase Difference Detection Flag TSnPPF 806 15 7 11 Timer Output Pattern Flag TSnOPF2 to TSnOPF0 807 15 7 12 Pattern Switch Detection Signal TSnPTE 808 15 8 Interrupt Skipping Function 810 15 8 1 Operation of Interrupt Skipping Function 811 15 8 2 E...

Page 15: ...rison Mode 950 17 4 Registers 953 17 4 1 OS Timer Registers Overview 953 17 4 2 OS Timer Registers in Detail 954 Section 18 Encoder Timer ENCA 964 18 1 ENCA Features 964 18 2 Functional Overview 966 18 2 1 Block Diagram 967 18 3 ENCA Control Registers 968 18 4 Functional Description 983 18 4 1 Timer Counter Operation 983 18 4 2 Up Down Control of Timer Counter 987 18 4 3 Control of Timer Counter C...

Page 16: ...iguration 1054 20 4 Bit Set Clear Functions 1059 20 5 Control Registers 1061 20 5 1 FCN Global Registers 1061 20 5 2 FCN Module Registers 1069 20 5 3 FCN Message Buffer Registers 1089 20 6 CAN Controller Initialization 1099 20 6 1 Initialization of FCN Module 1099 20 6 2 Redefinition of Message Buffer 1099 20 6 3 Transition from Initialization Mode to Operating Mode 1101 20 7 Reception of Message ...

Page 17: ...ve Modes 1163 Section 21 Clocked Serial Interface G CSIG 1170 21 1 CSIG Features 1170 21 2 Functional Overview 1172 21 3 Functional Description 1174 21 3 1 Master Slave Mode 1174 21 3 2 Master Slave Connections 1175 21 3 3 Selection of Serial Communications Clock 1176 21 3 4 Data Transfer Modes 1177 21 3 5 Data length Selection 1178 21 3 6 Serial Data Direction Selection 1180 21 3 7 Communication ...

Page 18: ...ecting the Baud Rate in LIN Communications as a Slave 1269 Section 23 A D Converter 1270 23 1 ADCA Features 1270 23 2 Functional Overview 1273 23 3 Functional Description 1275 23 3 1 Basic Operation 1277 23 3 2 Clock Usage 1278 23 3 3 Channel and Channel Group 1279 23 3 4 A D Conversion Modes 1281 23 3 5 Starting A D Conversion Start Triggers 1285 23 3 6 Stopping A D Conversion Stop Trigger 1287 2...

Page 19: ...1369 24 4 3 High Accuracy Triangle Wave PWM Output Function with Dead Time 1377 24 4 4 Trigger and Pulse Width Measurement Function 1408 24 4 5 Encoder Capture Trigger Selection Function 1422 24 4 6 Two Phase Encoder Control Function Control Method 1 1432 24 4 7 Two Phase Encoder Control Function Control Method 2 1444 24 4 8 Three Phase Encoder Control Function 1455 24 4 9 CAN Time Stamp Function ...

Page 20: ...27 6 7 ESOn Timing 1509 27 6 8 ADCA0TRGn Timing 1510 27 6 9 Timer Timing 1511 27 6 10 CSIGn Timing 1512 27 6 11 UARTHn Timing 1518 27 6 12 CAN Timing 1525 27 6 13 Nexus Interface Timing 1526 27 6 14 LPD Interface 1527 27 6 15 A D Converter Characteristics 1528 27 6 16 POF LVI Characteristics 1533 27 6 17 Flash Memory Programming Characteristics 1535 27 6 18 FLMD0 Pulse Timing Characteristics 1536 ...

Page 21: ...ts instruction bit manipulation instructions and so on In addition the 2 byte length for instructions instructions corresponding to high level languages and other measures improve the efficiency of object code from the C compiler leading to smaller executable programs The product s quick interrupt response including processing by the on chip interrupt controller makes it suitable for advanced real...

Page 22: ...Instruction set V850E2v3 Signed multiplication 32 bits 32 bits 64 bits 1 or 2 CPU clock cycles Saturation calculation instruction with overflow underflow detection 32 bit arithmetic logic shift instruction 1 CPU clock cycle Bit manipulation instructions Loading storing instructions in long short formats Signed load instruction Memory space 512 Mbyte address space common for programs and data On ch...

Page 23: ... unit J TAUJ 4 channels 1 unit Timer unit including 4 independent 32 bit counter channels and a dedicated prescaler TSG2 1 unit Timer unit suitable for motor control Timer pattern buffer TPBA 1 unit Timer unit suitable for duty cycle and period settings Encoder timer ENCA 1 unit Timer unit suitable for 2 phase encoder control OS timer OST 2 units For use by the OS 32 bit free running interval time...

Page 24: ...thesizer Clock output functions Baud rate generator BRG Allows setting of the operating clock frequency to suit the conditions of use Data CRC Data CRC cyclic redundancy checking can be used to verify or generate data streams protected by CRC with different widths in bits for various lengths Safety functions Flash memory ECC error detection RAM ECC error detection Oscillation stop detection Build ...

Page 25: ... WDTA 1 unit 1 unit ENCA 1 unit 1 unit TPBA 1 unit 1 unit TAPA 2 units 2 units PIC 1 unit 1 unit Serial interfaces Synchronous asynchronous UARTH 2 channels 2 channels CSIG 2 channels 2 channels CAN number of messages 2 channels 32 msg 2 channels 32 msg A D converter Resolution 12 bits 12 bits Input channels 18 channels 6 S H 12 other 18 channels 6 S H 12 other Interrupts External 10 10 Internal 1...

Page 26: ...o 5 5 V Internal regulator Included Included For interfaces 3 0 V to 5 5 V 3 0 V to 5 5 V For A D converter 4 2 V 5 5 V 4 2 V 5 5 V For reprogramming flash memory 3 0 V to 5 5 V 3 0 V to 5 5 V Package 100 pins LQFP 0 5 mm pitch 14 14 mm 1 4 mm thick 100 pins LQFP 0 5 mm pitch 14 14 mm 1 4 mm thick Series Name V850E2 PG4 L Product PD70F4154 PD70F4155 ...

Page 27: ... of application refer to the following document issued by Renesas NEC Semiconductor Device Quality Standards document reference number C11531J The former company name remains in the document but it is still a valid Renesas document Product Name Package On Chip ROM Quality Standard Operating Ambient Temperature TA External Oscillator Maximum Operating Frequency PD70F4154GC A2 UEU AX 100 pin 0 5 mm ...

Page 28: ...0 6 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 7 6 8 6 9 6 0 7 1 7 2 7 3 7 4 7 77 76 78 79 80 81 82 83 84 85 87 86 88 89 90 91 92 93 94 95 97 96 98 99 100 X2 X1 P3_4 CSIG1SC P3_3 CSIG1SO TPB0O P2_6 TAUB0I13 TAUB0O13 TAUB0I12 TAUB0O12 P2_5 TAUB0I11 TAUB0O11 TAUB0I10 TAUB0O10 P2_4 TAUB0I9 TAUB0O9 TAUB0I8 TAUB0O8 TAUB0O14 P2_3 TAUB0I7 TAUB0O7 TAUB0I6 TAUB0O6 TAUB0O12 P2_2 TAUB0I5 TAUB0O5 TAUB0I4 TAUB0O4 TAU...

Page 29: ...V 16 DCUEVTO RESETOUT O 17 DCUTDO JP0_1 FPDT I O 18 DCUTRDY RESETOUT JP0_5 I O 19 DCUTCK JP0_2 FPCK I O 20 DCUTMS JP0_3 I O 21 DCUTDI FPDR LPDIO I O 22 DCUTRST I 23 RESET I 24 EVSS G 25 EVDD V 26 P1_0 NMI CLKOUT OSTM1O TSG20O7 I O 27 P1_1 TAUJ0I0 TAUJ0O0 TSG20O1 I O 28 P1_2 TAUJ0I1 TAUJ0O1 TSG20O2 I O 29 P1_3 TAUJ0I2 TAUJ0O2 TSG20O3 I O 30 P1_4 TAUJ0I3 TAUJ0O3 TSG20O4 I O 31 P1_5 TSG20O5 I O 32 P1...

Page 30: ...IG1SI I O 49 P3_3 CSIG1SO TPB0O I O 50 P3_4 CSIG1SC I O 51 P3_5 INTP2 FCN1TX I O 52 P3_6 FCN1RX I O 53 P4_0 URTH1RXD INTP1 FCN0TX I O 54 P4_1 URTH1TXD TSG20PTSI0 ENCA0E0 FCN0RX I O 55 P8_0 TAUB0O15 OSTM1O TGLOUT I O 56 FLMD1 I 57 FLMD0 I 58 EVSS G 59 EVDD V 60 EVDD V 61 EVSS G 62 P4_2 CSIG1SI TSG20PTSI1 ENCA0E1 OSTM1O I O 63 P4_3 CSIG1SO TSG20PTSI2 ENCA0EC OSTM0O URTH1CTS I O 64 VSS G 65 VDD V 66 ...

Page 31: ...CA0I11 I 85 ADCA0I12 I 86 ADCA0I13 I 87 ADCA0I14 I 88 ADCA0I15 I 89 ADCA0I16 I 90 ADCA0I17 I 91 ADCA0I18 I 92 P5_0 URTH0RXD INTP0 I O 93 P5_1 URTH0TXD ADCA0TRG0 INTP3 I O 94 P5_2 INTP2 URTH0SC ADCA0TRG1 INTP4 I O 95 P5_3 ADCA0TRG0 INTP3 URTH0CTS ADCA0TRG2 INTP5 I O 96 VDD V 97 VSS G 98 EVDD V 99 EVSS G 100 ERROROUT O Table 1 1 List of Pin Numbers and Names 3 3 Pin Number Pin Name I O ...

Page 32: ...O Nexus event output DCUTCK Nexus input clock DCUTDI Nexus input DCUTDO Nexus output DCUTMS Nexus mode select DCUTRDY Nexus ready output DCUTRST Nexus reset input ENCA0E0 ENCA0E1 Timer encoder count pulse input ENCA0EC Timer encoder clear input ERROROUT Error output signal ESO0 ESO2 Timer output compulsion stop input EVDD I O CODE Flash DATA Flash Memory power supply EVSS I O CODE Flash DATA Flash...

Page 33: ...citor for internal voltage regulator RESET Reset input RESETOUT RESETOUT Reset output TAUB0I0 TAUB0I15 TAUJ0I0 TAUJ0I3 Timer input TAUB0O0 TAUB0O15 TAUJ0O0 TAUJ0O3 Timer output TGLOUT Toggle signal output TPB0O Timer pattern buffer pulse output TSG20O1 TSG20O7 Timer pulse output TSG20PTS10 TSG20PTS12 Timer pattern input URTH0RXD URTH1RXD Receive data URTH0TXD URTH1TXD Transmit data URTH0SC URTH1SC...

Page 34: ... REGC0 CRC0 DCUTRDY Nexus DCUTDI DCUTDO DCUTCK DCUTMS DCUTRST DCUEVTO debug 1pin debug RESETOUT RESETOUT LPDIO CLKOUT Clock Output BRG Timers TAUJ0 TSG20 TAUB0 TPBA0 TAPA0 TAPA2 Hi z ctl OST0 to OST1 TSG20O7 1 WDTA Peripheral Interconnection FCN0TX FCN0RX CAN0 RAM FCN1TX FCN1RX CAN1 RAM CSIGnSO CSIGnSC CSIGnSI CSIG0 to CSIG1 CSIGnRYI CSIGnRYO V850E2M Master CPU Debug SPF DMA Code Flash 384K Data F...

Page 35: ... data flash memory Memory capacity is given in the following table The CPU is able to access ROM in a single clock cycle when fetching instructions 4 RAM Mappings of RAM are listed below 5 Interrupt Controller INTC This module handles peripheral I O and external hardware interrupt requests INTP9 0 These interrupts can be prioritized at 16 levels to control multiple forms of handling for the interr...

Page 36: ...s TAUB TSG2 9 Peripheral Interconnection PIC Interlocking operation is available by connecting to a timer for simultaneous starting or peripheral I O 10 Serial Interface SIO Serial interfaces include synchronous asynchronous interface H UARTH clocked serial interface CSIG and CAN UARTH executes data transfer through the URTHnTXD and URTHnRXD pins n 0 1 CSIG executes data transfer through the CSIGn...

Page 37: ...put TSG2 TSG20 output Port 2 Bitwise I O Timer array unit B TAUB0 I O Serial interface CSIG0 CSIG1 I O Serial interface UARTH1 I O Port 3 Bitwise I O External interrupt INTP1 INTP2 input Serial interface CSIG1 I O Serial interface UARTH1 I O Serial interface CAN1 I O Timer pattern buffer TPBA0 output Port 4 Bitwise I O External interrupt NMI INTP1 INTP6 to INTP9 input Serial interface CAN0 output ...

Page 38: ... n for example PMCn for the port mode control register of Pn Register addresses All port n register addresses are given as address offsets from the individual base addresses PORTn_base0 and PORTn_base1 The base addresses PORTn_base0 and PORTn_base1 are specified in the following table Table 2 1 Port Groups Port Groups Product name µPD70F4154 µPD70F4155 Number of port groups 7 Name P0_0 P0_3 P1_0 P...

Page 39: ...to several modes for use The pin function allocated to a pin depends on the selected mode Port group Denotes a group of pins The pins of a port group have a common set of port mode control registers Port mode Port A pin in port mode works as a general purpose input output pin It is then called port The corresponding name is Pn_m For example P0_1 denotes port 1 of port group 0 It is referenced as p...

Page 40: ...trolled by the hardware for the alternative function so software settings are not required for this An overview of the register settings is given in the tables below Note The input buffer must be enabled PIBCn PIBCn_m 1 Note X Invalid setting If a pin is operated in an alternative mode PMCn PMCn_m 1 one out of up to four different alternative functions can be selected by the PFCn and PFCEn registe...

Page 41: ... the edges on the URTH0RXD and URTH1RXD pins respectively in the case of the multiplexed pins for URTH0RXD INTP0 and URTH1RXD INTP1 Caution 2 Do not use the same alternative function pin with multiple port pins For example if ADCA0TRG0 INTP3 is in use ALT_IN1 of P0_2 ALT_IN4 of P5_1 and so on Table 2 4 Alternative Mode Selection Overview PMCn PMCn_m 1 Function Register I O PIPC PM PFCE PFC Alterna...

Page 42: ...on Pin Port Pin Control Mode ADCA0TRG0 INTP3 P0_2 ALT IN1 P5_1 ALT IN4 P5_3 ALT IN2 ADCA0TRG1 INTP4 P0_1 ALT IN1 P5_2 ALT IN4 ADCA0TRG2 INTP5 P0_0 ALT IN1 P5_3 ALT IN4 ESO0 INTP6 P4_4 ALT IN4 ESO2 INTP8 P4_6 ALT IN4 URTH0RXD INTP0 P0_0 ALT IN4 P1_7 ALT IN4 P5_0 ALT IN3 URTH1RXD INTP1 P3_0 ALT IN3 P4_0 ALT IN1 TSG20PTSI0 ENCA0E0 P4_1 ALT IN2 TSG20PTSI1 ENCA0E1 P4_2 ALT IN2 TSG20PTSI2 ENCA0EC P4_3 A...

Page 43: ...registers connected to the ports are enabled Also read the registers twice and discard the value read the first time Note 1 If PBDCn_m 1 the Pn_m pin level is read via PPRn_m Note 2 When the PPRn_m bit is read while PMCn_m 1 for the internal signal output of an alternative function the level read is not that on the Pn_m pin but the level of the internal signal for the alternative function The cont...

Page 44: ...n bit set reset not An indirect way to set Pn_m 1 reset Pn_m 0 or invert Pn_m Pn_m a Pn bit is possible using the following two registers Port set reset register PSRn If the bit PSRn PSRn_ m 16 1 the value of bit PSRn PSRn_m determines the value of Pn Pn_m Thus Pn_m can be set reset without a direct write to Pn Port NOT register PNOTn Setting PNOTn PNOTn_m 1 inverts the bit Pn Pn_m without a direc...

Page 45: ...logic diagram of the port control function Caution This figure shows the logics for reference not show the actual circuits 0 1 1 0 0 1 P 0 0 1 1 0 1 1 0 1 4 2 3 ALT_OUT ALT_OUT control control ALT_IN ALT_IN 1 4 2 3 Enable Enable PUn_m PBDCn_m PIBCn_m PIPCn_m PODCn_m PPRn_m PNOTn_m PPCMDn_m PFCn_m PFCEn_m PPROTSn_m PMn_m PMSRn_m PMCn_m PMCSRn_m Pn_m PSRn_m ...

Page 46: ...e Shortcut Address Port input buffer control register PIBCn PORTn_base0 4000H n 4 Port bi direction control register PBDCn PORTn_base0 4100H n 4 Port IP control register PIPCn PORTn_base0 4200H n 4 Pull up option register PUn PORTn_base0 4300H n 4 Port open drain control register PODCn PORTn_base0 4500H n 4 Port register protection command register PPCMDn PORTn_base0 4C00H n 4 Port protection stat...

Page 47: ... registers include bits to which no function has been allocated Unless there is a specific indication to the contrary do not write values other than the initial values to such bits Operation is not guaranteed if other values are set in these bits Table 2 8 JTAG Port Group Configuration Registers Register Name Shortcut Address JTAG port register JP0 FF44 0000H JTAG port set reset register JPSR0 FF4...

Page 48: ...t units Address Refer to Table 2 7 Port Group Configuration Registers Initial value 0000H A reset from any source will initialize the bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PMCn_15 PMCn_14 PMCn_13 PMCn_12 PMCn_11 PMCn_10 PMCn_9 PMCn_8 PMCn_7 PMCn_6 PMCn_5 PMCn_4 PMCn_3 PMCn_2 PMCn_1 PMCn_0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Table 2 9 PMCn Register Contents Bit Posi...

Page 49: ...S Rn_28 PMCS Rn_27 PMCS Rn_26 PMCS Rn_25 PMCS Rn_24 PMCS Rn_23 PMCS Rn_22 PMCS Rn_21 PMCS Rn_20 PMCS Rn_19 PMCS Rn_18 PMCS Rn_17 PMCS Rn_16 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PMCS Rn_15 PMCS Rn_14 PMCS Rn_13 PMCS Rn_12 PMCS Rn_11 PMCS Rn_10 PMCS Rn_9 PMCS Rn_8 PMCS Rn_7 PMCS Rn_6 PMCS Rn_5 PMCS Rn_4 PMCS Rn_3 PMCS Rn_2 PMCS Rn_1 PM...

Page 50: ...ode of the serial interface PMn_m 0 for master mode and PMn_m 1 for slave mode setting the corresponding bit in the PIPCn register to 0 does not create a problem TAUB0O10 to TAUB0O15 TSG20O1 to TSG20O6 target pins for Hi Z control When a pin is to be used as a timer output pin for the timer option function TAPA and Hi Z control is not to be applied setting the corresponding bit in the PIPCn regist...

Page 51: ...t mode PMCn PMCn_m 0 and PMn PMn_m 1 the input buffer must be enabled PIBCn PIBCn_m 1 Note 2 By default PMn_m it specifies the I O direction in port mode PMCn PMCn_m 0 and alternative mode PMCn PMCn_m 1 since PIPCn PIPCn_m 0 after reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PMn_ 15 PMn_ 14 PMn_ 13 PMn_ 12 PMn_ 11 PMn_ 10 PMn_ 9 PMn_ 8 PMn_ 7 PMn_ 6 PMn_ 5 PMn_ 4 PMn_ 3 PMn_ 2 PMn_ 1 PMn_ 0 R W R W...

Page 52: ... PMSR n_29 PMSR n_28 PMSR n_27 PMSR n_26 PMSR n_25 PMSR n_24 PMSR n_23 PMSR n_22 PMSR n_21 PMSR n_20 PMSR n_19 PMSR n_18 PMSR n_17 PMSR n_16 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PMSR n_15 PMSR n_14 PMSR n_13 PMSR n_12 PMSR n_11 PMSR n_10 PMSR n_9 PMSR n_8 PMSR n_7 PMSR n_6 PMSR n_5 PMSR n_4 PMSR n_3 PMSR n_2 PMSR n_1 PMSR n_0 R W R W...

Page 53: ...l value 0000H A reset from any source will initialize the bits Caution Settings in this register are overruled in bi directional mode PBDCn PBDCn_m 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PIBC n_15 PIBC n_14 PIBC n_13 PIBC n_12 PIBC n_11 PIBC n_10 PIBC n_9 PIBC n_8 PIBC n_7 PIBC n_6 PIBC n_5 PIBC n_4 PIBC n_3 PIBC n_2 PIBC n_1 PIBC n_0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R ...

Page 54: ...ctions input output must be specified by PMn PMn_m n 0 to 5 8 Access Readable and writable in 16 bit units Address Refer to Table 2 7 Port Group Configuration Registers Initial value 0000H A reset from any source will initialize the bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PFC n_15 PFC n_14 PFC n_13 PFC n_12 PFC n_11 PFC n_10 PFC n_9 PFC n_8 PFC n_7 PFC n_6 PFC n_5 PFC n_4 PFC n_3 PFC n_2 PFC n_...

Page 55: ...ll initialize the bits Caution To use the data consistency checking function of the CSIG module set the bit in the PBDCn register that is allocated to the CSIGnSO pin to 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PBDC n_15 PBDC n_14 PBDC n_13 PBDC n_12 PBDC n_11 PBDC n_10 PBDC n_9 PBDC n_8 PBDC n_7 PBDC n_6 PBDC n_5 PBDC n_4 PBDC n_3 PBDC n_2 PBDC n_1 PBDC n_0 R W R W R W R W R W R W R W R W R W R W ...

Page 56: ...n 16 bit units Address Refer to Table 2 7 Port Group Configuration Registers Initial value 0000H A reset from any source will initialize the bits Note The bits of this register can be manipulated by different means refer to Section 2 2 3 Pin Data Input Output 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PPR n_15 PPR n_14 PPR n_13 PPR n_12 PPR n_11 PPR n_10 PPR n_9 PPR n_8 PPR n_7 PPR n_6 PPR n_5 PPR n_4 ...

Page 57: ...Refer to Table 2 7 Port Group Configuration Registers Initial value 0000H A reset from any source will initialize the bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PNOT n_15 PNOT n_14 PNOT n_13 PNOT n_12 PNOT n_11 PNOT n_10 PNOT n_9 PNOT n_8 PNOT n_7 PNOT n_6 PNOT n_5 PNOT n_4 PNOT n_3 PNOT n_2 PNOT n_1 PNOT n_0 W W W W W W W W W W W W W W W W Table 2 20 PNOTn Register Contents Bit Position Bit Name ...

Page 58: ... PSR n_31 PSR n_30 PSR n_29 PSR n_28 PSR n_27 PSR n_26 PSR n_25 PSR n_24 PSR n_23 PSR n_22 PSR n_21 PSR n_20 PSR n_19 PSR n_18 PSR n_17 PSR n_16 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PSR n_15 PSR n_14 PSR n_13 PSR n_12 PSR n_11 PSR n_10 PSR n_9 PSR n_8 PSR n_7 PSR n_6 PSR n_5 PSR n_4 PSR n_3 PSR n_2 PSR n_1 PSR n_0 R W R W R W R W R W...

Page 59: ...al value 0000H A reset from any source will initialize the bits Caution The pull up resistor has no effect when the pin is operated in output mode 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PUn_ 15 PUn_ 14 PUn_ 13 PUn_ 12 PUn_ 11 PUn_ 10 PUn_ 9 PUn_ 8 PUn_ 7 PUn_ 6 PUn_ 5 PUn_ 4 PUn_ 3 PUn_ 2 PUn_ 1 PUn_ 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Table 2 22 PUn Register Contents ...

Page 60: ...ration Registers Initial value 0000 0000H A reset from any source will initialize the bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PODC n_31 PODC n_30 PODC n_29 PODC n_28 PODC n_27 PODC n_26 PODC n_25 PODC n_24 PODC n_23 PODC n_22 PODC n_21 PODC n_20 PODC n_19 PODC n_18 PODC n_17 PODC n_16 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...

Page 61: ... of the write sequence for a protected port register n 2 Access Readable in 8 bit units Values written are ignored Address Refer to Table 2 7 Port Group Configuration Registers Initial value 00H A reset from any source will initialize the bits 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 W W W W W W W W Table 2 24 PPCMDm Register Contents Bit Position Bit Name Function 7 to 0 Command capable of writing to prot...

Page 62: ...ep 2 Write the set value in a 32 bit unit to a protected register this will not update the register Step 3 Write the inverse of the set value in a 32 bit unit to the same protected register this will not update the register Step 4 Again write the original set value in a 32 bit unit to the same protected register this will update the register Step 5 Check if the value in the PPROTSn PPROTSn_0 bit i...

Page 63: ...ws an overview of the port groups See Table 2 26 List of Port Groups Table 2 30 List of States of Port Pins shows the changes in pin function when this microcontroller is reset or is at each stand by mode In each sub section the configuration register settings of each port group are listed see Section 2 6 Port 0 and subsequent passages ...

Page 64: ...t output port Inputs and outputs are specifiable in 1 bit units P1_1 TAUJ0I0 TAUJ0O0 TSG20O1 P1_2 TAUJ0I1 TAUJ0O1 TSG20O2 P1_3 TAUJ0I2 TAUJ0O2 TSG20O3 P1_4 TAUJ0I3 TAUJ0O3 TSG20O4 P1_5 TSG20O5 P1_6 TSG20O6 P1_7 CSIG0SI URTH0RXD TSG20O7 INTP0 P1_8 TPB0O CSIG0SO URTH0TXD P1_9 CSIG0SC URTH0SC P2 P2_0 TAUB0I1 TAUB0O1 TAUB0I0 TAUB0O0 URTH1SC CSIG0RYI Input output port Inputs and outputs are specifiable...

Page 65: ..._5 ADCA0CNV2 INTP7 CSIG1RYO P4_6 ADCA0CNV1 ESO2 INTP8 P4_7 NMI ADCA0CNV0 INTP9 P5 P5_0 URTH0RXD INTP0 Input output port Inputs and outputs are specifiable in 1 bit units P5_1 URTH0TXD ADCA0TRG0 INTP3 P5_2 INTP2 URTH0SC ADCA0TRG1 INTP4 P5_3 ADCA0TRG0 INTP3 URTH0CTS ADCA0TRG2 INTP5 P8 P8_0 TAUB0O15 OSTM1O Input output port Inputs and outputs are specifiable in 1 bit units TGLOUT output JP0 1 JP0_1 J...

Page 66: ...t Functions 2 List of Pins Other than Port Pins Table 2 27 List of Pins Other than Port Pins 1 6 Pin Name Function INTC NMI Input for non maskable external interrupt requests INTP0 Input for maskable external interrupt requests INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTP7 INTP8 INTP9 ...

Page 67: ...UB0I2 TAUB0I3 TAUB0I4 TAUB0I5 TAUB0I6 TAUB0I7 TAUB0I8 TAUB0I9 TAUB0I10 TAUB0I11 TAUB0I12 TAUB0I13 TAUB0I14 TAUB0I15 TAUB0O0 Output for the TAUB0 channel TAUB0O1 TAUB0O2 TAUB0O3 TAUB0O4 TAUB0O5 TAUB0O6 TAUB0O7 TAUB0O8 TAUB0O9 TAUB0O10 TAUB0O11 TAUB0O12 TAUB0O13 TAUB0O14 TAUB0O15 Table 2 27 List of Pins Other than Port Pins 2 6 Pin Name Function ...

Page 68: ...ter TPB0 TPB0O Pulse output from the TPB0 timer pattern buffer OST0 OSTM0O Output for OS timer 0 OST1 OSTM1O Output for OS timer 1 TAPA ESO0 Input for forcibly stopping timer output ESO2 BRG CLKOUT Clock output CAN0 FCN0TX Output for data transmission from CAN0 FCN0RX Input for data reception by CAN0 CAN1 FCN1TX Output for data transmission from CAN1 FCN1RX Input for data reception by CAN1 UARTH0 ...

Page 69: ... CSIG0SC Input or output for the CSIG0 serial clock CSIG0SI Input for serial data reception by CSIG0 CSIG0SO Output for serial data transmission from CSIG0 CSIG0RYI Input for serial ready busy from CSIG0 CSIG0RYO Output for serial ready busy from CSIG0 CSIG1 CSIG1SC Input or output for the CSIG1 serial clock CSIG1SI Input for serial data reception by CSIG1 CSIG1SO Output for serial data transmissi...

Page 70: ... ADCA0CNV1 ADCA0CNV2 AVDD0 Source of positive power supply for the A D converter AVSS0 Ground potential for the A D converter AVREF0P Source of reference power supply for the A D converter AVREF0M Reference ground potential for the A D converter SGA ERROROUT Output for error signal from the safety guardian Nexus DCUTCK 1 Input for the debugger clock DCUTDI Input for debugger data DCUTDO 1 Output f...

Page 71: ...positive power supply for the OSC OSCVSS Ground potential for the OSC VDD Source of positive power supply for the on chip regulator VSS Ground potential for the on chip regulator EVDD Source of positive power supply for the external pins code flash and data flash EVSS Ground potential for external pins code flash and data flash REGC0 Pin for connection of the capacitor for the on chip regulator RE...

Page 72: ...n_m 1 in port mode PMCn_m 0 and connect them to on board pull up resistors PUn_m 1 Pins shall be left open circuit P1_1 TAUJ0I0 TAUJ0O0 TSG20O1 P1_2 TAUJ0I1 TAUJ0O1 TSG20O2 P1_3 TAUJ0I2 TAUJ0O2 TSG20O3 P1_4 TAUJ0I3 TAUJ0O3 TSG20O4 P1_5 TSG20O5 P1_6 TSG20O6 P1_7 CSIG0SI URTH0RXD TSG20O7 INTP0 P1_8 TPB0O CSIG0SO URTH0TXD P1_9 CSIG0SC URTH0SC P2 P2_0 TAUB0I1 TAUB0O1 TAUB0I0 TAUB0O0 URTH1SC CSIG0RYI T...

Page 73: ...CSIG1SO TSG20PTSI2 ENCA0EC OSTM0O URTH1CTS P4_4 CSIG1SC URTH1RTS ESO0 INTP6 CSIG0RYO P4_5 ADCA0CNV2 INTP7 CSIG1RYO P4_6 ADCA0CNV1 ESO2 INTP8 P4_7 NMI ADCA0CNV0 INTP9 P5 P5_0 URTH0RXD INTP0 Type5 W Set the pins as inputs PMn_m 1 in port mode PMCn_m 0 and connect them to on board pull up resistors PUn_m 1 Pins shall be left open circuit P5_1 URTH0TXD ADCA0TRG0 INTP3 P5_2 INTP2 URTH0SC ADCA0TRG1 INTP...

Page 74: ..._m 1 Pins shall be left open circuit JP0_2 Type TCK JP0_3 Type TMS JP0_5 Type RDY Note 1 It is alternative with Nexus interface When OPBT0 FOP31 0 JTAG ports are enabled When OPBT0 FOP31 1 Nexus interface is enabled Table 2 28 Handling of Unused Port Pins 3 3 Port Group Name Port Name Alternative Mode 1 Alternative Mode 2 Alternative Mode 3 Alternative Mode 4 Input Output Circuit Type Handling of ...

Page 75: ... Type TCK Leave DCUTDI Type LPDIO DCUTDO 1 Type TDO DCUTMS 1 Type TMS DCUTRDY 1 Type RDY DCUEVTO Type3 ERROROUT Type ERROROUT Leave this pin X1 Must be used X2 ADCA0I1 Type7 When the ADC is not in use directly connect the pins to EVDD or EVSS Unused channels when the ADC is in use directly connect the pins to AVDD0 or AVSS0 ADCA0I2 ADCA0I3 ADCA0I4 ADCA0I5 ADCA0I6 ADCA0I7 ADCA0I8 ADCA0I9 ADCA0I10 A...

Page 76: ...s VDD Must be used VSS OSCVDD OSCVSS EVDD EVSS REGC0 REGC1 Note 1 It is alternative with JTAG ports When OPBT0 FOP31 0 JTAG ports are enabled When OPBT0 FOP31 1 Nexus interface is enabled Table 2 29 Handling of Unused Pins Other than Port Pins 2 2 Pin Name Input Output Circuit Type Handling ...

Page 77: ...ta Type 7 IN P ch N ch VREF threshold voltage Comparator Type 2 1 IN Schmitt triggered input with hysteresis characteristics TTL input Type 2 X IN IN Type 2 W VDD Pull up enable Pull down enable Vss P ch N ch Schmitt triggered input with hysteresis characteristics IN OUT Type 5 W VDD VDD Pull up enable Output disable Input enable Data P ch P ch N ch ...

Page 78: ...tput disable Input enable Data P ch P ch N ch IN OUT Type TCK TMS VDD VDD Pull up enable Output disable Data Data input enable TTL input Control signal Control input enable Data P ch P ch N ch OUT VDD Output disable Input enable Data P ch N ch Type ERROROUT IN OUT Type LPDIO output disable data data input enable TTL input control signal control input enable data N ch ...

Page 79: ... operate P1_1 TAUJ0I0 TAUJ0O0 TSG20O1 P1_2 TAUJ0I1 TAUJ0O1 TSG20O2 P1_3 TAUJ0I2 TAUJ0O2 TSG20O3 P1_4 TAUJ0I3 TAUJ0O3 TSG20O4 P1_5 TSG20O5 P1_6 TSG20O6 P1_7 CSIG0SI URTH0RXD TSG20O7 INTP0 P1_8 TPB0O CSIG0SO URTH0TXD P1_9 CSIG0SC URTH0SC P2 P2_0 TAUB0I1 TAUB0O1 TAUB0I0 TAUB0O0 URTH1SC CSIG0RYI Hi Z Hi Z Hi Z Port output Retained Port input Non sampling Alternative output can operate Alternative inpu...

Page 80: ... Alternative input can operate P5_1 URTH0TXD ADCA0TRG0 INTP3 P5_2 INTP2 URTH0SC ADCA0TRG1 INTP4 P5_3 ADCA0TRG0 INTP3 URTH0CTS ADCA0TRG2 INTP5 P8 P8_0 TAUB0O15 OSTM1O Hi Z Hi Z Hi Z Port output Retained Port input Non sampling Alternative output can operate Alternative input can operate JP0 1 JP0_1 Hi Z Hi Z Hi Z Port output Retained Port input Non sampling JP0_2 Hi Z Hi Z Hi Z JP0_3 Hi Z Hi Z Hi Z...

Page 81: ...peration Operation Operation X2 Operation Operation Operation Operation Note 1 For input of the high level to DCUTRST confirm that the low level is being output from DCUTRDY and execute the Nexus start up sequence beforehand See Section 25 3 Notes on On Chip Debugging Note 2 The output on DCUEVTO is at the low level while the internal reset signal CPURES is at the low level If DCUTRST is set to th...

Page 82: ...CA0I6 ADCA0I7 ADCA0I8 ADCA0I9 ADCA0I10 ADCA0I11 ADCA0I12 ADCA0I13 ADCA0I14 ADCA0I15 ADCA0I16 ADCA0I17 ADCA0I18 AVREF0P AVREF0M AVDD0 AVSS0 VDD VSS OSCVDD OSCVSS EVDD EVSS REGC0 REGC1 Table 2 31 List of States of Pins Other than Port Pins 2 2 Pin Name Reset BIST for Self diagnosis is Running Immediately after Releasing the CPU Core from Reset Halt Mode ...

Page 83: ...rt pins are in the Hi Z state during an external reset in on chip debugging mode Self diagnosis BIST is not executed after release from an external reset in on chip debugging mode 2 Pin states in flash memory programming mode are identical to those in single chip mode Self diagnosis BIST is not executed in flash memory programming mode ...

Page 84: ... Group Name Port Name Alternative Mode 1 Alternative Mode 2 Alternative Mode 3 Alternative Mode 4 Pull Up Resistor Pull Down Resistor P0 P0_0 ADCA0TRG2 INTP5 URTH0RXD INTP0 Software pull up initial value off P0_1 ADCA0TRG1 INTP4 URTH0TXD P0_2 ADCA0TRG0 INTP3 URTH0SC P0_3 CLKOUT URTH0CTS P1 P1_0 NMI CLKOUT OSTM1O TSG20O7 Software pull up initial value off P1_1 TAUJ0I0 TAUJ0O0 TSG20O1 P1_2 TAUJ0I1 T...

Page 85: ...14 TAUB0O14 P3 P3_0 URTH1RXD INTP1 Software pull up initial value off P3_1 URTH1TXD P3_2 CSIG1SI P3_3 CSIG1SO TPB0O P3_4 CSIG1SC P3_5 INTP2 FCN1TX P3_6 FCN1RX P4 P4_0 URTH1RXD INTP1 FCN0TX Software pull up initial value off P4_1 URTH1TXD TSG20PTSI0 ENCA0E0 FCN0RX P4_2 CSIG1SI TSG20PTSI1 ENCA0E1 OSTM1O P4_3 CSIG1SO TSG20PTSI2 ENCA0EC OSTM0O URTH1CTS P4_4 CSIG1SC URTH1RTS ESO0 INTP6 CSIG0RYO P4_5 AD...

Page 86: ...ADCA0TRG2 INTP5 P8 P8_0 TAUB0O15 OSTM1O Software pull up initial value off JP0 JP_1 Software pull up initial value off JP_2 Software pull up initial value off JP_3 Software pull up initial value off JP_5 Software pull up initial value off Table 2 32 List of Pull Up and Pull Down Resistors for Port Pins 3 3 Port Group Name Port Name Alternative Mode 1 Alternative Mode 2 Alternative Mode 3 Alternati...

Page 87: ...ns 1 2 Pin Name Pull Up Resistor Pull Down Resistor FLMD0 Software pull up pull down initial value pull down on FLMD1 Always pull down RESET Always pull down DCUTRST Always pull down DCUEVTO DCUTDI DCUTDO Connected to the on chip pull up resistor However not connected to the pull up resistor during DCUTDO output DCUTCK Connected to the on chip pull up resistor DCUTMS Connected to the on chip pull ...

Page 88: ...0I2 ADCA0I3 ADCA0I4 ADCA0I5 ADCA0I6 ADCA0I7 ADCA0I8 ADCA0I9 ADCA0I10 ADCA0I11 ADCA0I12 ADCA0I13 ADCA0I14 ADCA0I15 ADCA0I16 ADCA0I17 ADCA0I18 AVREF0P AVREF0M AVDD0 AVSS0 VDD VSS OSCVDD OSCVSS EVDD EVSS REGC0 REGC1 Table 2 33 List of Pull Up and Pull Down Resistors for Pins Other than Port Pins 2 2 Pin Name Pull Up Resistor Pull Down Resistor ...

Page 89: ...t 0 Table 2 34 List of Alternative Functions of Port 0 Port Mode PMC 0 Control Mode PMC 1 Alternative Mode 1 PFC 0 PFCE 0 Alternative Mode 2 PFC 1 PFCE 0 Alternative Mode 3 PFC 0 PFCE 1 Alternative Mode 4 PFC 1 PFCE 1 Input PM 1 Output PM 0 Input PM 1 Output PM 0 Input PM 1 Output PM 0 Input PM 1 Output PM 0 P0_0 INTP5 ADCA0 TRG2 URTH0 RXD INTP0 P0_1 INTP4 ADCA0 TRG1 URTH0 TXD P0_2 INTP3 ADCA0 TRG...

Page 90: ...Section 2 Port Functions 2 6 2 List of Control Registers 1 Port 0 Control Registers Table 2 35 List of Port 0 Control Registers Name Number of Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 8 16 32 P0 PSR0 PPR0 PM0 PMC0 PFC0 PFCE0 PNOT0 PMSR0 PMCSR0 PIBC0 PBDC0 PIPC0 PU0 ...

Page 91: ...Mode 1 PFC 0 PFCE 0 Alternative Mode 2 PFC 1 PFCE 0 Alternative Mode 3 PFC 0 PFCE 1 Alternative Mode 4 PFC 1 PFCE 1 Input PM 1 Output PM 0 Input PM 1 Output PM 0 Input PM 1 Output PM 0 Input PM 1 Output PM 0 P1_0 NMI CLKOUT OSTM1O TSG20O7 P1_1 TAUJ0I0 TAUJ0O0 TSG20O1 P1_2 TAUJ0I1 TAUJ0O1 TSG20O2 P1_3 TAUJ0I2 TAUJ0O2 TSG20O3 P1_4 TAUJ0I3 TAUJ0O3 TSG20O4 P1_5 TSG20O5 P1_6 TSG20O6 P1_7 CSIG0SI URTH0 ...

Page 92: ...Section 2 Port Functions 2 7 2 List of Control Registers 1 Port 1 Control Registers Table 2 37 List of Port 1 Control Registers Name Number of Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 8 16 32 P1 PSR1 PPR1 PM1 PMC1 PFC1 PFCE1 PNOT1 PMSR1 PMCSR1 PIBC1 PBDC1 PIPC1 PU1 ...

Page 93: ...0 Alternative Mode 2 PFC 1 PFCE 0 Alternative Mode 3 PFC 0 PFCE 1 Alternative Mode 4 PFC 1 PFCE 1 Input PM 1 Output PM 0 Input PM 1 Output PM 0 Input PM 1 Output PM 0 Input PM 1 Output PM 0 P2_0 TAUB0I1 TAUB0O1 TAUB0I0 TAUB0O0 URTH1SC URTH1SC CSIG0RYI P2_1 TAUB0I3 TAUB0O3 TAUB0I2 TAUB0O2 CSIG1RYI P2_2 TAUB0I5 TAUB0O5 TAUB0I4 TAUB0O4 TAUB0O10 P2_3 TAUB0I7 TAUB0O7 TAUB0I6 TAUB0O6 TAUB0O12 P2_4 TAUB0...

Page 94: ...Port Functions 2 8 2 List of Control Registers 1 Port 2 Control Register Table 2 39 List of Port 2 Control Registers Name Number of Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 8 16 32 P2 PSR2 PPR2 PM2 PMC2 PFC2 PFCE2 PNOT2 PMSR2 PMCSR2 PIBC2 PBDC2 PIPC2 PU2 PODC2 PPROTS2 PPCMD2 ...

Page 95: ...rnative Functions of Port 3 Port Mode PMC 0 Control Mode PMC 1 Alternative Mode 1 PFC 0 PFCE 0 Alternative Mode 2 PFC 1 PFCE 0 Alternative Mode 3 PFC 0 PFCE 1 Alternative Mode 4 PFC 1 PFCE 1 Input PM 1 Output PM 0 Input PM 1 Output PM 0 Input PM 1 Output PM 0 Input PM 1 Output PM 0 P3_0 URTH1RXD INTP1 P3_1 URTH1 TXD P3_2 CSIG1SI P3_3 CSIG1SO 1 CSIG1SO TPB0O P3_4 CSIG1SC CSIG1SC P3_5 INTP2 FCN1TX P...

Page 96: ...ion 2 Port Functions 2 9 2 List of Control Registers 1 List of Port 3 Control Registers Table 2 41 List of Port 3 Control Registers Name Number of Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 8 16 32 P3 PSR3 PPR3 PM3 PMC3 PFC3 PFCE3 PNOT3 PMSR3 PMCSR3 PIBC3 PBDC3 PIPC3 PU3 ...

Page 97: ...C 0 PFCE 0 Alternative Mode 2 PFC 1 PFCE 0 Alternative Mode 3 PFC 0 PFCE 1 Alternative Mode 4 PFC 1 PFCE 1 Input PM 1 Output PM 0 Input PM 1 Output PM 0 Input PM 1 Output PM 0 Input PM 1 Output PM 0 P4_0 URTH1 RXD INTP1 FCN0TX P4_1 URTH1 TXD TSG20 PTSI0 ENCA0E0 FCN0RX P4_2 CSIG1SI TSG20 PTSI1 ENCA0E1 OSTM1O P4_3 CSIG1SO 1 CSIG1SO TSG20 PTSI2 ENCA0EC OSTM0O URTH1 CTS P4_4 CSIG1SC CSIG1SC URTH1 RTS ...

Page 98: ...Section 2 Port Functions 2 10 2 List of Control Registers 1 Port 4 Control Registers Table 2 43 List of Port 4 Control Registers Name Number of Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 8 16 32 P4 PSR4 PPR4 PM4 PMC4 PFC4 PFCE4 PNOT4 PMSR4 PMCSR4 PIBC4 PBDC4 PIPC4 PU4 ...

Page 99: ...le 2 44 List of Alternative Functions of Port 5 Port Mode PMC 0 Control Mode PMC 1 Alternative Mode 1 PFC 0 PFCE 0 Alternative Mode 2 PFC 1 PFCE 0 Alternative Mode 3 PFC 0 PFCE 1 Alternative Mode 4 PFC 1 PFCE 1 Input PM 1 Output PM 0 Input PM 1 Output PM 0 Input PM 1 Output PM 0 Input PM 1 Output PM 0 P5_0 URTH0 RXD INTP0 P5_1 URTH0 TXD ADCA0 TRG0 INTP3 P5_2 INTP2 URTH0SC URTH0SC ADCA0 TRG1 INTP4 ...

Page 100: ...Section 2 Port Functions 2 11 2 List of Control Registers 1 Port 5 Control Registers Table 2 45 List of Port 5 Control Registers Name Number of Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 8 16 32 P5 PSR5 PPR5 PM5 PMC5 PFC5 PFCE5 PNOT5 PMSR5 PMCSR5 PIBC5 PBDC5 PIPC5 PU5 ...

Page 101: ... Table 2 46 List of Alternative Functions of Port 8 Port Mode PMC 0 Control Mode PMC 1 Alternative Mode 1 PFC 0 PFCE 0 Alternative Mode 2 PFC 1 PFCE 0 Alternative Mode 3 PFC 0 PFCE 1 Alternative Mode 4 PFC 1 PFCE 1 Input PM 1 Output PM 0 Input PM 1 Output PM 0 Input PM 1 Output PM 0 Input PM 1 Output PM 0 P8_0 TAUB0O15 OSTM1O Table 2 47 List of Port 8 Control Registers Name Number of Bits 15 14 13...

Page 102: ...gisters of JTAG port 0 2 13 1 Alternative Functions 1 Alternative Functions of JTAG Port 0 The JTAG port 0 has no any alternative function pin 2 13 2 List of Control Registers 1 JTAG Port 0 Control Registers Table 2 48 List of JTAG Port 0 Control Registers Name Number of Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 8 16 32 JP0 JPSR0 JPPR0 JPM0 JPNOT0 JPMSR0 JPIBC0 JPU0 ...

Page 103: ...nd the level of the output signal from the filter does not change The length of an external signal pulse to be judged as noise depends on the sampling frequency and the specified number of same level samples Both parameters can be specified DNFAnCTL DNFAnPRS 2 0 allows to select the sampling frequency to fs fDNFATCKI 2DNFAnPRS 2 0 where fDNFATCKI is the frequency of the DNFATCKI clock DNFAnCTL DNF...

Page 104: ...NMI DNF_NMI G0 P1_1 TAUJ0I0 DNF_TAUJ0 G0 P1_2 TAUJ0I1 DNF_TAUJ0 G0 P1_3 TAUJ0I2 DNF_TAUJ0 G0 P1_4 TAUJ0I3 DNF_TAUJ0 G0 P1_7 INTP0 DNF_INTP G0 P2 P2_0 TAUB0I0 DNF_TAUB0 G0 TAUB0I1 DNF_TAUB0 G0 CSIG0RYI DNF_CSI G0 P2_1 TAUB0I2 DNF_TAUB0 G1 TAUB0I3 DNF_TAUB0 G1 CSIG1RYI DNF_CSI G0 P2_2 TAUB0I4 DNF_TAUB0 G2 TAUB0I5 DNF_TAUB0 G2 P2_3 TAUB0I6 DNF_TAUB0 G3 TAUB0I7 DNF_TAUB0 G3 P2_4 TAUB0I8 DNF_TAUB0 G3 T...

Page 105: ...I2 ENCA0EC DNF_TSG20 G1 P4_4 ESO0 ESO INTP6 DNF_INTP G2 P4_5 INTP7 DNF_INTP G2 P4_6 ESO2 ESO INTP8 DNF_INTP G2 P4_7 NMI DNF_NMI G0 INTP9 DNF_INTP G2 P5 P5_0 INTP0 DNF_INTP G0 P5_1 INTP3 DNF_INTP G1 P5_2 INTP2 DNF_INTP G0 INTP4 DNF_INTP G1 P5_3 INTP3 DNF_INTP G1 INTP5 DNF_INTP G1 Table 2 49 List of Noise Filter Insertion Pins and Filter Groups 2 2 Port Group Name Port Pin Filter Insertion Pin Filte...

Page 106: ...n 2 Port Functions 3 Noise Filter Insertion Pins and Filter Groups for Table 2 50 List of Filter Insertion Pins and Filter Groups for Pins Other than Port Pin Name Filter Insertion Pin Filter Group FLMD0 FLMD0 FLMD0 FLMD1 FLMD1 FLMD1 RESET RESET RESET DCUTRST DCUTRST DCUTRST ...

Page 107: ...ock Selection Group RESET RESET RESET Analog filter Min 100 ns Max 500 ns DCUTRST Nexus DCUTRST FLMD0 FLMD1 MODE FLMD0 FLMD1 Min 50 ns Max 250 ns ESO TAPA ESO0 ESO2 DNF_NMI G0 NMI NMI Digital filter INTP group 1 PCLK 2 PCLK 2 DNF_INTP G0 INTC INTP0 INTP1 INTP2 DNF_INTP G1 INTP3 INTP4 INTP5 DNF_INTP G2 INTP6 INTP7 INTP8 INTP9 DNF_TAUB0 G0 TAUB0 TAUB0I0 Digital filter TAUB0 group 1 PCLK 2 PCLK 2 3 T...

Page 108: ... 2 3 TAUJ0 ch0 CKEN TAUJ0I1 TAUJ0I2 TAUJ0I3 DNF_TSG20 G0 TSG20 TSG20PTSI0 ENCA0E0 TSG20PTSI1 ENCA0E1 Digital filter TSG2 ENC group 1 PCLK 2 PCLK 2 DNF_TSG20 G1 TSG20PTSI2 ENCA0EC DNF_CSI G0 CSIG0 CSIG0RYI CSIgroup 1 PCLK 2 PCLK 2 CSIG1 CSIG1RYI Table 2 51 List of Noise Cancelling Intervals and Sampling Clock for Noise Cancellation 2 2 Filter Group Function Block Target Pin Type Analog or Digital N...

Page 109: ...ut Caution 2 Many registers include bits to which no function has been allocated Unless there is a specific indication to the contrary do not write values other than the initial values to such bits Operation is not guaranteed if other values are set in these bits Table 2 53 The List of Registers for the Digital Noise Canceller Register Function Name Address Digital noise canceller control register...

Page 110: ...al value 00H 7 6 5 4 3 2 1 0 0 DNFAnNFSTS 1 0 0 0 DNFAnPRS 2 0 R W R W R W R W R W R W R W R W Table 2 54 Contents of Register DNFAnCTL Bit Position Bit Name Function 6 5 DNFAn NFSTS 1 0 Number of samples at the same level for judgment to validate or invalidate an external pulse 00 Two 01 Three 10 Four 11 Five 2 to 0 DNFAn PRS 2 0 Digital filter sampling clock selection 000 DNFATCKI 1 001 DNFATCKI...

Page 111: ...6 INTP7 INTP8 INTP9 DNFA4CTL FF410400 DNF_TAUB0 G0 TAUB0I0 TAUB0I1 DNFA5CTL FF410500 DNF_TAUB0 G1 TAUB0I2 TAUB0I3 DNFA6CTL FF410600 DNF_TAUB0 G2 TAUB0I4 TAUB0I5 DNFA7CTL FF410700 DNF_TAUB0 G3 TAUB0I6 TAUB0I7 TAUB0I8 TAUB0I9 DNFA9CTL FF410900 DNF_TAUB0 G5 TAUB0I10 TAUB0I11 TAUB0I12 TAUB0I13 TAUB0I14 TAUB0I15 DNFA20CTL FF411400 DNF_TAUJ0 G0 TAUJ0I0 TAUJ0I1 TAUJ0I2 TAUJ0I3 DNFA28CTL FF411C00 DNF_TSG2...

Page 112: ...t Position Bit Name Function 15 to 0 DNFAnNFEN 15 0 Each bit enables or disables digital noise cancellation for the signal on the corresponding pin DNFA0EN to DNFA3EN registers If the NMI or INTP0 to INTP9 is in use set the corresponding bit to 1 DNFA0EN DNFA0NFEN 0 bit DNFA1EN DNFA1NFEN 2 0 bits DNFA2EN DNFA2NFEN 2 0 bits DNFA3EN DNFA3NFEN 3 0 bits DNFA2EN register If the ADCA0TRG0 ADCA0TRG1 or A...

Page 113: ... 0 0 0 DNFA0NFEN 0 NMI DNFA1EN FF410104 0 0 0 0 0 0 0 0 0 0 0 0 0 DNFA1NFEN 2 INTP2 DNFA1NFEN 1 INTP1 DNFA1NFEN 0 INTP0 DNFA2EN FF410204 0 0 0 0 0 0 0 0 0 0 0 0 0 DNFA2NFEN 2 INTP5 ADCA0TRG2 DNFA2NFEN 1 INTP4 ADCA0TRG1 DNFA2NFEN 0 INTP3 ADCA0TRG0 DNFA3EN FF410304 0 0 0 0 0 0 0 0 0 0 0 0 DNFA3NFEN 3 INTP9 DNFA3NFEN 2 ESO2 INTP8 DNFA3NFEN 1 INTP7 DNFA3NFEN 0 ESO0 INTP6 DNFA4EN FF410404 0 0 0 0 0 0 0...

Page 114: ...This register is the 8 lower order bits of DNFAnEN register Access This register is readable writable in 8 or 1 bit units Address Refer to Table 2 53 The List of Registers for the Digital Noise Canceller Initial value 00H For details of each bit operation see DNFAnEN register 7 6 5 4 3 2 1 0 DNFAnNFEN 7 0 R W R W R W R W R W R W R W R W ...

Page 115: ...nding DNF is enabled 15 14 13 12 11 10 9 8 0 0 DNFSCKSL6 1 0 0 0 DNFSCKSL4 1 0 R R R W R W R R R W R W 7 6 5 4 3 2 1 0 0 0 0 DNFSCKS L20 0 DNFSCKS L10 0 DNFSCKS L00 R R R R W R R W R R W Table 2 58 DNFSCTL Register Contents Bit Position Bit Name Function 13 12 DNFSCKSL 61 60 Selects the sampling clock of the TAUJ0 group 00 PCLK 01 PCLK 2 10 TAUJ0 ch0 CKEN signal 11 Setting prohibited 9 8 DNFSCKSL ...

Page 116: ...ters used with edge detection 2 15 1 Details of Edge Detection 1 Pins for Use in Edge Detection Table 2 59 List of Pins for Use in Edge Detection Target Pin Control Register Name NMI FCLA0CTL0 INTP0 FCLA1CTL0 INTP1 FCLA1CTL1 INTP2 FCLA1CTL2 INTP3 FCLA1CTL3 INTP4 FCLA1CTL4 INTP5 FCLA1CTL5 INTP6 FCLA1CTL6 INTP7 FCLA1CTL7 INTP8 FCLA2CTL0 INTP9 FCLA2CTL1 ...

Page 117: ...ts Operation is not guaranteed if other values are set in these bits 7 6 5 4 3 2 1 0 0 0 0 0 0 0 FCLAn INTFm FCLAn INTRm R R R R R R R W R W Table 2 60 FCLAnCTLm Register Contents Bit Position Bit Name Function 1 FCLAnINTFm Controls falling edge detection of the input signal 0 Falling edge detection disabled 1 Falling edge detection enabled 0 FCLAnINTRm Controls rising edge detection of the input ...

Page 118: ... Instruction execution times Internal 32 bit architecture 7 stage pipeline 32 32 bit general purpose registers 2 way superscalar Memory space 512 Mbyte linear program space 4 Gbyte linear data space Table 3 1 Descriptions of CPU Functions Function V850E2M Architecture R01US0001E This Manual V850E2 CPU including instruction set Processor protection functions MPU SRP PPU TSU DMA controller DMAC Inte...

Page 119: ...al access to peripheral modules Timing supervision unit TSU Protection against inappropriate CPU time possession by a non trusted program and resources and time of disabling interrupts can be managed Instruction set V850E2 instruction set compatible to former V850 instruction sets plus additional powerful instructions for reduced code size and increasing execution speed Signed multiplication opera...

Page 120: ...rs are named with m 0 to 31 PPVn PPVnm PPTn PPTnm PPPn PPPnm PPSn PPSnm The protected address ranges their control registers and bits and the modules in the respective address are listed in Table 3 2 PPU Protected Areas and Modules Table 3 2 PPU Protected Areas and Modules 1 4 Protection Range Size Protection Control Module Name Address Range Registers PPVn PPTn PPPn PPSn n Bits PPVnm PPTnm PPPnm ...

Page 121: ...B 2 16 CSIG0 FF70 0000H FF70 FFFFH 17 CSIG1 FF71 0000H FF71 FFFFH 4 KB 3 0 OSTM0 FF80 0000H FF80 0FFFH 1 OSTM1 FF80 1000H FF80 1FFFH 2 CLMA0 FF80 2000H FF80 2FFFH 3 CLMA1 FF80 3000H FF80 3FFFH 4 CLMA2 FF80 4000H FF80 4FFFH 6 WDTA0 FF80 6000H FF80 6FFFH 8 TAUB0 FF80 8000H FF80 8FFFH 17 TAUJ0 FF81 1000H FF81 1FFFH 21 TAPA0 FF81 5000H FF81 5FFFH 23 TAPA2 FF81 7000H FF81 7FFFH 25 ENCA0 FF81 9000H FF81...

Page 122: ...F 80FFH 1 FFFF 8100H FFFF 81FFH 2 FFFF 8200H FFFF 82FFH 3 FFFF 8300H FFFF 83FFH 4 FFFF 8400H FFFF 84FFH 5 FFFF 8500H FFFF 85FFH 6 FFFF 8600H FFFF 86FFH 7 FFFF 8700H FFFF 87FFH 8 FFFF 8800H FFFF 88FFH 9 FFFF 8900H FFFF 89FFH 256 B 7 0 OSTM0 FFFF C000H FFFF C0FFH 1 OSTM1 FFFF C100H FFFF C1FFH 2 TAUJ0 FFFF C200H FFFF C2FFH 4 TAUB0 FFFF C400H FFFF C4FFH 5 FFFF C500H FFFF C5FFH 6 FFFF C600H FFFF C6FFH ...

Page 123: ...FH 11 UARTH1 FFFF EB00H FFFF EBFFH 16 TPBA0 FFFF F000H FFFF F0FFH 17 FFFF F100H FFFF F1FFH 26 DCRA0 FFFF FA00H FFFF FAFFH 30 Baud rate detection in operation as a slave device for LIN communications FFFF FE00H FFFF FEFFH Table 3 2 PPU Protected Areas and Modules 4 4 Protection Range Size Protection Control Module Name Address Range Registers PPVn PPTn PPPn PPSn n Bits PPVnm PPTnm PPPnm PPSnm m ...

Page 124: ... that immediately follows the branching instruction is in an area of on chip RAM that is not initialized this does not apply when the loading instruction is in the flash area Applicable branching instructions are Bcond JARL JMP and JR Applicable loading instructions are LD and SLD Use any one of the following methods to avoid the above phenomenon Initialize the on chip RAM area before using it Ins...

Page 125: ...ng to the table below Note When the FLMD0 pin is in use connect a resistor with a value of at least 270 k to pull it down to the EVSS level 3 2 1 Normal Operation Mode This mode enables to access the on chip ROM In single chip mode instruction processing starts with a branch to the reset entry address in the on chip ROM after release from the system reset state 3 2 2 Flash Programming Mode This mo...

Page 126: ...f a reset or to the generation of an interrupt or other exception Following the acceptance of any interrupt or exception program counting by the program counter resumes from the address of the instruction after the HALT instruction Input of any of the following resets or the generation of any of the following interrupts or exceptions constitutes a request for release from HALT mode Reset input RES...

Page 127: ...ress space With the 32 bit general purpose registers addresses for a 4 Gbyte memory can be generated This is the maximum address space supported by the CPU 512 Mbyte physical program address space The CPU provides 512 Mbyte physical address space to access instruction codes in program memory That means that a maximum of 512 Mbyte internal or external program memory can be accessed 3 3 2 Program an...

Page 128: ...f the data space Figure 3 2 Wrap Around of Data Space 2 Wrap Around of Program Space If an instruction address calculation exceeds 28 bits only the lower 28 bits of the result are considered Therefore the addresses 0000 0000H and 0FFF FFFFH are contiguous addresses This results in a wrap around of the program space Figure 3 3 Wrap Around of Program Space FFFF FFFEH FFFF FFFFH 0000 0000H 0000 0001H...

Page 129: ...structions are not executed 3 4 2 Data Space This product is capable of handling misaligned data This allows the allocation of data to any address regardless of the unit of data word or half word However for a word or half word of data at least 2 bus cycles are generated unless the data are aligned with the corresponding boundary and this decreases bus efficiency 1 Access to Data with Half Word Le...

Page 130: ... Jul 17 2014 V850E2 PG4 L Section 3 CPU System Function 3 5 Memory Mapping This section describes memory maps for the CPU and the address map for DMA 3 5 1 Memory Map for DMA Access For details refer to Section 5 3 3 Memory Map for DMA Access ...

Page 131: ...FF3F FFFFH FF40 0000H FF7F FFFFH FF80 0000H FFFF 5000H FFFF 4FFFH FFFF 5FFFH FFFF 6000H FFFF FFFFH Undefined area Undefined area Undefined area On chip RAM area 24 Kbytes Undefined area 0200 4000H 0200 3FFFH FEDF 9FFFH FEDF A000H FF83 FFFFH FF84 0000H PBUS peripheral I O area 32 Kbytes PBUS peripheral I O area 256 Kbytes PBUS peripheral I O area 4 Mbytes FFFF 6FFFH FFFF 7000H FFFF 7FFFH FFFF 8000H...

Page 132: ...on 3 6 CPU Related Registers This section describes CPU related registers 3 6 1 Overview of CPU Related Registers Table 3 5 List of CPU Related Registers Register Name Symbol Address Processor element identifier register PEID FFFF 6490H Data flash access wait setting register DCLKWAIT FF43 6000H ...

Page 133: ...1FH by a reset from any source Table 3 7 DCLKWAIT Register Caution After release from the reset state set the waiting time for access by the time of the first access to data flash memory 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PEID 15 0 R R R R R R R R R R R R R R R R Bit Position Bit Name Function 15 to 0 PEID 15 0 These bits indicate a processor element ID and are always read as 0001H 7 6 5 4 3 2 ...

Page 134: ...This section describes the registers involved in system error notification 3 7 1 Overview of System Error Notification Registers Table 3 8 List of System Error Notification Function Registers Register Name Symbol Address System error control register SEG_CONT FFFF 64B0H SEG_CONTL System error flag register SEG_FLAG FFFF 64B2H SEG_FLAGL ...

Page 135: ...he generation of SYSERR exceptions due to system error sources Access SEG_CONT is readable writable in 16 bit units SEG_CONTL consists of the 8 lower order bits of SEG_CONT and is readable writable in 8 and 1 bit units Address FFFF 64B0H Initial value 0000H 15 14 13 12 11 10 9 8 SEG_CONT 0 0 0 0 0 0 0 0 R R R R R R R R 7 6 5 4 3 2 1 0 SEG_CONTL SEG_ CONT DMAE 0 SEG_ CONT SEGE SEG_ CONT RAME 0 SEG_...

Page 136: ...F 0000H to FFFF 4FFFH is for use in future expansion The user is unable to use this area A system error will occur if access is attempted 4 SEG_ CONT RAME CPU on chip RAM area error notification enable This bit is used to set the behavior when CPU access to data in the on chip RAM area leads to an uncorrectable error 0 SYSERR exception is not generated initial value 1 SYSERR exception is generated...

Page 137: ...SYSERR exceptions A flag is cleared by reading it as 1 and then writing 0 to it Even when 0 is later written to a flag that was read as 0 the flags will still be set to reflect any errors that occurred between the reading and writing Access SEG_FLAG is readable writable in 16 bit units SEG_FLAGL consists of the 8 lower order bits of SEG_FLAG and is readable writable in 8 and 1 bit units Address FF...

Page 138: ...se this area A system error will occur if access is attempted 4 SEG_ FLAG RAMF CPU on chip RAM area error flag This flag is set when CPU access to data in the on chip RAM area leads to an uncorrectable ECC error 0 Error in the on chip RAM area is not generated 1 Error in the on chip RAM area is generated 2 SEG_ FLAG EXTF EXT area error flag This flag is set when CPU access to data in data flash me...

Page 139: ...put 1 Reserved 2 FE level non maskable interrupt FENMI FENMI input 3 FE System error exception SYSERR System error SYSERR input 1 4 FE Peripheral device protection exception PPI Peripheral device protection violation 5 FE Timing supervision exception TSI Timing supervision violation 6 FE FE level maskable interrupt FEINT FEINT input 7 FE Reserved 8 EI level maskable interrupt EIINT EIINT input 9 E...

Page 140: ...in Resume enabled recover enabled Highest priority interrupt except FENMI EI level maskable interrupt EIINT 131 sources Resume enabled recover enabled Interrupt masking can be specified per interrupt channel 16 interrupt priority levels can be specified for each interrupt channel In this section the EIINT that corresponds to interrupt channel n is indicated by EIINTn Note Resume Indicates whether ...

Page 141: ... EIINT8 INTECCLRED Detection of an ECC error in on chip RAM Safety 8 00000100 H 0100 H currentPC EIRET ICECCLRED FFFF 6010 EI EIINT9 INTECCLREC Detection or correction of an ECC error in on chip RAM Safety 9 00000110 H 0110 H currentPC EIRET ICECCLREC FFFF 6012 EI EIINT10 INTECCCDRED2 Detection due to cache flushing of an ECC error in RAM level 2 Safety 10 00000120 H 0120 H currentPC EIRET ICECCCD...

Page 142: ... transfer count matched 4 DMA 37 000002D0 H 02D0 H currentPC EIRET ICDMACT4 FFFF 604A EI EIINT38 INTDMA5 DMA transfer completed 5 DMA 38 000002E0 H 02E0 H currentPC EIRET ICDMA5 FFFF 604C EI EIINT39 INTDMACT5 DMA transfer count matched 5 DMA 39 000002F0 H 02F0 H currentPC EIRET ICDMACT5 FFFF 604E EI EIINT40 INTDMA6 DMA transfer completed 6 DMA 40 00000300 H 0300 H currentPC EIRET ICDMA6 FFFF 6050 ...

Page 143: ...EIINT65 INTTAUB0I11 TAUB0 CH11 interrupt signal TAUB0 65 00000490 H 0490 H currentPC EIRET ICTAUB0I11 FFFF 6082 EI EIINT66 INTTAUB0I12 TAUB0 CH12 interrupt signal TAUB0 66 000004A0 H 04A0 H currentPC EIRET ICTAUB0I12 FFFF 6084 EI EIINT67 INTTAUB0I13 TAUB0 CH13 interrupt signal TAUB0 67 000004B0 H 04B0 H currentPC EIRET ICTAUB0I13 FFFF 6086 EI EIINT68 INTTAUB0I14 TAUB0 CH14 interrupt signal TAUB0 6...

Page 144: ...F 60C8 EI EIINT101 INTCSIG0IC CSIG0 communication complete CSIG0 101 000006D0 H 06D0 H currentPC EIRET ICCSIG0IC FFFF 60CA EI EIINT102 INTCSIG1IRE CSIG1 reception error CSIG1 102 000006E0 H 06E0 H currentPC EIRET ICCSIG1IRE FFFF 60CC EI EIINT103 INTCSIG1IR CSIG1 reception complete CSIG1 103 000006F0 H 06F0 H currentPC EIRET ICCSIG1IR FFFF 60CE EI EIINT104 INTCSIG1IC CSIG1 communication complete CS...

Page 145: ...20 compare match 2 interrupt TSG20 131 000008B0 H 08B0 H currentPC EIRET ICTSG20I02 FFFF 6106 EI EIINT132 INTTSG20I03 TSG20 compare match 3 interrupt TSG20 132 000008C0 H 08C0 H currentPC EIRET ICTSG20I03 FFFF 6108 EI EIINT133 INTTSG20I04 TSG20 compare match 4 interrupt TSG20 133 000008D0 H 08D0 H currentPC EIRET ICTSG20I04 FFFF 610A EI EIINT134 INTTSG20I05 TSG20 compare match 5 interrupt TSG20 13...

Page 146: ...NCA0 overflow interrupt ENCA0 163 00000AB0 H 0AB0 H currentPC EIRET ICENCA0IOV FFFF 6146 EI EIINT164 INTENCA0I0 ENCA0 capture compare match 0 interrupt ENCA0 164 00000AC0 H 0AC0 H currentPC EIRET ICENCA0I0 FFFF 6148 EI EIINT165 INTENCA0I1 ENCA0 capture compare match 1 interrupt ENCA0 165 00000AD0 H 0AD0 H currentPC EIRET ICENCA0I1 FFFF 614A EI EIINT166 INTENCA0IUD ENCA0 underflow interrupt ENCA0 1...

Page 147: ...ed 00000C80 H 0C80 H currentPC EIRET EI EIINT193 INTSW0 6 Software interrupt 0 Software 193 00000C90 H 0C90 H currentPC EIRET ICSW0 FFFF 6182 EI EIINT194 INTSW1 6 Software interrupt 1 Software 194 00000CA0 H 0CA0 H currentPC EIRET ICSW1 FFFF 6184 EI EIINT195 INTSW2 6 Software interrupt 2 Software 195 00000CB0 H 0CB0 H currentPC EIRET ICSW2 FFFF 6186 EI EIINT196 INTSW3 6 Software interrupt 3 Softwa...

Page 148: ...t SGA 220 00000E40 H 0E40 H currentPC EIRET ICSGACMEDIAG FFFF61B8 EI EIINT221 Reserved 00000E50 H 0E50 H currentPC EIRET EI EIINT222 Reserved 00000E60 H 0E60 H currentPC EIRET EI EIINT223 Reserved 00000E70 H 0E70 H currentPC EIRET Note 1 The base address is set by the exception handler address switching function Note 2 If the INTCFGB register is set for level output of EI FENMI interrupts will not...

Page 149: ...EI level maskable interrupt n EINTn will be generated in the same way as when an interrupt request is received 0 No interrupt request is made initial value 1 Interrupt request is made 7 MKxx This is an interrupt mask bit Setting the MKxx bit masks interrupt requests set in the interrupt request flag RFxx i e it may be used to obstruct interrupt requests from the given channel to the CPU core If th...

Page 150: ...FF6014H MKECCCDRED2 0 0 0 P3ECCCDRED2 P2ECCCDRED2 P1ECCCDRED2 P0ECCCDRED2 ICECCCDRED2H FFFF6015H 0 0 0 RFECCCDRED2 0 0 0 0 ICECCCTRED2L FFFF6016H MKECCCTRED2 0 0 0 P3ECCCTRED2 P2ECCCTRED2 P1ECCCTRED2 P0ECCCTRED2 ICECCCTRED2H FFFF6017H 0 0 0 RFECCCTRED2 0 0 0 0 ICECCCDRED1L FFFF6018H MKECCCDRED1 0 0 0 P3ECCCDRED1 P2ECCCDRED1 P1ECCCDRED1 P0ECCCDRED1 ICECCCDRED1H FFFF6019H 0 0 0 RFECCCDRED1 0 0 0 0 I...

Page 151: ...FF604AH MKDMACT4 0 0 0 P3DMACT4 P2DMACT4 P1DMACT4 P0DMACT4 ICDMACT4H FFFF604BH 0 0 0 RFDMACT4 0 0 0 0 ICDMA5L FFFF604CH MKDMA5 0 0 0 P3DMA5 P2DMA5 P1DMA5 P0DMA5 ICDMA5H FFFF604DH 0 0 0 RFDMA5 0 0 0 0 ICDMACT5L FFFF604EH MKDMACT5 0 0 0 P3DMACT5 P2DMACT5 P1DMACT5 P0DMACT5 ICDMACT5H FFFF604FH 0 0 0 RFDMACT5 0 0 0 0 ICDMA6L FFFF6050H MKDMA6 0 0 0 P3DMA6 P2DMA6 P1DMA6 P0DMA6 ICDMA6H FFFF6051H 0 0 0 RFD...

Page 152: ...ICTAUB0I10L FFFF6080H MKTAUB0I10 0 0 0 P3TAUB0I10 P2TAUB0I10 P1TAUB0I10 P0TAUB0I10 ICTAUB0I10H FFFF6081H 0 0 0 RFTAUB0I10 0 0 0 0 ICTAUB0I11L FFFF6082H MKTAUB0I11 0 0 0 P3TAUB0I11 P2TAUB0I11 P1TAUB0I11 P0TAUB0I11 ICTAUB0I11H FFFF6083H 0 0 0 RFTAUB0I11 0 0 0 0 ICTAUB0I12L FFFF6084H MKTAUB0I12 0 0 0 P3TAUB0I12 P2TAUB0I12 P1TAUB0I12 P0TAUB0I12 ICTAUB0I12H FFFF6085H 0 0 0 RFTAUB0I12 0 0 0 0 ICTAUB0I13...

Page 153: ...3URTH1IT P2URTH1IT P1URTH1IT P0URTH1IT ICURTH1ITH FFFF60E3H 0 0 0 RFURTH1IT 0 0 0 0 ICFCN0ERRL FFFF60EAH MKFCN0ERR 0 0 0 P3FCN0ERR P2FCN0ERR P1FCN0ERR P0FCN0ERR ICFCN0ERRH FFFF60EBH 0 0 0 RFFCN0ERR 0 0 0 0 ICFCN0WUPL FFFF60ECH MKFCN0WUP 0 0 0 P3FCN0WUP P2FCN0WUP P1FCN0WUP P0FCN0WUP ICFCN0WUPH FFFF60EDH 0 0 0 RFFCN0WUP 0 0 0 0 ICFCN0RECL FFFF60EEH MKFCN0REC 0 0 0 P3FCN0REC P2FCN0REC P1FCN0REC P0FCN...

Page 154: ... 0 0 RFTSG20I11 0 0 0 0 ICTSG20I12L FFFF611AH MKTSG20I12 0 0 0 P3TSG20I12 P2TSG20I12 P1TSG20I12 P0TSG20I12 ICTSG20I12H FFFF611BH 0 0 0 RFTSG20I12 0 0 0 0 ICTSG20IPEKL FFFF611CH MKTSG20IPEK 0 0 0 P3TSG20IPEK P2TSG20IPEK P1TSG20IPEK P0TSG20IPEK ICTSG20IPEKH FFFF611DH 0 0 0 RFTSG20IPEK 0 0 0 0 ICTSG20IVLYL FFFF611EH MKTSG20IVLY 0 0 0 P3TSG20IVLY P2TSG20IVLY P1TSG20IVLY P0TSG20IVLY ICTSG20IVLYH FFFF61...

Page 155: ... 0 P3SW2 P2SW2 P1SW2 P0SW2 ICSW2H FFFF6187H 0 0 RFSW2 0 0 0 0 ICSW3L FFFF6188H MKSW3 0 0 0 P3SW3 P2SW3 P1SW3 P0SW3 ICSW3H FFFF6189H 0 0 RFSW3 0 0 0 0 ICSW4L FFFF618AH MKSW4 0 0 0 P3SW4 P2SW4 P1SW4 P0SW4 ICSW4H FFFF618BH 0 0 RFSW4 0 0 0 0 ICSW5L FFFF618CH MKSW5 0 0 0 P3SW5 P2SW5 P1SW5 P0SW5 ICSW5H FFFF618DH 0 0 RFSW5 0 0 0 0 ICSW6L FFFF618EH MKSW6 0 0 0 P3SW6 P2SW6 P1SW6 P0SW6 ICSW6H FFFF618FH 0 0 ...

Page 156: ...he corresponding IMR0EIMK 15 0 bits are updated simultaneously in response to writing in 8 or 16 bit units Address FFFF 6400H Initial value FFFFH A reset from any source will initialize the bits IMR0 15 7 14 6 13 5 12 4 11 3 10 2 9 1 8 0 IMR0H IMR0EIMK 15 1 IMR0EIMK 13 IMR0EIMK 12 IMR0EIMK 11 IMR0EIMK 10 IMR0EIMK 9 IMR0EIMK 8 R W R R W R W R W R W R W R W 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 IMR0L IMR0...

Page 157: ... R W R W R W 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 IMR1L IMR1EIMK 23 IMR1EIMK 22 IMR1EIMK 21 IMR1EIMK 20 IMR1EIMK 19 IMR1EIMK 18 IMR1EIMK 17 IMR1EIMK 16 R W R W R W R W R W R W R W R W Bit Position Bit Name Function 15 to 0 IMR1EIMK31 to IMR1EIMK16 These are mask bits for EI level maskable interrupt EIINT channels 16 to 31 IMR1EIMK31 to IMR1EIMK16 correspond to EIINT31 to EIINT16 0 Enables interrupt ser...

Page 158: ...IMK 61 IMR3EIMK 60 IMR3EIMK 59 IMR3EIMK 58 IMR3EIMK 57 IMR3EIMK 56 R W R W R W R W R W R W R W R W 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 IMR3L IMR3EIMK 55 IMR3EIMK 54 1 1 1 1 IMR3EIMK 49 IMR3EIMK 48 R W R W R R R R R W R W Bit Position Bit Name Function 15 to 0 IMR3EIMK63 to IMR3EIMK48 These are mask bits for EI level maskable interrupt EIINT channels 48 to 63 IMR3EIMK63 to IMR3EIMK48 correspond to EIIN...

Page 159: ...5EIMK 90 IMR5EIMK 89 IMR5EIMK 88 R R R R R R W R W R W 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 IMR5L IMR5EIMK 87 IMR5EIMK 86 1 1 1 1 1 1 R W R W R R R R R R Bit Position Bit Name Function 15 to 0 IMR5EIMK95 to IMR5EIMK80 These are mask bits for EI level maskable interrupt EIINT channels 80 to 95 IMR5EIMK95 to IMR5EIMK80 correspond to EIINT95 to EIINT80 0 Enables interrupt servicing 1 Disables interrupt se...

Page 160: ...W R W R W R W R W 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 IMR7L IMR7EIMK 119 IMR7EIMK 118 IMR7EIMK 117 1 1 1 IMR7EIMK 113 IMR7EIMK 112 R W R W R W R R R R W R W Bit Position Bit Name Function 15 to 0 IMR7EIMK127 to IMR7EIMK112 These are mask bits for EI level maskable interrupt EIINT channels 112 to 127 IMR7EIMK127 to IMR7EIMK112 correspond to EIINT127 to EIINT112 0 Enables interrupt servicing 1 Disables ...

Page 161: ...IMR9H 1 1 1 1 1 1 1 1 R R R R R R R R 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 IMR9L 1 1 1 1 1 1 IMR9EIMK 145 IMR9EIMK 144 R R R R R R R W R W Bit Position Bit Name Function 15 to 0 IMR9EIMK159 to IMR9EIMK144 These are mask bits for EI level maskable interrupt EIINT channels 144 to 159 IMR9EIMK159 to IMR9EIMK144 correspond to EIINT159 to EIINT144 0 Enables interrupt servicing 1 Disables interrupt servicing...

Page 162: ...1 1 1 1 R R R R R R R R 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 IMR11L 1 IMR11EIMK 182 IMR11EIMK 181 1 1 1 1 1 R R W R W R R R R R Bit Position Bit Name Function 15 to 0 IMR11EIMK191 to IMR11EIMK176 These are mask bits for EI level maskable interrupt EIINT channels 176 to 191 IMR11EIMK191 to IMR11EIMK176 correspond to EIINT191 to EIINT176 0 Enables interrupt servicing 1 Disables interrupt servicing IMR12 ...

Page 163: ...FFFF 641AH Initial value FFFFH A reset from any source will initialize the bits IMR12 15 7 14 6 13 5 12 4 11 3 10 2 9 1 8 0 IMR13H 1 1 1 IMR13EIMK 220 1 1 1 1 R R R R W R R R R 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 IMR13L 1 1 1 1 1 1 1 1 R R R R R R R R Bit Position Bit Name Function 15 to 0 IMR12EIMK223 to IMR12EIMK208 These are mask bits for EI level maskable interrupt EIINT channels 223 to 208 IMR13E...

Page 164: ... or lower order bits 7 0 may be accessed by reading in 8 bit units Address FFFF 6440H Initial value 0000H A reset from any source will initialize the bits Note All of the bits in ISPR can be cleared by simultaneously writing 1 to all bits of register ISPC and then simultaneously writing 0 to all bits of ISPR i e by using 16 bit operations Clearing and setting individual bits as required by softwar...

Page 165: ...le in 1 8 or 16 bit units Either the eight higher order bits 15 8 or lower order bits 7 0 may be accessed by reading in 8 bit units Address FFFF 6448H Initial value 0000H A reset from any source will initialize the bits PMR 15 7 14 6 13 5 12 4 11 3 10 2 9 1 8 0 PMRH PMR15 PMR14 PMR13 PMR12 PMR11 PMR10 PMR9 PMR8 R W R W R W R W R W R W R W R W 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 PMRL PMR7 PMR6 PMR5 PMR...

Page 166: ...leared to 0 When register ISPC is read the value 1 is read from all bits after 1 has been written to all bits and the value 0 is read from all bits after a reset or clearing of the ISPR Writing other than writing 1 to all bits or 0 to all bits leaves the register s value unchanged Furthermore although writing 0 to all bits while all bits currently have the value 1 clears all bits of register ISPC ...

Page 167: ... or lower order bits 7 0 may be accessed by reading in 8 bit units Address FFFF 6458H Initial value 0000H A reset from any source will initialize the bits SCR 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 R R R R R R R R 7 6 5 4 3 2 1 0 SCRL SCR7 SCR6 SCR5 SCR4 SCR3 SCR2 SCR1 SCR0 R R R R R R R R Bit Position Bit Name Function 7 to 0 SCR7 to SCR0 Holds the channel number of the maskable interrupt that has...

Page 168: ... ICSREIR 0 ICSRFNE ICSRFIE ICSREIE R R R R R R R R Bit Position Bit Name Function 8 ICSRPMF Indicates 1 if the request flag of a channel of EI level maskable interrupt EIINT that has the interrupt priority prohibited by the setting of PMR from being serviced is set 6 ICSRFNR Indicates 1 if an FE level non maskable interrupt FENMI has been issued to the CPU 5 ICSRFIR Indicates 1 if an FE level mask...

Page 169: ... only and is read in 1 8 or 16 bit units Either the eight higher order bits 15 8 or lower order bits 7 0 may be accessed by reading in 8 bit units Address FFFF 645CH Initial value 0000H A reset from any source will initialize the bits FNC 15 14 13 12 11 10 9 8 FNCH 0 0 0 FNRF 0 0 0 0 R R R R R R R R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R R R R R R R R Bit Position Bit Name Function 12 FNRF Interrupt re...

Page 170: ...nly and is read in 1 8 or 16 bit units Either the eight higher order bits 15 8 or lower order bits 7 0 may be accessed by reading in 8 bit units Address FFFF 645EH Initial value 0000H A reset from any source will initialize the bits FIC 15 14 13 12 11 10 9 8 FICH 0 0 0 FIRF 0 0 0 0 R R R R R R R R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R R R R R R R R Bit Position Bit Name Function 12 FIRF Interrupt requ...

Page 171: ... of interrupt signals from the safety guardian INTISG signals output is disabled with the initial value 3 Select EI level operation by writing to this register INTCFGB 4 Enable operation of WDTA0 CLMA1 and CLMA2 and output of interrupt signals from the safety guardian Caution When changing the setting of this register only do so when the state is such that interrupts from none of the following sou...

Page 172: ...INTWDTA0NMI further interrupts will not be generated once one interrupt has been generated and until a reset is input Clear the bit if the generation of multiple interrupts or a new interrupt is required Caution 2 When a CPU comparison error occurs an SGA status register specifically the SGAmESSTR0 SGAmSSE005 bit must be read to determine whether the error has occurred because in some cases the er...

Page 173: ... not write 1 to any bit for which no function is indicated This register always returns 0 when read Address FF83 A008H Initial value 00H A reset from any source will initialize the bits 7 6 5 4 3 2 1 0 INTSTC0B 0 0 INTISTC5 INTISTC4 0 INTISTC2 INTISTC1 INTISTC0 W W W W W W W W Bit Position Bit Name Function 5 INTISTC5 0 No processing This bit is always read as 0 1 Clears the INTISTF5 flag 4 INTIST...

Page 174: ...ite only with writing in 1 or 8 bit units Do not write 1 to any bit for which no function is indicated This register always returns 0 when read Address FF83 A00CH Initial value 00H A reset from any source will initialize the bits 7 6 5 4 3 2 1 0 INTSTS0B 0 0 INTISTS5 INTISTS4 0 INTISTS2 INTISTS1 INTISTS0 W W W W W W W W Bit Position Bit Name Function 5 INTISTS5 0 No processing This bit is always r...

Page 175: ...his FE level non maskable interrupt is used when a fatal system error occurs Caution Upon acknowledgment of the FENMI interrupt generation of the next FENMI FEINT or EIINT interrupt is pended until the FERET instruction is executed interrupt request is acknowledged and held FENMI can be acknowledged even when the NP bit is set to 1 Therefore if the FENMI interrupt occurs during the processing of a...

Page 176: ...P and IMP bits are always cleared 0 regardless of the status of MPM AUE FENMI interrupt request FNC FNRF 1 ICSR FNR 1 Yes No ICSR FNE 1 FE level non maskable interrupt Interrupt request is retained Interrupt processing CPU processing INTC acknowledged FEPC FEPSW FEIC PSW NP PSW ID PC value on return PSW Exception code 1 1 PC Handler address ICSR FNE 1 FNC FNRF 0 ICSR FNR 0 PSW EP 0 MPM AUE 1 Yes N...

Page 177: ...al system error occurs Execute a system reset after exception processing 4 4 3 FE Level Maskable Interrupt Caused by FEINT Interrupt Request When an FEINT interrupt is requested by the FEINT pin an FE level maskable interrupt is generated This interrupt is a recoverable FE level interrupt Upon acknowledgment of the FEINT interrupt generation of the next FEINT or EIINT interrupt is pended until the...

Page 178: ...eared 0 regardless of the status of MPM AUE FEINT interrupt request FNC FNRF 1 ICSR FNR 1 Yes No Yes ICSR FNE 1 or ICSR FIE 1 FE level maskable interrupt Interrupt request is retained PSW NP 0 No Interrupt request is retained Interrupt processing CPU processing INTC acknowledged FEPC FEPSW FEIC PSW NP PSW ID PC value on return PSW Exception code 1 1 PSW EP 0 MPM AUE 1 Yes No PSW PP PSW NPV PSW DMP...

Page 179: ...on with the PSW EP bit always cleared 0 Caution Although this CPU core incorporates an RETI instruction this is only provided for backward compatibility with the V850E1 and V850E2 architectures and its use is in principle prohibited Replace all RETI instructions other than existing programs that cannot be modified with EIRET or FERET instructions Figure 4 3 Restore from FE Level Maskable Interrupt...

Page 180: ...nel number can be easily known when wishing to share the same interrupt vectors among several channels Caution Upon acknowledgment of the EI level interrupt the priority level of the currently acknowledged interrupt is registered to the ISPR register in service priority register Then until execution of the EIRET instruction interrupt with a priority level lower than that of this ISPR register are ...

Page 181: ...est is retained Yes Yes Interrupt processing CPU processing INTC acknowledged No EIINT interrupt request with priority level lower than ISPR Priority level masked by PMR Yes No ICSR FNE 1 or ICSR FIE 1 EIPC EIPSW EIIC PSW ID PC value on return PSW Exception code 1 PC Handler address ICSR EIE 1 EIC EIRF 0 ICSR EIR 0 Corresponding bit of SCR 1 Corresponding bit of ISPR 1 EIC EIRF 1 ICSR EIR 1 ICSR P...

Page 182: ...t always cleared 0 Caution Although this CPU core incorporates an RETI instruction this is only provided for backward compatibility with the V850E1 and V850E2 architectures and its use is in principle prohibited Replace all RETI instructions other than existing programs that cannot be modified with EIRET or FERET instructions Figure 4 5 Restore from EI Level Maskable Interrupt EIINT Note The shade...

Page 183: ...n interrupt request while the request is held pending the interrupt will be generated at that time To delete a pending interrupt request that is currently held pending clear the corresponding ICxx RFxx bit 4 5 2 Interrupt Priority Level Judgment When an FE level non maskable interrupt FENMI FE level maskable interrupt FEINT or EI level maskable interrupt EIINT is input the priority levels of other...

Page 184: ...t stage 3 Of the Requested Interrupt Sources that with the Highest Priority Level is Selected In the case of simultaneous interrupt requests at the highest priority level from multiple sources that with the lowest interrupt channel number is selected 4 Interrupt Hold by CPU Interrupt acknowledgment is pended according to the state of the NP and ID bits of the PSW register At this time priority jud...

Page 185: ...owledged while another interrupt is being serviced is shown in Figure 4 6 When an interrupt request signal is acknowledged the PSW ID flag is automatically set to 1 Therefore when multiple interrupts are to be used clear the ID flag to 0 beforehand for example by placing the EI instruction in the interrupt service program to set the interrupt enable mode ...

Page 186: ...ve priority between two interrupt request signals Main routine EI EI Interrupt request a level 3 Servicing of a Servicing of b Servicing of c Interrupt request c level 3 Servicing of d Servicing of e EI Interrupt request e level 2 Servicing of f EI Servicing of g Interrupt request g level 1 Interrupt request h level 1 Servicing of h Interrupt request b is acknowledged because the priority of b is ...

Page 187: ... s level 1 Interrupt request k level 1 Servicing of l Servicing of n Servicing of m Servicing of s Servicing of u Servicing of t Interrupt request m level 3 Interrupt request n level 1 Servicing of o Interrupt request p level 2 Interrupt request q level 1 Interrupt request r level 0 Interrupt request u level 2 2 Interrupt request t level 2 1 Servicing of p Servicing of q Servicing of r EI If level...

Page 188: ...e 1 The letters a to c in the figure are simply labels for convenient reference to the interrupt requests in the explanation Note 2 The default priority in the figure indicates the relative priority between two interrupt request signals Default priority a b c Main routine EI Interrupt request a level 2 Interrupt request b level 1 Interrupt request c level 1 Servicing of interrupt request b Servici...

Page 189: ...is function Temporary prohibition of interrupts that have a priority level that is lower than a given priority level Temporary prohibition of interrupts that have a given priority level The PMR register prohibits interrupt occurrence Interrupt request is acknowledged and held even while the interrupt occurrence is prohibited The presence of EIINT interrupts held pending with this function can be c...

Page 190: ...IR bit in the interval during which PSW ID 1 it is possible to check whether an EIINT interrupt request exists When FE level maskable interrupt request is not output to the CPU ICSR FIR bit is set to 1 By looking at the ICSR FIR bit in the interval during which PSW NP 1 it is possible to check whether a FEINT interrupt request exists 4 5 5 In Service Priority Clear Function This function initializ...

Page 191: ...me 1HEAPCKL Note 1 In addition to the times described above the internal interrupt requires from a minimum of 1HEAPCLK to a maximum of 3HEAPCLK for the interval between generation and acknowledgement of the interrupt request Note 2 INT1 to INT7 in the figure indicate interrupt acknowledgement Note 3 The following cases are excluded When successive interrupt non sample instructions are being execut...

Page 192: ...m and l are used as shown below For the DMA function n indicates the channel numbers n 0 to 7 For the DMA function m indicates the DMA trigger source numbers m 0 to 107 For the DMA function l indicates the highest number for a DMA trigger source l 107 1 DMA Trigger Sources Assignment of DMA trigger sources to DMA channel n is set by the DTFRn IFC 6 0 bits All DMA trigger sources and the settings i...

Page 193: ...TIN015 INTDMA4 0 0 1 0 0 0 0 16 INTIN016 INTDMA5 0 0 1 0 0 0 1 17 INTIN017 INTDMA6 0 0 1 0 0 1 0 18 INTIN018 INTDMA7 0 0 1 0 0 1 1 19 INTIN019 INTTAUJ0I0 0 0 1 0 1 0 0 20 INTIN020 INTTAUJ0I1 0 0 1 0 1 0 1 21 INTIN021 INTTAUJ0I2 0 0 1 0 1 1 0 22 INTIN022 INTTAUJ0I3 0 0 1 0 1 1 1 23 INTIN023 Reserved 0 0 1 1 0 0 0 24 INTIN024 Reserved 0 0 1 1 0 0 1 25 INTIN025 Reserved 0 0 1 1 0 1 0 26 INTIN026 Rese...

Page 194: ...NTIN057 Reserved 0 1 1 1 0 1 0 58 INTIN058 Reserved 0 1 1 1 0 1 1 59 INTIN059 INTADCA0ERR 0 1 1 1 1 0 0 60 INTIN060 INTADCA0I0 0 1 1 1 1 0 1 61 INTIN061 INTADCA0I1 0 1 1 1 1 1 0 62 INTIN062 INTADCA0I2 0 1 1 1 1 1 1 63 INTIN063 Reserved 1 0 0 0 0 0 0 64 INTIN064 Reserved 1 0 0 0 0 0 1 65 INTIN065 Reserved 1 0 0 0 0 1 0 66 INTIN066 Reserved 1 0 0 0 0 1 1 67 INTIN067 Reserved 1 0 0 0 1 0 0 68 INTIN06...

Page 195: ...NTIN091 Reserved 1 0 1 1 1 0 0 92 INTIN092 INTENCA0IOV 1 0 1 1 1 0 1 93 INTIN093 INTENCA0I0 1 0 1 1 1 1 0 94 INTIN094 INTENCA0I1 1 0 1 1 1 1 1 95 INTIN095 INTENCA0IUD 1 1 0 0 0 0 0 96 INTIN096 INTENCA0IEC 1 1 0 0 0 0 1 97 INTIN097 Reserved 1 1 0 0 0 1 0 98 INTIN098 Reserved 1 1 0 0 0 1 1 99 INTIN099 Reserved 1 1 0 0 1 0 0 100 INTIN100 Reserved 1 1 0 0 1 0 1 101 INTIN101 Reserved 1 1 0 0 1 1 0 102 ...

Page 196: ...e DMA transfer request DMA transfer request in the form of any interrupt signal Software DMA transfer request DMA transfer request through an internal register the DTSnSR bit in DTSn register DMA transfer request Hardware DMA transfer request or software DMA transfer request Single transfer The DMAC executes a single DMA cycle per transfer request Single step transfer The number of transfers speci...

Page 197: ...est is accepted a transfer request is output to the DMAT according to the transfer information it contains Hardware DMA transfer requests DMA acknowledge signals and DMA transfer completion interrupts are input and output Write back information is written back to the registers 5 3 2 Function of the DMA Trigger Factor Register DTFR This register selects DMA transfer sources from among the interrupt...

Page 198: ...ls DTFR DMAC0 DMA controller INTDMA 7 0 INTCT 7 0 INTIN 0 INTIN 1 INTIN 2 INTIN l DMAC transfer factor 0 DMAC transfer factor 1 DMAC transfer factor 2 DMAC transfer factor l DMAC transfer completion interrupts INTDMA 7 0 DMAC transfer count match interrupts INTCT 7 0 INTIN l 0 DMAC transfer factors l 0 DMAC transfer requests 7 0 ...

Page 199: ...he top priority FFFF_FFFFH 0FFF_FFFFH 0200_3FFFH 01FF_FFFFH 0005_FFFFH 0200_4000H 0200_0000H 0006_0000H 0000_0000H FFFF_7FFFH FF83_FFFFH FF3F_FFFFH FEDF_FFFFH FEDF_9FFFH FFFF_8000H FF84_0000H FF40_0000H FEE0_0000H FEDF_A000H Memory Map Upper 256 Mbytes On chip peripheral I O PBUS area On chip peripheral I O PBUS area On chip RAM area 24 Kbytes Access prohibited Access prohibited Access prohibited ...

Page 200: ...priority control Fixed priority highest priority CH0 lowest priority CH7 Targets for transfer Code flash On chip RAM Data flash Peripheral I O area Transfer type Two cycle transfer dual address transfer The addresses at both the transfer source and destination are accessed Two bus cycles are required to execute transfer once read cycles write cycles The bus is not locked between the read cycles an...

Page 201: ...MA transfer request can be selected for each channel by setting the DTRSn register A software DMA transfer request can be set by software by setting the DTS register This register also has a status bit DTS register to indicate when a hardware DMA transfer request has been generated Interrupt output upon a match of transfer count This function has a transfer count compare register DTCCn for each ch...

Page 202: ...estination address register CH0 00000000H FFFF732CH DNDA0L DMA next destination address register LCH0 0000H FFFF732EH DNDA0H DMA next destination address register HCH0 0000H FFFF7330H DNDC0 DMA next destination chip select register CH0 0001H FFFF7332H DTC0 DMA transfer count register CH0 0000H FFFF7334H DNTC0 DMA next transfer count register CH0 0000H FFFF7336H DTCC0 DMA transfer count compare reg...

Page 203: ...ddress register HCH2 0000H FFFF7380H DNSC2 DMA next source chip select register CH2 0001H FFFF7384H DDA2 DMA destination address register CH2 00000000H FFFF7384H DDA2L DMA destination address register LCH2 0000H FFFF7386H DDA2H DMA destination address register HCH2 0000H FFFF7388H DDC2 DMA destination chip select register CH2 0001H FFFF738CH DNDA2 DMA next destination address register CH2 00000000...

Page 204: ...sfer status register CH3 00H FFFF73D0H DTRS4 DMA transfer request select register CH4 0000H FFFF73D4H DSA4 DMA source address register CH4 00000000H FFFF73D4H DSA4L DMA source address register LCH4 0000H FFFF73D6H DSA4H DMA source address register HCH4 0000H FFFF73D8H DSC4 DMA source chip select register CH4 0001H FFFF73DCH DNSA4 DMA next source address register CH4 00000000H FFFF73DCH DNSA4L DMA ...

Page 205: ...F741CH DNDA5L DMA next destination address register LCH5 0000H FFFF741EH DNDA5H DMA next destination address register HCH5 0000H FFFF7420H DNDC5 DMA next destination chip select register CH5 0001H FFFF7422H DTC5 DMA transfer count register CH5 0000H FFFF7424H DNTC5 DMA next transfer count register CH5 0000H FFFF7426H DTCC5 DMA transfer count compare register CH5 0000H FFFF7428H DTCT5 DMA transfer ...

Page 206: ...ister LCH7 0000H FFFF7468H DSC7 DMA source chip select register CH7 0001H FFFF746CH DNSA7 DMA next source address register CH7 00000000H FFFF746CH DNSA7L DMA next source address register LCH7 0000H FFFF746EH DNSA7H DMA next source address register HCH7 0000H FFFF7470H DNSC7 DMA next source chip select register CH7 0001H FFFF7474H DDA7 DMA destination address register CH7 00000000H FFFF7474H DDA7L ...

Page 207: ... prohibited while DMA transfer is enabled However all of the registers are always readable Note n 0 to 7 Table 5 5 Availability of Writing to Control Registers Availability of Writing Register Name Always writable DTRC0 DNSAnL DNSAnH DNSCn DNDAnL DNDAnH DNDCn DNTCn DTSn Writing prohibited while DMA transfer is enabled DTSnDTE 1 Operation is not guaranteed if writing to these registers is attempted...

Page 208: ...R R R R R W Bit Position Bit Name Function 7 DTRC0ERR DMA transfer error status This bit indicates that an error response has been received from a target for transfer during DMA transfer To clear this bit write 0 to it 0 No DMA transfer error 1 DMA transfer error Note If an error response is received the DTRC0ERR and DTRC0ADS bits are set and a SysError exception is generated for the CPU 0 DTRC0AD...

Page 209: ...1 Writing to these bits is prohibited while DMA transfer is enabled DTSnDTE bit 1 Operation is not guaranteed if this is attempted Caution 2 Operation is also not guaranteed if a prohibited setting is made in DTRSnDTR 3 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 R R R R R R R R 7 6 5 4 3 2 1 0 0 0 0 0 DTRSn DTR3 DTRSn DTR2 DTRSn DTR1 DTRSn DTR0 R R R R R W R W R W R W Bit Position Bit Name Function 3...

Page 210: ...orted The 4 lower order bits of addresses corresponding to the transfer data size are as follows x indicates any value Operation is not guaranteed if settings other than the following are made 15 14 13 12 11 10 9 8 DSAn SA15 DSAn SA14 DSAn SA13 DSAn SA12 DSAn SA11 DSAn SA10 DSAn SA9 DSAn SA8 R W R W R W R W R W R W R W R W 7 6 5 4 3 2 1 0 DSAn SA7 DSAn SA6 DSAn SA5 DSAn SA4 DSAn SA3 DSAn SA2 DSAn ...

Page 211: ...ss in 32 bit units while the DTSnDTE bit is 0 because data transfer is not possible from an address for which setting is in progress 15 14 13 12 11 10 9 8 0 0 0 DSAn SA28 DSAn SA27 DSAn SA26 DSAn SA25 DSAn SA24 R R R R W R W R W R W R W 7 6 5 4 3 2 1 0 DSAn SA23 DSAn SA22 DSAn SA21 DSAn SA20 DSAn SA19 DSAn SA18 DSAn SA17 DSAn SA16 R W R W R W R W R W R W R W R W Bit Position Bit Name Function 12 t...

Page 212: ...s prohibited while DMA transfer is enabled DTSnDTE bit 1 Operation is not guaranteed if this is attempted Caution 2 Set the DSCnSCS0 and DSCnSCSE bits so that only one of them is 1 Operation is not guaranteed if both bits are set to 1 Caution 3 Be sure to set the DSCnSCS1 bit to 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 R R R R R R R R 7 6 5 4 3 2 1 0 0 0 0 0 0 DSCn SCS1 DSCn SCS0 DSCn SCSE R R R R ...

Page 213: ...isaligned data is not supported The 4 lower order bits of addresses corresponding to the transfer data size are as follows x indicates any value Operation is not guaranteed if settings other than the following are made 15 14 13 12 11 10 9 8 DNSAn NSA15 DNSAn NSA14 DNSAn NSA13 DNSAn NSA12 DNSAn NSA11 DNSAn NSA10 DNSAn NSA9 DNSAn NSA8 R W R W R W R W R W R W R W R W 7 6 5 4 3 2 1 0 DNSAn NSA7 DNSAn ...

Page 214: ... source 15 14 13 12 11 10 9 8 DNSAn NSAV 0 0 DNSAn NSA28 DNSAn NSA27 DNSAn NSA26 DNSAn NSA25 DNSAn NSA24 R W R R R W R W R W R W R W 7 6 5 4 3 2 1 0 DNSAn NSA23 DNSAn NSA22 DNSAn NSA21 DNSAn NSA20 DNSAn NSA19 DNSAn NSA18 DNSAn NSA17 DNSAn NSA16 R W R W R W R W R W R W R W R W Bit Position Bit Name Function 15 DNSAnNSAV DMA next source address valid This bit controls whether to copy the address fro...

Page 215: ...set the DNSCnNSCS1 bit to 0 15 14 13 12 11 10 9 8 DNSCn NSCV 0 0 0 0 0 0 0 R W R R R R R R R 7 6 5 4 3 2 1 0 0 0 0 0 0 DNSCn NSCS1 DNSCn NSCS0 DNSCn NSCSE R R R R R R W R W R W Bit Position Bit Name Function 15 DNSCnNSCV DMA next source address select valid This bit controls whether to copy the chip select signal from the DMA next source chip select register to the DMA source chip select register ...

Page 216: ...nation address is still updated Caution 4 DMA transfer of misaligned data is not supported The 4 lower order bits of addresses corresponding to the transfer data size are as follows x indicates any value Operation is not guaranteed if settings other than the following are made 15 14 13 12 11 10 9 8 DDAn DA15 DDAn DA14 DDAn DA13 DDAn DA12 DDAn DA11 DDAn DA10 DDAn DA9 DDAn DA8 R W R W R W R W R W R ...

Page 217: ...ddress for which setting is in progress Caution 3 If an error occurs in the target for transfer in a cycle of reading for DMA transfer the corresponding write cycle is not executed but the destination address is still updated 15 14 13 12 11 10 9 8 0 0 0 DDAn DA28 DDAn DA27 DDAn DA26 DDAn DA25 DDAn DA24 R R R R W R W R W R W R W 7 6 5 4 3 2 1 0 DDAn DA23 DDAn DA22 DDAn DA21 DDAn DA20 DDAn DA19 DDAn...

Page 218: ...ohibited while DMA transfer is enabled DTSnDTE bit 1 Operation is not guaranteed if this is attempted Caution 2 Set the DDCnDCS0 and DDCnDCSE bits so that only one of them is 1 Operation is not guaranteed if both bits are set to 1 Caution 3 Be sure to set the DDCnDCS1 bit to 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 R R R R R R R R 7 6 5 4 3 2 1 0 0 0 0 0 0 DDCn DCS1 DDCn DCS0 DDCn DCSE R R R R R R ...

Page 219: ...isaligned data is not supported The four lower order bits of addresses corresponding to the transfer data size are as follows x indicates any value Operation is not guaranteed if settings other than the following are made 15 14 13 12 11 10 9 8 DNDAn NDA15 DNDAn NDA14 DNDAn NDA13 DNDAn NDA12 DNDAn NDA11 DNDAn NDA10 DNDAn NDA9 DNDAn NDA8 R W R W R W R W R W R W R W R W 7 6 5 4 3 2 1 0 DNDAn NDA7 DND...

Page 220: ... 15 14 13 12 11 10 9 8 DNDAn NDAV 0 0 DNDAn NDA28 DNDAn NDA27 DNDAn NDA26 DNDAn NDA25 DNDAn NDA24 R W R R R W R W R W R W R W 7 6 5 4 3 2 1 0 DNDAn NDA23 DNDAn NDA22 DNDAn NDA21 DNDAn NDA20 DNDAn NDA19 DNDAn NDA18 DNDAn NDA17 DNDAn NDA16 R W R W R W R W R W R W R W R W Bit Position Bit Name Function 15 DNDAnNDAV DMA next destination address valid This bit controls whether to copy the address from ...

Page 221: ...he DNDCnNDCS1 bit to 0 15 14 13 12 11 10 9 8 DNDCn NDCV 0 0 0 0 0 0 0 R W R R R R R R R 7 6 5 4 3 2 1 0 0 0 0 0 0 DNDCn NDCS1 DNDCn NDCS0 DNDCn NDCSE R R R R R R W R W R W Bit Position Bit Name Function 15 DNDCnNDCV DMA next destination chip select valid This bit controls whether to copy the chip select signal from the DMA next destination chip select register to the DMA destination chip select re...

Page 222: ...ted 15 14 13 12 11 10 9 8 0 DTCnDTC1 4 DTCnDTC1 3 DTCnDTC1 2 DTCnDTC1 1 DTCnDTC1 0 DTCnDTC9 DTCnDTC8 R R W R W R W R W R W R W R W 7 6 5 4 3 2 1 0 DTCnDTC7 DTCnDTC6 DTCnDTC5 DTCnDTC4 DTCnDTC3 DTCnDTC2 DTCnDTC1 DTCnDTC0 R W R W R W R W R W R W R W R W Bit Position Bit Name Function 14 to 0 DTCnDTC14 to DTCnDTC0 DMA transfer count These bits specify the number of times DMA transfer DMA transfer coun...

Page 223: ... W R W R W R W R W R W 7 6 5 4 3 2 1 0 DNTCn NDTC7 DNTCn NDTC6 DNTCn NDTC5 DNTCn NDTC4 DNTCn NDTC3 DNTCn NDTC2 DNTCn NDTC1 DNTCn NDTC0 R W R W R W R W R W R W R W R W Bit Position Bit Name Function 15 DNTCnNTCV DMA next transfer count valid This bit controls whether or not copying of the number of DMA unit transfers DMA transfer count from the DMA next transfer count register to the DMA count regi...

Page 224: ... 9 8 0 DTCCn DTCC14 DTCCn DTCC13 DTCCn DTCC12 DTCCn DTCC11 DTCCn DTCC10 DTCCn DTCC9 DTCCn DTCC8 R R W R W R W R W R W R W R W 7 6 5 4 3 2 1 0 DTCCn DTCC7 DTCCn DTCC6 DTCCn DTCC5 DTCCn DTCC4 DTCCn DTCC3 DTCCn DTCC2 DTCCn DTCC1 DTCCn DTCC0 R W R W R W R W R W R W R W R W Bit Position Bit Name Function 14 to 0 DTCCnDTCC14 to DTCCnDTCC0 DMA transfer count comparison DTCC 14 0 specifies a number of tim...

Page 225: ...5 4 3 2 1 0 DTCTn SACM1 DTCTn SACM0 DTCTn DACM1 DTCTn DACM0 0 0 0 0 R W R W R W R W R R R R Bit Position Bit Name Function 14 13 DTCTnDS1 DTCTnDS0 DMA transfer data size These bits specify the DMA transfer data size of channel n 12 DTCTnMLE Multi link enable This bit specifies whether to acknowledge the next DMA transfer request without clearing the DTSnTC bit to 0 after DMA transfer has been comp...

Page 226: ...nSACM0 DMA transfer source address counting direction These bits specify the direction up or down in which counting from the transfer source address for channel n is to proceed 5 4 DTCTnDACM1 DTCTnDACM0 DMA transfer destination address counting direction These bits specify the direction up or down in which counting from the transfer destination address for channel n is to proceed Bit Position Bit ...

Page 227: ...ng to this bit can proceed at the same time as writing to the DTSnDTE bit 0 DMA transfer request acknowledged 1 DMA transfer in progress 3 DTSnER DMA transfer error flag This bit indicates that a DMA transfer error has occurred in channel n It is cleared to 0 when the DTRC0ERR bit of the DTRC0 register is cleared Note that this bit is read only 0 No DMA transfer error 1 DMA transfer error 2 DTSnDR...

Page 228: ...ansfer After a 1 is written to this bit DMA transfer is executed once a DMA transfer request is issued This bit is automatically cleared to 0 on completion of DMA transfer if the DTCTnMLE bit is 0 DMA transfer is suspended if 0 is written to this bit during DMA transfer 0 DMA transfer is disabled 1 DMA transfer is enabled Bit Position Bit Name Function ...

Page 229: ... software request Set DTS DTSnDTE 1 DMA transfer enabled Hardware DMA transfer request Software DMA transfer request Set DTRS software request Set DTRS except for software request Set DTS DTSnDTE 1 enable DMA transfer Set DTS DTSnTC 0 TC clear Hardware DMA transfer request Transfer completed Transfer completed Set DTS DTSnDTE 1 enable DMA transfer DTSnSR 1 software request Set DTS DTSnTC 0 TC clea...

Page 230: ... a hardware DMA transfer request is acknowledged the amount of data specified as the unit of data transfer 8 16 32 or 128 bits is transferred Each time transfer of this amount is executed the bus is released and the DMA controller waits for a DMA transfer request The acknowledge n signal n 7 to 0 which indicates that a hardware DMA transfer request has been acknowledged is also output at this time...

Page 231: ...ach time transfer is executed so a DMA cycle for a channel having a higher priority may interrupt transfer in response to a software DMA request Figure 5 6 Example of Single Step Transfer 8 16 32 Bits DMA Channel Priority CH0 High CH1 Low DMA1 Read DMA1 Read DMA1 Read DMA0 Read DMA1 Read DMA1 Write DMA1 Write DMA1 Write DMA1 Write DMA0 Write CPU CPU CPU CPU CPU CPU CPU CPU CH0 CH1 Transfer complet...

Page 232: ...U CPU CPU CPU CPU CPU CH0 CH1 DMA1 Read DMA1 Read DMA1 Read DMA1 Read DMA0 Read DMA1 Write DMA1 Write DMA1 Write DMA1 Write DMA1 Write Software DMA transfer request CH1 DMA transfer count setting 1 time Hardware DMA transfer request 0 input Acknowledge 0 output Transfer completed Note The bus is always released When the CPU requests the bus mastership the CPU acquires the bus mastership ...

Page 233: ...requests since the bus is also released after every DMA cycle in response to a software DMA transfer request The following figure shows an example where a next DMA transfer request with higher priority is generated while DMA transfer is in progress Figure 5 8 Example of Priority Control CPU CPU CPU CPU CPU CPU CPU DMA3 DMA2 DMA0 CPU DMA1 DMA2 DMA3 DMA3 CPU CH0 CH1 CH2 CH3 Hardware DMA transfer req...

Page 234: ...owing table lists the relationship between the settings of these bits and whether a DMA transfer request is or is not acknowledged Note n 0 to 7 Table 5 6 Conditions for Validity of Requests for DMA Transfer on Channel n Register Bit Name DTSn DTSnDTE DTSn DTSnTC DTCTn DTCTnMLE DTRC0 DTRC0ERR DTRC0 DTRC0ADS DMA Transfer Request When DMA transfer is disabled 0 X X X X Invalid When DMA transfer erro...

Page 235: ... Transfer Completion when Using Next Address Function Normally upon completion of DMA transfer the DMA transfer enable bit DTSnDTE is cleared at the same time the DMA transfer completion status bit DTSnTC of the DMA transfer status register DTSn is set and subsequent DMA transfer requests are no longer acknowledged However if the multilink enable bit DTCTnMLE is set DTSnDTE is not cleared and DMA ...

Page 236: ...ear 2 Suspending or Resuming DMA Transfer by Using DMA Transfer Enable Bit DTSnDTE Subsequent DMA transfer can be suspended by clearing the DMA transfer enable bit DTSnDTE of the DMA transfer status register DTSn When this is done during a DMA cycle DMA transfer is suspended on completion of the ongoing DMA cycle Note that the software DMA transfer request bit DTSnSR for the DTSn is not cleared To...

Page 237: ...ER of the DMA transfer status register DTSn can be used to identify the channel where the error occurred In this case note that if the error response is acknowledged within the read cycle the write cycle does not proceed but the transfer address and transfer count are updated 2 Canceling Transfer Suspension Due to Error Response DMA transfer suspension can be reversed by clearing the DMA transfer ...

Page 238: ...void this use the DMA request clearing register DRQCLR to clear the transfer activating source flag just before transfer is enabled 5 7 1 Features Number of transfer sources DMA transfer requests for 8 channels are selected from among the m 108 interrupt signals DMAC interface The DMA transfer request signal n n 7 to 0 is output The DMA transfer request signal n is cleared by an acknowledge signal...

Page 239: ...B0CH DTFR7 FFFF 7B0EH Initial value 0000H This register is initialized by a reset from any source 15 14 13 12 11 10 9 8 DTFRn REQEN 0 0 0 0 0 0 0 R W R R R R R R R 7 6 5 4 3 2 1 0 0 IFCn 6 0 R R W R W R W R W R W R W R W Bit Position Bit Name Function 15 DTFRnREQEN This bit enables or disables operation of the DMA activating source selector for channel n 1 The source selector operates 0 The source...

Page 240: ...1 in this bit clears a transfer request held for channel 6 to 0 5 RQCR5 This is a control bit for clearing the DMA request check register DRQSTR RQST5 bit Setting 1 in this bit clears a transfer request held for channel 5 to 0 4 RQCR4 This is a control bit for clearing the DMA request check register DRQSTR RQST4 bit Setting 1 in this bit clears a transfer request held for channel 4 to 0 3 RQCR3 Th...

Page 241: ...uest DMA transfer request signal 7 is 0 6 RQST6 1 Request issued DMA transfer request signal 6 is 1 0 No request DMA transfer request signal 6 is 0 5 RQST5 1 Request issued DMA transfer request signal 5 is 1 0 No request DMA transfer request signal 5 is 0 4 RQST4 1 Request issued DMA transfer request signal 4 is 1 0 No request DMA transfer request signal 4 is 0 3 RQST3 1 Request issued DMA transfe...

Page 242: ... If the dedicated flash programmer is to program on chip memory it has to be connected to the target system For self programming an application program is used instead of the dedicated flash programmer Flash memory is commonly used for the following purposes in the development environment and field of application altering software after solder mounting of the microcontroller on the target system d...

Page 243: ...efer to section 9 Safety Functions for details Methods of erasure and programming Support for Nexus Support for serial interfaces one line UART and three line CSI HS Support for programming by the dedicated flash programmer Support for self programming Other supported functions Prohibition of erasure and programming security function Boot changeover boot swapping Note While writing to the code fla...

Page 244: ...yte read or write is possible for data flash Attempt read or write in 4 byte or 1 byte units leads to a SYSERR exception if SEG_CONT SEG_CONTEXTE 1 6 1 3 On Chip RAM RAM capacity 24 Kbytes Caution The size of the block for the code flash memory in this product is 32 Kbytes Since the size of the on chip RAM is smaller than the block unit of the code flash memory divide the programming accordingly w...

Page 245: ...upply the operating clock for this product by mounting oscillators and capacitors to configure an oscillation circuit on the same board as this product 6 3 Communications Methods 1 Nexus communications Transfer rate 25 MHz max 2 LPD single pin debugging communications Transfer rate 2Mbps max When the E1 emulator is used 3 One line UART communications Transfer rate 1 Mbps max 4 Three line CSI HS co...

Page 246: ...cluding flash self programming 6 4 2 Pins Pins to be used for each interface are as follows Nexus FLMD0 RESET DCUTRST DCUTCK DCUTMS DCUTDI DCUTDO DCUTRDY LPD single pin debugging LPDIO FLMD0 RESET One line UART RxD TxD FLMD0 RESET Three line CSI HS SI SO SCK FLMD0 RESET When connecting pins for interfaces which are already connected to other devices on the board to the dedicated flash programmer t...

Page 247: ...nput keep the pin at the high level until flash memory operations are completed 6 4 5 Port Pins All port pins other than those for communications with the dedicated flash programmer will be in the high impedance state when the settings for flash memory programming mode are made No adjustment is required for these pins However if a pin being in the high impedance state is not acceptable for an exte...

Page 248: ...or writing to them Operation of the product with option bytes erased is not guaranteed For details refer to Section 6 OPBT0 Option Byte Verification Register Caution When the chip is erased the FOP option byte setting is also initialized HEAPCLK 48 MHz PCLK 1 4 HEAPCLK Therefore set the serial communication rate within the range shown below and re set the FOP One line UART communications Baud rate...

Page 249: ...7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 FOP3 FOP2 FOP1 1 R R R R R R R R R R R R R W R W R W R Table 6 5 Option Byte Verification Register of V850E2 PG4 L Products Bit Position Bit Name Function 31 FOP31 Switches the JTAG port 0 Port function 1 JTAG Nexus When connecting the port to a development tool set this bit to 1 disabled 23 FOP23 Enables or disables output of the toggled signal TGLOUT 0 TGL...

Page 250: ... 1 00 of the μPD70F4154 103B0100H version 1 00 of the μPD70F4155 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 1 0 0 0 0 0 0 1 1 1 0 1 0 1 R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 R R R R R R R R R R R R R R R R Table 6 6 PRDNAME Register Contents Bit Position Function 31 to 12 Bits 31 to 12 Description 10...

Page 251: ...nitial value FEDF A001H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 1 1 1 1 1 1 0 1 1 0 1 1 1 1 1 R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 R R R R R R R R R R R R R R R R Table 6 7 PRDSELH Register Contents Bit Position Function 31 to 8 31 to 8 Bits Description FEDFA0H Address where on chip RAM starts FEDF A000H 7 to 0 7 to 0 Bits ...

Page 252: ...0020H Initial value 8000 10FFH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 0 0 0 0 1 1 1 1 1 1 1 1 R R R R R R R R R R R R R R R R Table 6 8 PRDSELL Register Contents Bit Position Function 31 to 24 31 to 24 Bits Description 80H Code flash memory 384 Kbytes 23 to 8 23 to 8 Bits Descript...

Page 253: ...programming is not in the specified sequence the FLMDPREPP bit in the FLMDPS register is set to 1 to indicate the protection error For details refer to Section 6 7 2 Setting the FLMDCNT Register Access This register can be read written in 8 bit units Address FF43 8000H Initial value 00H This register is initialized by a reset from any source Table 6 10 FLMDCNT Register Contents Register Name Symbo...

Page 254: ...s whether writing to the write protection register FLMDCNT was successful or not For details refer to Section 6 7 2 Setting the FLMDCNT Register Access This register can be read in 8 bit units Address FF43 8008H Initial value 00H This register is initialized by a reset from any source Table 6 12 FLMDPS Register Contents 7 6 5 4 3 2 1 0 FLMDPCMD 7 0 W W W W W W W W Bit Position Bit Name Function 7 ...

Page 255: ... setting registers can proceed during the sequence without preventing its completion The protection function operates as follows when the sequence is suspended Suspension of the sequence due to the arrival of an interrupt If an interrupt request is accepted while the above specified sequence for writing is in progress and the interrupt service routine does not access any of the FLMD pin setting re...

Page 256: ...Section 7 Clock Generation The clock generator CG controls the internal system clocks that are supplied to individual on board units such as the CPU It also monitors the input clock to detect abnormalities and has a baud rate generator to produce the desired output clock signal on the CLKOUT pin ...

Page 257: ...s the WDTCLKI clock and generates reset signals This product does not support the generation of interrupt request signals by CLMA0 CLMA1 monitors the internal system clock and generates reset and interrupt request signals CLMA2 monitors the internal oscillator and generates reset and interrupt request signals Clock output The frequency of the signal output on the CLKOUT pin is adjustable Note For ...

Page 258: ...128 1 2 CLMA0 CLMA2 SEL SEL SCLK1 M S M S INTCLMA2 WDTCLKI LPDCLK BRGA0 CLKOUT pin CLMA1 INTCLMA1 CLMA1RES PCLK BRGA0TCLK S M Checker CPU system CLK Master CPU system CLK Timer Internal PRS and BRG Serial Internal PRS and BRG CAN Internal PRS and BRG A D Internal PRS and BRG CLMA0RES CLMA2RES Note 1 When the frequency of the main oscillator OSC is 8 MHz Note 2 When the frequency of the main oscill...

Page 259: ... Connectable to the X1 and X2 Pins The 8 or 16 MHz signal from the external resonator is input to PLL1 which produces a frequency multiplied clock signal for supply that is supplied to the CPU as the operating clock and to peripheral I O via the prescaler Table 7 1 Oscillators Connectable to the X1 and X2 Pins Table 7 2 Operating Frequency Note For input frequency and multiplier settings refer to ...

Page 260: ... provides the clock for the main systems and is input to the PLL The oscillator circuit requires the connection of an external resonator between X1 and X2 PLL1 The PLL1 circuit generates the clock signal for use in driving the microcontrollers The clock signal output from PLL1 is divided by one or two and then supplied to peripheral input and output Resetting the clock generating circuit The clock...

Page 261: ... in the BRGA0CMP register If BRGA0CTL BRGA0ODIS 1 the low level is output on CLKOUT When the counter reaches the value for comparison set in BRGA0CMP BRGA0CMP 7 0 the BRGA0 interrupt INTBRG0 is generated Note When BRGA0CMP BRGA0CMP 7 0 00H the initial counting value is 01H and the sequence of counting is 02H 03H FEH FFH 00H Comparison after the overflow of the counter overflows produces a match Ca...

Page 262: ...itor registers is given below Table 7 3 Clock Source for BRGA0 BRGA0 Clock Source BRGATCLK Clock selected in the BRGCKCTL register SCLK1 or PCLK Table 7 4 BRGA Interrupt BRGA Signal Function Connected to INTBRG0 BRGA0 interrupt signal Interrupt controller Table 7 5 List of Registers in the Baud Rate Generator for CLKOUT Register Name Symbol Address BRGA0 flag register BRGA0FLG FFFF FD00H BRGA0 con...

Page 263: ...H Initial value 00H This register is initialized by a reset from any source Table 7 6 BRGCKCTL Register Contents Caution Write to BRGCKCTL selection of BRGA0 operation clock while BRGA0 is stopped the BRGA0CE bit of the BRGA0CTL register 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 BRGCKSL1 BRGCKSL0 R R R R R R R W R W Bit Position Bit Name Function 1 0 BRGCKSL1 BRGCKSL0 This register selects the input clock sig...

Page 264: ... reset from any source 7 6 5 4 3 2 1 0 0 0 0 BRGA0CE 0 BRGA0 ODIS BRGA0 CCS1 BRGA0 CCS0 R R R R W R R W R W R W Table 7 7 BRGA0CTL Register Contents Bit Position Bit Name Function 4 BRGA0CE This bit enables or disables operation of the baud rate counter 0 Baud rate counter operation is disabled INTBRG0 interrupts will not be generated 1 Enable baud rate counter operation INTBRG0 interrupts will be...

Page 265: ... confirm that the baud rate counter is stopped BRGA0FLG BRGA0CEF 0 The level of the CLKOUT signal and timing of INTBRG0 interrupts become undefined when the setting of the BRGA0CTL BRGA0CE bit is 0 and 1 is written to BRGA0CTL BRGA0CE bit while the baud rate counter is not stopped BRGA0FLG BRGA0CEF 1 Caution 3 BRGA0CTL BRGA0CE is synchronized with BRGA0TCLK so synchronization requires 3 clock cycl...

Page 266: ...ration status of the baud rate counter Access This register can be read in 8 bit units Address FFFF FD00H Initial value 00H This register is initialized by a reset from any source 7 6 5 4 3 2 1 0 BRGA0CMP 7 0 R W R W R W R W R W R W R W R W Table 7 8 BRGA0CMP Register Contents Bit Position Bit Name Function 7 to 0 BRGA0CMP 7 0 Value for comparison 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 BRGA0 CEF R R R R R ...

Page 267: ...clock will not stop until the voltage is cut off once it starts operating during single pin debugging LPDRES high level Therefore even when a reset is generated during single pin debugging the Main OSC and PLL1 never stop However the other clocks operate in the same way as in single chip mode during single pin debugging 7 7 WDTA0 Count Clock WDTCLKI WDTCLKI SCLK1 32 is the input clock for WDTA0 in...

Page 268: ...ble below Clock supply The monitored and the sampling clocks of all clock monitors A are listed in the following table Table 7 10 Instances Clock Monitor A Number of instances 3 Name CLMAn Table 7 11 Register Base Address CLMAn_base CLMAn CLMAn_base Address CLMA0 FF80_2000H CLMA1 FF80_3000H CLMA2 FF80_4000H Table 7 12 CLMAn Clock Supply Clocks for CLMAn Function Connected to CLMA0 CLMA0TSMP Sampli...

Page 269: ...RES CLMA1 error reset Reset controller CLMA1RES CLMA1TI CLMA1 error interrupt request Interrupt controller INTCLMA1 CLMA2 CLMA2RES CLMA2 error reset Reset controller CLMA2RES CLMA2TI CLMA2 error interrupt request Interrupt controller INTCLMA2 Table 7 14 Output Signals from CLMAn CLMAn Signal Function Connected to CLMA0 CLMA0TERR Error output signal from CLMA0 Safety guardian CLMA0RES Error reset s...

Page 270: ...the frequency of an input clock CLMAnTMON by using a sampling clock CLMAnTSMP indication of abnormal clock frequencies by the following means output of a reset request signal or output of an error signal in combination with the generation of an error interrupt request The following figure shows the main components of the clock monitor Figure 7 2 Block Diagram of the Clock Monitor A Note Abnormalit...

Page 271: ...r falls below CLMAnCMPL CLMAnCMPL 11 0 3 When the frequency of CLMAnTMON is too high the counter exceeds CLMAnCMPH CLMAnCMPH 11 0 In both cases CLMAn indicates an abnormal clock frequency as described in Section 7 8 4 2 Indication of Abnormal Clock Frequency Figure 7 3 Example fCLMAnTMON is low Figure 7 4 Example fCLMAnTMON is high Note When fCLMAnTMON changes within the sampling interval 16 cycle...

Page 272: ...umber of clock cycles is denoted by N Considering the allowed frequency deviations of CLMAnTMON and CLMAnTSMP the threshold values can be calculated by the following formulas Note For examples of CLMAnCMPH and CLMAnCMPL registers of this product refer to Table 7 16 Examples of CLMAnCMPH and CLMAnCMPL Register Settings Minimum thresholds The following restrictions must be taken into account CLMAnCM...

Page 273: ...o the current setting of CLMAnCTL1 CLMAnOSEL Figure 7 6 Indication of Clock Abnormality when fCLMAnTMON Falls below the Lower Threshold when CLMAnCTL1 CLMAnOSEL 1 CLMAnTI CLMAnTERR CLMAnRES PERRES 2 1 Table 7 15 When fCLMAnTMON is too Low CLMAnCTL1 CLMAnOSEL Indication of Clock Abnormality when fCLMAnTMON Falls below the Upper Threshold 0 CLMAn outputs a reset request signal CLMAnRES active low Th...

Page 274: ...s in the sequence below to set the CLMAnCTL0 register to 01H 1 Write A5H to the CLMAnPCMD register 2 The following sequence is required for writing to the CLMAnCTL0 register Write 01H to enable CLMAn Write the inverse of that value i e FEH Write the intended value 01H again 3 Read the CLMAnCTL0 register If the value of the register is 01H CLMAn is enabled If this was not the value check the settin...

Page 275: ...the chip will not be released from the reset state Caution After CLMAnRES is asserted check whether the main oscillator PLL1 internal oscillator and WDTCLKI are operating normally To do so check the RESF register and start the CLMAn operating to monitor their frequencies when the CPU starts operating Table 7 16 Examples of CLMAnCMPH and CLMAnCMPL Register Settings Operating Frequency Main OSC Moni...

Page 276: ...d peripheral functions in this case is not guaranteed b After a CLMA2 Error Interrupt Request CLMA2TI The error signal is conveyed to the SGA If the internal oscillator is stopped even if oscillation of the main oscillator is abnormal the problem will not be detectable by CLM0 or CLM1 so the operation of the CPU and peripheral functions cannot be guaranteed If the internal OSC is stopped at that t...

Page 277: ...ns For details refer to Section 7 8 4 3 Enabling CLMAn Writing to the CLMAnCTL0 Register Address CLMAn_base 00H Initial value 00H This register is initialized by a reset from any source Table 7 17 List of Clock Monitor Registers Register Name Symbol Address CLMAn control register 0 CLMAnCTL0 CLMAn_base 00H CLMAn control register 1 CLMAnCTL1 CLMAn_base 04H CLMAn compare register L CLMAnCMPL CLMAn_b...

Page 278: ...AnCLME 0 Address CLMAn_base 04H Initial value 00H This register is initialized by a reset from any source Caution When the Internal OSC is halted an internal reset is not generated Even when the CLMA2CTL1 CLMA2OSEL bit is set to 0 reset request signal SGA detects the halt of the Internal OSC and the ERROROUT pin outputs the low level 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 CLMAn OSEL R R R R R R R R W Table...

Page 279: ...n 16 bit units It can only be written when CLMAn is disabled CLMAnCTL0 CLMAnCLME 0 Address CLMAn_base 0CH Initial value 03FFH This register is initialized by a reset from any source 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 CLMAnCMPH 11 0 R R R R R W R W R W R W R W R W R W R W R W R W R W R W Table 7 20 CLMAnCMPH Register Contents Bit Position Bit Name Function 11 to 0 CLMAnCMPH 11 0 Specifie...

Page 280: ...ten in 16 bit units It can be written only when CLMAn is disabled CLMAnCTL0 CLMAnCLME 0 Address CLMAn_base 08H Initial value 0001H This register is initialized by a reset from any source 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 CLMAnCMPL 11 0 R R R R R W R W R W R W R W R W R W R W R W R W R W R W Table 7 21 CLMAnCMPL Register Contents Bit Position Bit Name Function 11 to 0 CLMAnCMPL 11 0 Spe...

Page 281: ...TL0 was successful For details refer to Section 7 8 4 3 Enabling CLMAn Writing to the CLMAnCTL0 Register Access This register can be read in 8 bit units Address CLMAn_base 14H Initial value 00H This register is initialized by a reset from any source 7 6 5 4 3 2 1 0 CLMAnREG 7 0 W W W W W W W W Table 7 22 CLMAnPCMD Register Contents Bit Position Bit Name Function 7 to 0 CLMAnREG 7 0 Protection comm...

Page 282: ...MA0RES to CLMA2RES Low voltage indicator reset LVIRES Software reset SWRES Safety guardian reset SGARES Self diagnostic BIST reset BISTRES Debug reset DBRES The following block diagram shows the main components of the reset controller Figure 8 1 Block Diagram of the Reset Controller Reset controller Watchdog timer reset Clock monitor CLMA0 reset Clock monitor CLMA1 reset Clock monitor CLMA2 reset ...

Page 283: ...ic BIST is executed on release from the reset state Note 4 All other RESF flags are cleared by SYSRES RESET DBRES Note 5 For a list of the reset sources refer to section 8 1 1 Internal Reset Signals Table 8 1 Reset Sources and Timing of Operations Reset Input Source Internal Reset Signals 1 Flash Reset Sequence Time 2 PLL Lock up Time 2 OSC Stabilization Time 2 Self Diagnostic BIST Execution 3 RES...

Page 284: ...C LVI clear reset LVICLR The LVI clear reset is generated by all reset sources except the LVIRES Peripheral reset PERRES The peripheral reset is generated by all reset sources Single pin debugging reset LPDRES The single pin debugging reset LPDRES is a dedicated reset signal for use in single pin debugging LPDRES is de asserted when the power supply is turned on Once LPDRES is de asserted it remai...

Page 285: ...ter RESF provides reset flags for each reset source If a reset has occurred the assigned flag is set This way the source of the reset can be evaluated All flags in RESF are only cleared by SYSRES or by software clear request via the RESFC register Thus the operation of these registers is cumulative each reset source sets its own flag independent of all others ...

Page 286: ...he LVIRES flag RESF RESF0 is set RESF RESF0 is not automatically cleared if VDD exceeds VLVI It is cleared by setting RESFC RESFC0 1 SYSRES LVI reference voltage For the specification of the internal reference voltage VLVI refer to Section 27 6 16 POF LVI Characteristics Generation of LVIRES The generation of an interrupt instead of LVIRES is selectable The following figure shows the timing of LVI...

Page 287: ... an analog noise filter to prevent erroneous resets due to noise The following figure shows the timing when an external reset is performed It explains the effect of the noise eliminator Figure 8 3 External RESET Timing The analog delay is caused by the analog filter The filter regards pulses up to a certain width as noise and suppresses them For the noise cancelling intervals see Table 2 51 List o...

Page 288: ...t if the watchdog time expires After a watchdog reset RESF RESF2 for the watchdog timer reset flag WDTA0RES is set RESF RESF2 is not automatically cleared It is cleared by setting RESFC RESFC2 1 SYSRES 8 2 5 Software Reset The software reset SWRES can be asserted by setting SWRESA SWRESA 1 RESF RESF1 is not automatically cleared It is cleared by setting RESFC RESFC1 1 SYSRES ...

Page 289: ...ponding monitor generates a reset CLMA0RES A failure in the main oscillation circuit is being detected CLMA1RES A failure in PLL1 is being detected CLMA2RES A failure in internal OSC is being detected Upon a clock monitor reset the respective reset flags in the RESF register are set These flags are not cleared automatically They are cleared by setting RESFC RESFC3 1 for CLMA0RES RESFC RESFC4 1 for...

Page 290: ...elf diagnostic BIST The generation of BISTRES is indicated by RESF RESF7 RESF RESF7 is not automatically cleared It is cleared by setting RESFC RESFC7 1 SYSRES 8 2 8 Safety Guardian Reset The safety guardian SGA collects all internal error signals from different monitoring units All error inputs connected to the SGA are able to generate the SGARES reset signal After a safety guardian reset the saf...

Page 291: ... is assumed The reset flag register RESF can be evaluated as described below Figure 8 4 Procedure for Evaluating and Handling the Reset Flag External reset RESET Safety guardian reset All resets except SGARES Faulty software restarting at address 0000 0000H Program starts at address 0000 0000H Read RESF register RESF Handling according to reset source SGARES occurred Read SGAmESSTER0 1 to determin...

Page 292: ...ster by checking that CSCPS CSCPRERR 0 In case of any access to the reset related registers between steps 1 to 4 of the above sequence of instructions the write to the protected register fails indicated by CSCPS CSCPRERR 1 and the entire sequence of instructions has to be restarted from step 1 Within the special sequence of instructions described above it is allowed to access other registers excep...

Page 293: ...o which no function is allocated Do not write values other than 0 to these bits because operation cannot be guaranteed if this is done Table 8 2 List of the Reset Controller Registers Register Name Symbol Address Reset flag registers Reset source register RESF FF42 0020H Reset source set register RESFS FF42 0024H Reset source clear register RESFC FF42 0028H Software reset control register Software...

Page 294: ...erated 7 RESF7 Self diagnostic BIST reset flag 0 The BISTRES reset is not being generated 1 The BISTRES reset is being generated This flag will always be set after the execution of self diagnostic BIST The state of the flag is retained as long as self diagnostic BIST is not executed again 6 RESF6 Safety guardian reset flag 0 The SGARES reset is not being generated 1 The SGARES reset is being gener...

Page 295: ... the RESFC register are in contention the setting for generation of the reset takes priority Note After writing to the RESFS and RESFC registers actual reflection of the written value in the register takes at least 6 cycles of the PLL input clock If a next value is written within less than 6 cycles the value may not be reflected in the register ...

Page 296: ...RESFC6 Controls clearing of the safety guardian reset flag the RESF RESF6 bit 0 No effect writing 0 to the bit does not affect the flag 1 RESF RESF6 is cleared 5 RESFC5 Controls clearing of the clock monitor CLMA2 reset flag the RESF RESF5 bit 0 No effect writing 0 to the bit does not affect the flag 1 RESF RESF5 is cleared 4 RESFC4 Controls clearing of the clock monitor CLMA1 reset flag the RESF ...

Page 297: ...the self diagnostic BIST reset flag RESF RESF7 0 No effect writing 0 to the bit does not affect the flag 1 RESF RESF7 is set 6 RESFS6 Sets the safety guardian reset flag RESF RESF6 0 No effect writing 0 to the bit does not affect the flag 1 RESF RESF6 is set 5 RESFS5 Sets the clock monitor CLMA2 reset flag RESF RESF5 0 No effect writing 0 to the bit does not affect the flag 1 RESF RESF5 is set 4 R...

Page 298: ...er CSCPCMD For details refer to the Section 8 2 10 Protection for Registers of the Reset Controller Address FF42 002CH Initial value 00H This register is initialized by a reset from any source Caution Do not use the software reset when data flash memory is operated Note After 1 is written to this register actual execution of the reset takes up to two cycles of the internal oscillator 7 6 5 4 3 2 1...

Page 299: ...ntroller 2 CSCPS Protection Status Register This register shows the status of the protection sequence operated by the CSCPCMD Access This register can be read in 8 bit units Writing to this register is ignored Address FF42 0018H Initial value 00H This register is initialized by a reset from any source 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 W W W W W W W W Table 8 7 CSCPCMD Register Contents Bit Position ...

Page 300: ...age The LVIMD bit in the LVICNT register is used to select the output of an interrupt or reset signal in response to detection of a low voltage An internal reset signal is output when the power supply voltage falls below the detection voltage this is the case when LVICNT LVIMD 1 An interrupt request signal is generated when the power supply voltage falls below the detection voltage this is the cas...

Page 301: ...upplied and when the voltage is cut off Note The state operating or stopped is not specifiable by software Caution When the power supply voltage for the internal regulator VDD falls below the POF detection voltage an external reset must be input Wait more than 6 ms before de asserting the external reset signal after individual power supply voltage exceeds the lower limit on guaranteed range of ope...

Page 302: ...Software handles at least 350 s of waiting time 4 Test the value of the LVISF LVISF bit to confirm that the voltage currently being supplied is above the detection level 5 Set the LVICNT LVIMD bit to 1 selecting the output of a reset signal Caution After the LVICNT LVIMD bit has been set to 1 further changes to the LVICNT register are not possible until the generation of a request for a different ...

Page 303: ...ied is above the detection level 6 In the interrupt controller clear the interrupt request flag for INTLVI 7 Also in the interrupt controller release masking of INTLVI 8 On generation of the interrupt INTLVI test the value of the LVISF LVISF bit to confirm the state of the power supply voltage Stopping LVI operation Set the LVICNT LVICNT bit to 0 Caution1 When an INTLVI is generated test the value...

Page 304: ...rs Table 8 10 List of POF LVI Registers Register Name Symbol Address Power on flag control registers Power on flag register POF FFFF FC00H Power on flag clear register POFC FFFF FC04H Power on flag set register POFS FFFF FC08H LVI control registers LVI status flag register LVISF FFFF FC10H LVI control register LVICNT FF45 0020H ...

Page 305: ...register can be written in 8 bit units When read the value returned is 00H Address FFFF FC04H Initial value 00H 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 POF R R R R R R R R Table 8 11 POF Register Contents Bit Position Bit Name Function 0 POF This bit indicates the state of detection for the power on flag 0 Voltage VDD is above the detection voltage 1 Voltage VDD is below the detection voltage a low voltage ...

Page 306: ...gister is set with the LVIMD and LVICNT bits set to 1 further changes to the setting are prohibited until the generation of a reset signal by various reset Access This register can be read written in 8 bit units Address FF45 0020H Initial value 00H This register is initialized by a reset generated by a source other than the LVI 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 POFS R R R R R R R W Table 8 13 POFS Reg...

Page 307: ...1 LVICNT0 These bits enables disables voltage detection by the LVI LVICNT1 LVICNT0 Function 0 0 Voltage detection by the LVI is disabled 0 1 Voltage detection by the LVI is enabled The detection voltage is 4 6 0 1 V 1 0 Voltage detection by the LVI is enabled The detection voltage is 4 3 0 1 V 1 1 Voltage detection by the LVI is enabled The detection voltage is 3 1 0 1 V 7 6 5 4 3 2 1 0 0 0 0 0 0 ...

Page 308: ...s in the form of access to undefined areas and access timeout 9 2 Memory Access Protection This product incorporates memory access protection functions CPU core protection Memory protection MPU Peripheral protection PPU 9 2 1 Memory Access Protection CPU core protection can be applied to memory areas and the address spaces specified in peripheral function registers Rights to access can be assigned...

Page 309: ...ted to the Peripheral I O Bus Table 9 1 List of Registers Related to the Peripheral I O Bus Register Name Symbol Address Peripheral I O bus PSELG control register APC FF45 4000H Peripheral I O bus PSELG error status register APES FF45 4004H Peripheral I O bus PSELG error status clear register APEC FF45 4008H Peripheral I O bus PSELG error address storage register APAM FF45 400CH Peripheral I O bus...

Page 310: ...0H This register is initialized by a reset from any source 7 6 5 4 3 2 1 0 0 0 0 0 0 UAA 0 ATO R R R R R R W R R W Table 9 2 APC Register Contents Bit Position Bit Name Function 2 UAA 0 Checking for access to undefined areas does not proceed 1 Checking for access to undefined areas proceeds Undefined area is the area which does not belong to the peripheral I O area 0 ATO 0 Checking for access time...

Page 311: ...y a reset from any source or by writing to the APEC register Caution Once any of the ATO and UAA bits in this register is set to 1 it remains so until it is cleared by writing to the APEC register or by a reset 7 6 5 4 3 2 1 0 0 0 0 0 0 UAA 0 ATO R R R R R R R R Table 9 3 Contents of the APES Register Bit Position Bit Name Function 2 UAA 0 An undefined area access error has not been generated 1 An...

Page 312: ...ned is 00H Address FF45 4008H Initial value 00H This register is initialized by a reset from any source 7 6 5 4 3 2 1 0 0 0 0 0 0 UAA 0 ATO R R R R R R W R R W Table 9 4 Contents of the APEC Register Bit Position Bit Name Function 2 UAA 0 The undefined area access error source flag in the APES register is not cleared 1 The undefined area access error source flag in the APES register is cleared 0 A...

Page 313: ...s initialized by a reset from any source Caution Since this register holds the address of the most recent error the stored address might not be that corresponding to the source which led to setting of an error status bit APES ATO and APES UAA to 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 1 1 1 1 1 1 1 A23 A22 A21 A20 A19 A18 A17 A16 R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 ...

Page 314: ...ror flag ATO in the APES register is also set to 1 Access This register can be read written in 8 bit units Address FF45 4010H Initial value 00H This register is initialized by a reset from any source 7 6 5 4 3 2 1 0 0 0 0 0 MATS3 MATS2 MATS1 MATS0 R R R R R W R W R W R W Table 9 6 MATS Register Contents Bit Position Bit Name Function 3 to 0 MATS 3 0 The available settings for maximum bus access ti...

Page 315: ... Status Register BSEQ0CTL is a majority circuit of BSEQ0CTLA C POF power on flag register RESF reset source flag register SGAMESSTR0 1 error source status registers 0 and 1 master SGACESSTR0 1 error source status registers 0 and 1 checker BSEQ0STRHBT self diagnostic BIST status register BRAMDAT3 0 backup RAM3 0 registers BSEQ0CTL self diagnostic BIST control register BSEQ0CTLA C self diagnostic BI...

Page 316: ...n of Self Diagnostic BIST The output on the TGLOUT pin is fixed to the low level once it is toggled to the low level after Self Diagnostic BIST is completed Check the TGLOUTOE TGLOUTSTS bit to see whether toggled output on the TGLOUT pin has stopped Follow the procedure below when changing the function of the TGLOUT pin to port mode after the CPU has started executing instructions After the CPU ha...

Page 317: ...serted after an LVI reset or CLM reset The value of FOP23 determines the function of the P8_0 TGLOUT pin When FOP23 0 and HWBISTEN is set for skipping of Self Diagnostic BIST the pin continues to operate as TGLOUT after release from the reset state In this case the setting of the TGLOUTOE register needs to be changed from TGLOUT mode to port control mode ...

Page 318: ...BIST control register A BSEQ0CTLA FF42 0044H Self Diagnostic BIST control register B BSEQ0CTLB FF42 0048H Self Diagnostic BIST control register C BSEQ0CTLC FF42 004CH BIST protection command register BSEQ0TCRPCMD FF83 B000H BIST protection status register BSEQ0TCRPESR FF83 B004H Self Diagnostic BIST status register BSEQ0STRHBT FF83 B008H Self Diagnostic BIST status clear trigger register BSEQ0STCH...

Page 319: ...s register is initialized by a reset from a source other than SWRES and BISTRES 7 6 5 4 3 2 1 0 0 0 TGLOUT STS TGLOUT LVL 0 0 0 TGLOUT OE0 R R R R R R R R W Table 9 10 Contents of the TGLOUTOE Register Bit Position Bit Name Function 5 TGLOUTSTS Shows the state of output from TGLOUT 0 Output on TGLOUT is stopped 1 The toggled signal is being output on TGLOUT 4 TGLOUTLVL Shows the level being output...

Page 320: ...les of the PLL input clock between consecutive rounds of writing to this register Example When heapclk is running at 80 MHz ensure an interval of at least 60 cycles of heapclk When the interval is shorter than this cycle the register will not reflect the second value For reading after writing ensure an interval of 3 cycles of the PLL input clock Example When heapclk is running at 80 MHz ensure an ...

Page 321: ...has been successful Also check that the setting of the register matched the result of Self Diagnostic BIST execution after release from the reset state When the setting of the BSEQ0CTL and a reset source are in contention the effectiveness of the setting of the BSEQ0CTL register is not guaranteed Caution After executing the instruction to write to this register the completion of actual writing tak...

Page 322: ...the majority decision can be checked by reading registers A B and C The registers are initialized when the power supply is turned on or the power supply voltage for the internal regulator VDD falls below the detection voltage indicated for the POF Access This register can be read written in 8 bit units Address BSEQ0CTLA FF42 0044H BSEQ0CTLB FF42 0048H BSEQ0CTLC FF42 004CH Initial value 01H Caution...

Page 323: ...m any source 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 W W W W W W W W W W W W W W W W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 W W W W W W W W W W W W W W W W Table 9 13 BSEQ0TCRPCMD Register Contents Bit Position Bit Name Function 31 to 0 Write enable command for the write protected BIST registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R ...

Page 324: ...are generated 30 MPE 0 Self diagnostic BIST code parity errors are not generated on the master side 1 Self diagnostic BIST code parity errors are generated on the master side 29 CPE 0 Self diagnostic BIST code parity errors are not generated on the checker side 1 Self diagnostic BIST code parity errors are generated on the checker side 15 to 8 HWBS 15 8 The state of self diagnostic BIST by the che...

Page 325: ...ST by the master s BIST sequencer 0 The sequence of self diagnostic BIST by the master ended abnormally did not end or has not started 1 The sequence of self diagnostic BIST by the master ended normally HWBS Bit Memory Logic Test Group 7 Memory Fixed to 0 6 This bit reflects the result of memory BIST execution 1 5 This bit reflects the result of memory BIST execution 1 4 This bit reflects the resu...

Page 326: ...CLHW BS13 CLHW BS12 0 CLHW BS10 CLHW BS9 CLHW BS8 0 CLHW BS6 CLHW BS5 CLHW BS4 0 CLHW BS2 CLHW BS1 CLHW BS0 W W W W W W W W W W W W W W W W Table 9 16 Contents of the BSEQ0STCHBT Register Bit Position Bit Name Function 31 CLHWBS31 This bit clears the HWBS31 bit in the BSEQ0STRHBT register 0 No effect setting this bit to 0 does not affect the BSEQ0STRHBT register 1 Bit HWBS31 is cleared 30 CLHWBS30...

Page 327: ...are undefined after self diagnostic BIST Since this register may hold values before the execution of self diagnostic BIST save the data beforehand This 128 bit register is composed of four registers Access This register can be read written in 32 bit units Address FF83 F030H BRAMDAT0 FF83 F034H BRAMDAT1 FF83 F038H BRAMDAT2 FF83 F03CH BRAMDAT3 Initial value Undefined 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 SG...

Page 328: ...e on chip RAM This register is initialized when the power supply is turned on or the power supply voltage for the internal regulator VDD falls below the detection voltage indicated for the POF Therefore if the LRAMSTBYCTL0 bit is set to 1 the state of the on chip RAM is retained after release from the reset state Change to normal mode before access to the on chip RAM This function does not support...

Page 329: ...Step 1 Write the designated value 000000A5H to the protection command register BSEQ0TCRPCMD Step 2 Write the desired setting to the target write protected register BSEQ0STCHBT Writing is invalid in this step Step 3 Write the inverse of the desired setting to the target write protected register BSEQ0STCHBT Writing is invalid in this step Step 4 Again write the desired setting to the target write pr...

Page 330: ...mbol Address Code flash ECC Code flash ECC error flag register CECCER FF43 2000H Code flash ECC error flag clear register CECCERC FF43 2004H Code flash ECC error correction address register CECADR FF43 2008H Code flash ECC error detection address register CEDADR FF43 200CH On chip RAM ECC On chip RAM ECC error flag register LECCER FF46 8000H On chip RAM ECC error flag clear register LECCERC FF46 8...

Page 331: ... Access This register can be read in 8 bit units Address FF43 2000H Initial value 00H This register is initialized by a reset from any source 7 6 5 4 3 2 1 0 0 0 0 0 0 0 CECCER0 EDFLG CECCER0 ECFLG R R R R R R R R Table 9 20 Contents of the CECCER Register Bit Position Bit Name Function 1 CECCER0EDFLG 0 ECC uncorrectable error is not generated 1 ECC uncorrectable error is generated 0 CECCER0ECFLG ...

Page 332: ...ed is always 00H Address FF43 2004H Initial value 00H This register is initialized by a reset from any source 7 6 5 4 3 2 1 0 0 0 0 0 0 0 CECCER 0EDCLR CECCER 0ECCLR R R R R R R R W R W Table 9 21 Contents of the CECCERC Register Bit Position Bit Name Function 1 CECCER0EDCLR This bit controls clearing of the code flash ECC error flag the CECCER CECCER0EDFLG bit 0 CECCER CECCER0EDFLG is not cleared...

Page 333: ...s register can be read in 32 bit units Address FF43 2008H Initial value 0000 0000H This register is initialized by clearing the CECCER CECCER0ECFLG bit or by a reset from any source 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 CECADR0A 21 16 R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CECADR0A 15 4 0 0 0 0 R R R R R R R R R R R R R R R R Table 9 22 ...

Page 334: ... register can be read in 32 bit units Address FF43 200CH Initial value 0000 0000H This register is initialized by clearing the CECCER CECCER0EDFLG bit or by a reset from any source 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 CEDADR0A 21 16 R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CEDADR0A 15 4 0 0 0 0 R R R R R R R R R R R R R R R R Table 9 23 C...

Page 335: ...its Address FF46 8000H Initial value 00H This register is initialized by a reset from any source 7 6 5 4 3 2 1 0 0 0 0 0 0 0 LECCER0 EDFLG LECCER0 ECFLG R R R R R R R R Table 9 24 Contents of the LECCER Register Bit Position Bit Name Function 1 LECCER0EDFLG 0 ECC uncorrectable error is not generated in the on chip RAM 1 ECC uncorrectable error is generated in the on chip RAM 0 LECCER0ECFLG 0 ECC c...

Page 336: ...urned is 00H Address FF46 8004H Initial value 00H This register is initialized by a reset from any source 7 6 5 4 3 2 1 0 0 0 0 0 0 0 LECCER0 EDCLR LECCER0 ECCLR R R R R R R R W R W Table 9 25 Contents of the LECCERC Register Bit Position Bit Name Function 1 LECCER0EDCLR This bit controls clearing of the on chip RAM ECC error flag the LECCER LECCER0EDFLG bit 0 LECCER LECCER0EDFLG is not cleared 1 ...

Page 337: ...ss This register can be read in 32 bit units Address FF46 8008H Initial value 0000 0000H This register is initialized by clearing the LECCER LECCER0ECFLG bit or by a reset from any source 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 LECADR0A 20 16 R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LECADR0A 15 2 0 0 R R R R R R R R R R R R R R R R Table 9...

Page 338: ...ister can be read in 32 bit units Address FF46 800CH Initial value 0000 0000H This register is initialized by clearing the LECCER LECCER0EDFLG bit or by a reset from any source 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 LEDADR0A 20 16 R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LEDADR0A 15 2 0 0 R R R R R R R R R R R R R R R R Table 9 27 Content...

Page 339: ...0H E6A0CTL Initial value Undefined This register is initialized by a reset from any source 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 E6A0 CTLE R2C 0 0 0 0 0 0 0 E6A0 CTLE CCER2 0 1 0 1 R R R R R R W R R R R R R R R R R Table 9 28 Contents of the E6A0CTL Register Bit Position Bit Na...

Page 340: ...0H E6A2CTL Initial value Undefined This register is initialized by a reset from any source 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 E6A2 CTLE R2C 0 0 0 0 0 0 0 E6A2 CTLE CCER2 0 1 0 1 R R R R R R W R R R R R R R R R R Table 9 29 Contents of the E6A2CTL Register Bit Position Bit Na...

Page 341: ...ialized 8 After the chip is restarted read the RESF register to check that an SGA reset SGARES is being generated 9 Clear the flag set to indicate the comparison unit error SGATERRIN5 in the error source status register of the SGA Procedure 2 1 After start up read the RESF register to check that a reset is not being generated by the SGA 2 In the INTCFGB register change INTCME compare interrupt fro...

Page 342: ...elow are undefined so reading them without initialization raises the possibility of a CPU comparison error Accordingly we recommend initializing all of these registers with any desired values When initializing the specified registers only according to the conditions evaluate them enough before using Caution In some cases these registers will be implicitly used by the C compiler etc so use the star...

Page 343: ...el exception 11 SCCFG Settings for SYSCAL operations 12 SCBP Base pointer for SYSCALL 16 CTPC This register preserves the state on execution of a CALLT instruction 20 CTBP Base pointer for CALLT 28 EIWR Working register for use with EI levels 29 FEWR Working register for use with FE levels CPU core protection group CPU core protection violations 1 VSTID Task identifier for system register protecti...

Page 344: ...T state violation task ID register H FFFF511AH VPNTIDHL Peripheral device protection NT state violation task ID register HL FFFF511BH VPNTIDHH Peripheral device protection NT state violation task ID register HH FFFF5120H VPTECR Peripheral device protection T state violation cause register FFFF5120H VPTECRL Peripheral device protection T state violation cause register L FFFF5120H VPTECRLL Periphera...

Page 345: ...nt value of timing supervision counter n register 2 FFFF5048H TSCCMP2 Comparison value of timing supervision counter n register 2 FFFF504CH TSCRLD2 Reload value of timing supervision counter n register 2 FFFF5054H TSCCNT3 Count value of timing supervision counter n register 3 FFFF5058H TSCCMP3 Comparison value of timing supervision counter n register 3 FFFF505CH TSCRLD3 Reload value of timing supe...

Page 346: ...SGACESET Meaning of xx in signal names Throughout this section the index xx xx 0 to 47 attached to the common part of the signal name collectively indicates SGATERRIN0 to SGATERRIN47 The individual values 0 to 47 identify the respective signals Register addresses All SGA register addresses are given as address offsets from the individual base addresses SGA_base SGAM_base or SGAC_base The addresses...

Page 347: ...ED SGATERRIN7 Flash memory ECC error detection and correction FLASH_EC SGATERRIN8 RAM ECC error detection IRAM_ED SGATERRIN9 RAM ECC error detection and correction IRAM_EC SGATERRIN10 Flash cache RAM ECC error detection FCACHE_RAM_ED2 SGATERRIN11 Flash cache RAM ECC error detection FCACHE_RAM_ED1 SGATERRIN12 Flash cache TAG ECC error detection FCACHE_TAG_ED2 SGATERRIN13 Flash cache TAG ECC error d...

Page 348: ...n is masked in accord with this signal This signal also indicates whether or not error generation is masked beyond BIST execution SG_HW_BIST_ERR_EN SGATERRIN 42 to SGATERRIN 47 Reserved Reserved SGATERRSWS This signal indicates the state of writing to SGAmESET SGA internal connection SGATERRLB Loop back signal from the signal on the ERROROUT pin i e this signal indicates the level on the ERROROUT ...

Page 349: ...ome of the redundant registers are accessed simultaneously by one write operation and some registers have to be accessed individually This allows an individual functional test by software of the two safety guardian instances SGA safety guardian register area represents the common register area where the redundant registers are accessed simultaneously by one write operation SGAM safety guardian mas...

Page 350: ...m shows the main components of the SGA Figure 10 2 Block Diagram of the Redundant SGA SGA checker SGA master ISG SGAM_base SGA_base DSG SGARES ISG SGAC_base SGA_base DSG SGATERROUTZ SGATI SGATERRINxx SGATTIN Peripheral bus Peripheral bus PCLK SGATERRINxx SGATTIN PCLK SGA SGATERRINxx SG_CMP_ERR SG_CMP_ERR SGATERRLB SGATERRLB ...

Page 351: ...e to indicate an error towards SGATERROUTZ even in case of clock faults The SGA has the following external connections Inputs Error inputs SGATERRINxx from all internal error sources and monitoring units The SGA master and SGA checker have identical error input signals The SGATTIN timer input connection is for generating dynamic error operation Error loop back SGATERRLB is used to read back the er...

Page 352: ... Error handling according to SGA configuration The following block diagram shows an example of the different phases of operation Figure 10 3 SGA Error States and Phases Reset Error Internal reset WDTA0RES CLMA0RES to CLMA2RES LVIRES SGARES Hardware error Error clear Error clear Application Error set E r r o r s e t SGATERROUTZ 0 ERROROUT Hi Z Reset by the RESET signal Start up test SGATERROUTZ 0 E...

Page 353: ...ror output SGATERROUZ Internal reset configuration registers Each individual error input SGATERRINxx can be configured to generate an internal reset or not Interrupt configuration register Interrupt generation by SGATI can be configured for some error inputs SGATERRIN41 to SGATERRIN32 Pseudo error registers This function allows functional tests of the error path by pseudo error injection Error pul...

Page 354: ...Trigger Register 4 Set the SGAEPCFG SGASL0 bit to 1 for dynamic mode 5 Start the timer Note Set the timer cycle according to the characteristics of the external device to be connected 2 Dynamic Mode Disable 1 Set the SGAEMK0 and SGAEMK1 registers 2 Drive the error output to low level by setting the SGAmESET SGAmEST bit to 1 Refer to the note in Section 10 4 2 1 SGAmESET SGAm Error Set Trigger Regi...

Page 355: ... Mask SG_CMP_ERR by setting the SGAEMK1 SGAEMK108 bit 5 Set error output to high level by the SGAMECLR and SGACECLR registers 6 Read the SGAMESSTR1 SGAMSSE131 and SGACESSTR1 SGACSSE131 bits and check for 1 7 Set error output to low level by the SGAMESET register 8 Read the SGAMESSTR1 SGAMSSE131 and SGACESSTR1 SGACSSE131 bits and check for 0 9 Clear the error by the SGAESSTC1 SGACLSSE130 bit 10 Set...

Page 356: ...upt or internal reset apply in the same way The pseudo error generation can be used for debug purposes to generate errors and check for instance the operation of the software for SGA interrupts SGATI Internal reset SGARES error output SGATERROUTZ for test purposes after reset to perform a functional test of the error source status registers SGAMESSTR0 and SGAMESSTR1 This test can be combined with ...

Page 357: ...SGAmESSTR0 and SGAmESSTR1 registers The error status is only cleared after external reset by RESET In case of an internal reset the status is kept and the error source can be evaluated afterwards by reading the SGAmESSTR0 and SGAmESSTR1 registers Additionally these registers are excluded from the self diagnostic BIST in order to not destroy their content ...

Page 358: ...echanism behaves as follows If the second register belongs to the SGA the write to the protected register fails indicated by SGAPS SGAPRERR 1 The entire sequence has to be restarted at step 1 If the second register does not belong to the SGA the protection unlock sequence is not disrupted and the write to the first register can be completed successfully Note For sequences of SGAPCMD1 and SGAmPCMD0...

Page 359: ... error source status register 0 SGACESSTR0 Disabled SGAC_base 8H SGA checker error source status register 1 SGACESSTR1 Disabled SGAC_base CH SGA checker protection command register SGACPCMD0 Not applicable SGAC_base 10H Table 10 10 Overview of SGA Registers Register Name Symbol Write Protected by Special Sequence Address SGA error pulse configuration register SGAEPCFG Enabled SGA_base SGA interrup...

Page 360: ... SGATI interrupts by setting the SGAICFG1 SGAIE108 bit to prohibited 3 Prevent generation of the SGARES reset by setting the SGAIRCFG1 SGAIRE108 bit to prohibited 4 Set the error output bit in the SGAmESET register 5 Clear error flags by setting the SGAESSTC1 SGACLSSE108 and SGAESSTC1 SGACLSSE130 bits 6 Make the following settings in accord with the condition of usage for the SGATERRIN40 error If ...

Page 361: ...he SGARES reset by setting the SGAIRCFG1 SGAIRE108 bit to prohibited 4 Clear the error output bit in the SGAmECLR register 5 Clear error flags by setting the SGAESSTC1 SGACLSSE108 bit 6 Make the following settings in accord with the condition of usage for the SGATERRIN40 error If an SGATERROUTZ error is being output set the SGAEMK1 SGAEMK108 bit to not masked If an SGATI interrupt is being generat...

Page 362: ...ating detection of an ECC error in flash memory including when the error has been corrected For reliable detection of ECC errors set the SGAIRCFG0 SGAIRE006 and SGAIRCFG0 SGAIRE007 bits to suppress internal resetting by the SGA i e setting the bits to 0 and test the error source flags in register CECCER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 SGAm SSE 019 SGAm SSE 0...

Page 363: ...r these bits to 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SGAm SSE 131 SGAm SSE 130 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 SGAm SSE 109 SGAm SSE 108 SGAm SSE 107 SGAm SSE 106 SGAm SSE 105 SGAm SSE 104 SGAm SSE 103 SGAm SSE 102 SGAm SSE 101 SGAm SSE 100 R R R R R R R R R R R R R R R R Table 10 14 SGAmESSTR1 Register Cont...

Page 364: ...Writing to Protected Registers The status of the protected write sequence is indicated in the description in 15 SGAPS SGA Protection Status Register Access This register can be written in 32 bit units Address SGAm_base 10H Initial value Undefined Table 10 15 SGAPmCMD0 Register Contents 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W W W W W W W W W W W W W W W W 1...

Page 365: ...tting the dynamic mode it is recommended not to change to non dynamic mode again because there is a possibility of a glitch at the error output For details see Section 10 3 3 Operations for Error Output 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SGAS L0 R R R R R...

Page 366: ...tialized by a reset from any source 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 SGAI E109 SGA IE108 SGA IE107 SGA IE106 SGA IE105 SGA IE104 SGA IE103 SGA IE102 SGA IE101 SGA IE100 R R R R R R R W R W R W R W R W R W R W R W R W R W Table 10 17 SGAICFG1 Register Contents Bit positio...

Page 367: ...SGAIRE006 and SGAIRCFG0 SGAIRE007 bits to suppress internal resetting by the SGA i e setting the bits to 0 and test the error source flags in register CECCER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 SGA IRE 019 SGA IRE 018 0 SGA IRE 016 R R R R R R R R R R R R R W R W R R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SGA IRE 015 SGA IRE 014 SGA IRE 013 SGA IRE 012 SGA IRE ...

Page 368: ...9 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 SGA IRE 109 SGA IRE 108 SGA IRE 107 SGA IRE 106 SGA IRE 105 SGA IRE 104 SGA IRE 103 SGA IRE 102 SGA IRE 101 SGA IRE 100 R R R R R R R W R W R W R W R W R W R W R W R W R W Table 10 19 SGAIRCFG1 Register Contents Bit position Bit Name Function 9 ...

Page 369: ...6 R R R R R R R R R R R R R W R W R R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SGA EMK 015 SGA EMK 014 SGA EMK 013 SGA EMK 012 SGA EMK 011 SGA EMK 010 SGA EMK 009 SGA EMK 008 SGA EMK 007 SGA EMK 006 SGA EMK 005 SGA EMK 004 SGA EMK 003 SGA EMK 002 SGA EMK 001 SGA EMK 000 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Table 10 20 SGAEMK0 Register Contents Bit position Bit Name Functi...

Page 370: ...25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 SGA EMK 109 SGA EMK 108 SGA EMK 107 SGA EMK 106 SGA EMK 105 SGA EMK 104 SGA EMK 103 SGA EMK 102 SGA EMK 101 SGA EMK 100 R R R R R R R W R W R W R W R W R W R W R W R W R W Table 10 21 SGAEMK1 Register Contents Bit position Bit Name Function 9 to 0 SGAEMK10...

Page 371: ...8 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 SGA CLSSE 019 SGA CLSSE 018 0 SGA CLSSE 016 W W W W W W W W W W W W W W W W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SGA CLSSE 015 SGA CLSSE 014 SGA CLSSE 013 SGA CLSSE 012 SGA CLSSE 011 SGA CLSSE 010 SGA CLSSE 009 SGA CLSSE 008 SGA CLSSE 007 SGA CLSSE 006 SGA CLSSE 005 SGA CLSSE 004 SGA CLSSE 003 SGA CLSSE 002 SGA CLSSE 001 SGA CLSSE 000 ...

Page 372: ...23 22 21 20 19 18 17 16 0 SGA CLSSE 130 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W W W W W W W W W W W W W W W W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 SGA CLSSE 109 SGA CLSSE 108 SGA CLSSE 107 SGA CLSSE 106 SGA CLSSE 105 SGA CLSSE 104 SGA CLSSE 103 SGA CLSSE 102 SGA CLSSE 101 SGA CLSSE 100 W W W W W W W W W W W W W W W W Table 10 23 SGAmESSTC1 Register Contents Bit position Bit Name Function 30 SGA...

Page 373: ...te protection sequence refer to Section 10 3 7 Writing to Protected Registers Access This register can be written in 32 bit units Address SGA_base 20H Initial value Undefined Table 10 24 SGAPCMD1 Register Contents 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W W W W W W W W W W W W W W W W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 SGA1REG 7 0 W W W W ...

Page 374: ...2 bit units Address SGA_base 24H Initial value 0000 0000H This register is initialized by a reset from any source Table 10 25 SGAPS Register Contents 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SGA PRE RR R R R R R R R R R R R R R R R R Bit position Bit Name Funct...

Page 375: ...N18 SGATERRIN19 and SGATERRIN36 cannot be generated simultaneously with other pseudo errors 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 SGA PE 019 SGA PE 018 0 SGA PE 016 W W W W W W W W W W W W W W W W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SGA PE 015 SGA PE 014 SGA PE 013 SGA PE 012 SGA PE 011 SGA PE 010 SGA PE 009 SGA PE 008 SGA PE 007 SGA PE 006 SGA PE 005 SGA PE 004...

Page 376: ...is register is initialized by a reset from any source Caution SGATERRIN18 SGATERRIN19 and SGATERRIN36 cannot be generated simultaneously with other pseudo errors 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W W W W W W W W W W W W W W W W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 SGA PE 109 SGA PE 108 SGA PE 107 SGA PE 106 SGA PE 105 SGA PE 104 SGA PE 103...

Page 377: ...in dynamic mode Access This register can be read written in 8 bit units Address FF83 F020H Initial value 00H This register is initialized by a reset from any source 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 SGATMSL R R R R R R R R W Table 10 28 SGAEPCTL Register Contents Bit position Bit Name Function 0 SGATMSL This bit selects the timer for the output of error signals while the SGA is in dynamic mode 0 TAUB0...

Page 378: ...DCRAnCTL for the DCRAn control register Register addresses All DCRAn register addresses are given as address offsets to the individual base address DCRAn_base0 or DCRAn_base1 The base addresses DCRAn_base0 and DCRAn_base1 of each DCRAn are listed in the following table Clock supply All data CRC function A provide one clock input Table 11 1 Instances of DCRA Data CRC Function A Instance 2 Name DCRA...

Page 379: ... X5 1 XOR of the result for the generated CRC code and 0000H CRC generation to an arbitrary data block length After initialization of the CRC input register every write access to the CRC input register generates a new CRC according to the chosen polynomial and the result is stored in the CRC data register Calculation result DCRAnCOUT Shift register Input data DCRAnCIN for 8 bit effective bit width...

Page 380: ...a CRC Function A DCRA The following figure shows the block diagram of the data CRC function A Figure 11 1 Block Diagram of Data CRC Function A PBUS PBUS DCRAnCOUT Selector DCRAnCTL DCRAnPOL DCRAnCIN 8 16 32 bits 32 bit Ethernet CRC code generator 16 bit CCITT CRC code generator EXOR ...

Page 381: ...ernet or 16 bit CCITT The initial starting value must be set at the DCRAnCOUT register before the first write access to the CRC input register DCRAnCIN is performed The flow chart below shows the CRC generating procedure Figure 11 2 Data CRC Function A Flow Diagram Note For the settings of the individual registers and points for caution regarding the settings see Section 11 4 2 DCRA Registers Deta...

Page 382: ...ription of all registers of the DCRA 11 4 1 DCRA Registers Overview The DCRA is controlled and operated by the following registers Table 11 4 DCRA Registers Overview Register Name Symbol Address DATA DCRA input register n DCRAnCIN DCRAn_base0 00H DATA DCRA data register n DCRAnCOUT DCRAn_base0 04H DCRA control register n DCRAnCTL DCRAn_base1 20H ...

Page 383: ...POL 0 The byte order is LSB least significant byte first means LSB at bit position 7 0 of the DCRAnCIN register 16 bit CCITT CRC polynomial generation DCRAnCTL DCRAnPOL 1 The byte order is MSB most significant byte first means MSB at bit position 7 0 of the DCRAnCIN register Access This register can be read written in 32 bit units Address DCRAn_base0 00H Initial value 0000 0000H This register is i...

Page 384: ...DCRAnCOUT 31 16 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DCRAnCOUT 15 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Table 11 6 DCRAnCOUT Register Contents Bit Position Bit Name Function 31 to 0 DCRAnCOUT 31 0 Result of the CRC code generation When the 16 bit CCITT polynomial is enabled bits 15 to 0 show the CRC result...

Page 385: ... final CRC result is read from the DCRAnCOUT register the bit width can be changed In that case the register should be set again according to Figure 11 2 Data CRC Function A Flow Diagram 7 6 5 4 3 2 1 0 0 0 0 0 0 DCRAnISZ 1 0 DCRAn POL R W R W R W R W R W R W R W R W Table 11 7 DCRAnCTL Register Contents Bit Position Bit Name Function 2 1 DCRAnISZ 1 0 Specifies the CRC input bit width 00 32 bits D...

Page 386: ...or example WDTAnWDTE for the WDTAn enable register Register addresses All WDTAn register addresses are given as address offsets from the individual base address WDTAn_base The register base address of each WDTAn is listed in the following table Clock supply The window watchdog timer A provides WDTATCKI as the clock input WDTATCKI is connected to the clock controller Table 12 1 Instances of WDTA Wi...

Page 387: ...tection Generation of reset WDTAnTRES on error detection Interrupt request generation at 75 of the counter overflow value Window function The following figure shows the main components of the WDTA Figure 12 1 Block Diagram of the WDTA Table 12 4 WDTA Interrupts and Reset Outputs WDTAn Signal Function Connected to WDTA0TRES WDTA0 error reset Reset controller WDTA0RES Safety guardian SGATERRIN3 WDTA...

Page 388: ...ls 12 3 1 WDTA after Reset Release The counter value remains 0000H after reset release The counter is started with the first WDTA trigger 1 WDTA Settings after Reset Release The WDTA settings are as follows after reset release Change WDTA settings After the first trigger the WDTA continues according to the settings of the watchdog timer mode register WDTAnMD To change the WDTA settings WDTAnMD mus...

Page 389: ...iately 3 The counter starts at the first trigger The overflow value and other settings specified in WDTAnMD are applied 12 3 2 WDTA Trigger The WDTA trigger has the following functions Starting the WDTA by the first trigger after release from reset i e the first software trigger to start counting Counter re start trigger to keep the counter from overflowing The WDTA can be triggered by writing a f...

Page 390: ...the trigger register outside the open window Illegal update of the watchdog timer mode register WDTAnMD Writing a new value to WDTAnMD after the first trigger leads to an error detection Writing the same value to WDTAnMD after the first trigger does not lead to an error detection Error mode When an error is detected either an NMI request WDTAnTNMI or a reset WDTAnTRES is generated WDTAnMD WDTAnERM...

Page 391: ... written before the first trigger is generated However the settings are not applied immediately 3 The counter starts at the first trigger The overflow value and other settings specified in WDTAnMD are applied 4 When the counter overflows an error is detected Depending on the error mode either interrupt request WDTAnTNMI or reset WDTAnTRES is generated The counter value remains until the system res...

Page 392: ...generated The WDTAnMD WDTAnWIE register enables disables this function The following figure shows the 75 interrupt request generation with the following conditions Count clock changes after the first trigger Figure 12 4 Timing Diagram of WDTA 75 Interrupt Output FFFFH WDTAnTIT Counter value WDTAnTRES or WDTAnTNMI Reset release First trigger Error detection Trigger 75 of the overflow value WDTAnMD ...

Page 393: ... WDTA Window Function The timing diagram above shows the following 1 The operating mode settings in WDTAnMD should be made before the first trigger is generated However the settings are not applied immediately 2 The window open period is fixed to 100 for the first trigger After the first trigger the overflow value and other settings specified in WDTAnMD are applied 3 A trigger that occurs in the w...

Page 394: ...ters This section contains a description of all registers of the WDTA 12 4 1 WDTA Registers Overview The WDTA is controlled and operated by the following registers Table 12 6 WDTA Register Overview Register Name Symbol Address WDTA enable register WDTAnWDTE WDTAn_base 0000H WDTA mode register WDTAnMD WDTAn_base 000CH ...

Page 395: ...for details Do not write a value other than ACH Otherwise an error is detected Access This register can be read written in 8 bit units Address WDTAn_base 0000H Initial value 2CH This register is initialized by any reset sources 7 6 5 4 3 2 1 0 WDTAn RUN 0 1 0 1 1 0 0 R W R W R W R W R W R W R W R W Table 12 7 WDTAnWDTE Register Contents Bit Position Bit Name Function 7 WDTAnRUN Enables disables th...

Page 396: ...DTAn_base 000CH Initial value 7FH This register is initialized by any reset sources 7 6 5 4 3 2 1 0 0 WDTAnOVF 2 0 WDTAnWIE WDTAnERM WDTAnWS 1 0 R R W R W R W R W R W R W R W Writing to this bit is ignored reading returns 0 Table 12 8 WDTAnMD Register Contents Bit Position Bit Name Function 6 to 4 WDTAnOVF 2 0 Selects the overflow time WDTAnOVF 2 WDTAnOVF 1 WDTAnOVF 0 Overflow Time 0 0 0 2 048 ms ...

Page 397: ...gister TAUBnTOM Channels index m TAUB has 16 channels Throughout this section each channel is dentified by m m 0 to 15 Thus a certain channel is denoted as CHm The even numbered channels m 0 2 4 6 8 10 12 14 are denoted as CHm_even The odd numbered channels m 1 3 5 7 9 11 13 15 are denoted as CHm_odd Register addresses All TAUBn register addresses are given as address offsets to the individual bas...

Page 398: ...5 interrupt Interrupt controller INTTAUB0I5 DMA controller trigger 32 INTTAUB0I6 Channel6 interrupt Interrupt controller INTTAUB0I6 DMA controller trigger 33 INTTAUB0I7 Channel7 interrupt Interrupt controller INTTAUB0I7 DMA controller trigger 34 INTTAUB0I8 Channel8 interrupt Interrupt controller INTTAUB0I8 DMA controller trigger 35 INTTAUB0I9 Channel9 interrupt Interrupt controller INTTAUB0I9 DMA ...

Page 399: ...TIN0 TAUBnTTIN1 TAUBnTTIN2 TAUBnTTIN3 TAUBnTTIN4 TAUBnTTIN5 TAUBnTTIN6 TAUBnTTIN7 TAUBnTTIN8 TAUBnTTIN9 TAUBnTTIN10 TAUBnTTIN11 TAUBnTTIN12 TAUBnTTIN13 TAUBnTTIN14 TAUBnTTIN15 Prescaler Channel 0 Channel 2 Channel 1 Channel 3 Channel 4 Channel 6 Channel 5 Channel 7 Channel 8 Channel 10 Channel 9 Channel 11 Channel 12 Channel 14 Channel 13 Channel 15 TAUBnTTOUT8 TAUBnTTOUT0 INTTAUBnI0 TAUBnTTOUT1 I...

Page 400: ... fx 2 to fx 215 Prescaler Block PCLK Selector Selector Selector Selector PRS03 00 PRS13 10 PRS23 20 PRS33 30 CK0 CK1 CK2 CK3 Simultaneous Rewrite Trigger from Upper Start Trigger from Master INT from Master INT from Upper Clock Selector CKENm Edge Detector TINm SSTm Count Clock Selector Trigger Selector sel sel UpDown Signal from Master sel CMORm STS2 0 CMORm CCS1 0 CMORm CKS1 0 CMURm TIS1 0 CMORm...

Page 401: ...peration and features of a channel In synchronous channel operation every channel in a channel group can operate in a different operating mode Examples are capture mode event count mode and interval timer mode Channel output mode The channel output mode defines the operation of TAUBnTTOUTm of a single channel independent output operation or of all channels in a channel group synchronous output ope...

Page 402: ...r a slave A master channel can have multiple slaves and the state of one channel affects that of the other channels For example one channel can be used to control the count start timing or reset timing of others The following describes the functional blocks Prescaler block The prescaler block provides up to 4 clock signals CK0 to CK3 that can be used as count clocks for all channels Plescaler outp...

Page 403: ...n output trigger signal of master channel Dead time output signal of TAUBnTTOUTm generation unit Simultaneous rewrite controller Simultaneous rewrite control is a special function that can be used in synchronous operating modes The data registers TAUBnCDRm of all channels in a channel group can be rewritten at any time The simultaneous rewrite controller ensures that new data register values of al...

Page 404: ...r output function type1 Independent channel signal measurement functions Synchronous PWM signal functions triggered by an external signal TAUBnTTINm input pulse interval measurement function One shot pulse output function TAUBnTTINm input signal width measurement function Synchronous triangle PWM output functions TAUBnTTINm input period count detection function Triangle PWM output function TAUBnTT...

Page 405: ...CK0 to CK3 2 Configure the desired TAUBn function Set the operating mode Set the channel output mode Set any other control bits 3 Enable the counter by setting the TAUBnTS TAUBnTSm bit to 1 The counter starts to count immediately or when an appropriate trigger is detected according to bit settings 4 If desired during counting and if possible for the configured function stop the counter or perform ...

Page 406: ...ins 12 operating modes One operating mode can be set for each channel which is specified using the TAUBnCMORm TAUBnMD 4 0 bits Note Some of the registers and bits are fixed and some are user selectable depending on the operation function For details on the registers and bit settings see the corresponding sections of operational functions ...

Page 407: ...ous Rewrite 13 6 1 Rules Number of masters and slaves Only even channels CH0 CH2 CH4 can be set as master channels Any channel apart from CH0 can be set as a slave channel Only channels lower than the master channel can be set as slave channels and several slave channels can be set for one master channel Example If CH2 is a master channel channels CH3 CH4 CH5 following CH3 can be set as slave chan...

Page 408: ...by CK0 Channel group 2 operated by CK0 The operation clock can be set separately for each channel group Channel group 3 operated by CK3 A channel that operates independently can also be set between the master and slave channels of channel group 3 Its counter clock can be set independently of that of the channel group CH0 Master CH1 Slave CH2 Slave CH4 Master CH5 Slave CK0 CK0 TAUBn CH8 Master CH10...

Page 409: ... synchronized channels the TAUBnTS TAUBnTSm bits of the channels should be set at the same time To simultaneously stop synchronized channels the TAUBnTT TAUBnTTm bits of the channels should be set at the same time Setting to the TAUBnTS TAUBnTSm bits to 1 also sets the corresponding TAUBnTE TAUBnTEm bits to 1 enabling counting The count start timing depends on operating mode 2 Simultaneous start b...

Page 410: ...channel specified by TAUBnRDC TAUBnRDCm There are three methods for simultaneous rewrite These are listed in the following table along with how to specify them and when they cause simultaneous rewrite to be triggered The following table lists which of these three methods is available for each channel operation function For details on the individual channel operation functions see Section 13 12 Ind...

Page 411: ...ewrite and Trigger Timing Function A B C1 Simultaneous rewrite trigger generating function type 1 X PWM output function X X One shot pulse output function X Delay pulse output function X Triangle PWM output function X X Triangle PWM output function with dead time X X AD conversion trigger output function type 1 X X AD conversion trigger output function type 2 X X ...

Page 412: ...imultaneous Rewrite TAUBnRDE RDEm TAUBnRDM RDMm TAUBnRSF RSFm 1 Carry out simultaneous rewrite Update TAUBnCDRm TAUBnTOL TOLm buffers TAUBnCDRm TAUBnTOL TOLm TAUBnRSF RSFm 0 Sets TAUBnRSF RSFm 1 TAUBnRDT RDTm 1 TAUBnTS TSm Update TAUBnCDRm TAUBnTOL TOLm buffers Counter operates using TAUBnCDRm buffer and TAUBnTOL TOLm buffer values awaits simultaneous rewrite trigger based on initial settings On t...

Page 413: ...BnTOLm buf and data buffer registers TAUBnCDRm buf and the counters start Setting the reload data trigger bit TAUBnRDT TAUBnRDTm to 1 sets the reload flag TAUBnRSF TAUBnRSFm to 1 enabling simultaneous rewrite TAUBnRSF TAUBnRSFm remains set to 1 until simultaneous rewrite is completed When the specified trigger for simultaneous rewrite is detected the TAUBnRSF TAUBnRSFm bit is checked to see if sim...

Page 414: ...e any other function is used TAUBnTTOUTm outputs an invalid wave When an upper channel is used as a channel issuing the simultaneous rewrite trigger TAUBnRDS TAUBnRDSm 1 the TAUBnRDC TAUBnRDCm bit controls all the lower channels This means that if the TAUBnRDC TAUBnRDCm bits of CH2 and CH7 are set to 1 and the TAUBnRDC TAUBnRDCm bits of other channels are set to 0 CH2 and CH7 serve as simultaneous...

Page 415: ...ethod A Figure 13 5 Simultaneous Rewrite When the Master Channel Starts Restarts Counting Setting CH0 is the master channel which starts counting down and CH1 represents an arbitrary slave channel The simultaneous rewrite method A is applied TAUBnTS TAUBnTSm TAUBnTE TAUBnTEm TAUBnCNT0 INTTAUBnI0 TAUBnCNT1 INTTAUBnI1 TAUBnTTOUT1 TAUBnTOL TAUBnTOL1 TAUBnTOL TAUBnTOL1 buf TAUBnCDR0 TAUBnCDR0 buf TAUB...

Page 416: ... but simultaneous rewrite does not occur because it is disabled TAUBnRSF TAUBnRSFm 0 4 The reload data trigger bit TAUBnRDT TAUBnRDTm is set to 1 which sets the status flag TAUBnRSF TAUBnRSFm 1 enabling simultaneous rewrite 5 Because simultaneous rewrite is enabled it is triggered when CH0 restarts counting The TAUBnCDRm value is loaded into the TAUBnCDRm buffer and the TAUBnTOL TAUBnTOLm value is...

Page 417: ...of Master Channel Setting CH0 is the master channel which performs counting up and down and CH1 represents an arbitrary slave channel The simultaneous rewrite method B is applied TAUBnTS TAUBnTSm TAUBnTE TAUBnTEm TAUBnCNT0 INTTAUBnI0 TAUBnCNT1 INTTAUBnI1 TAUBnTTOUT1 TAUBnTOL TAUBnTOL1 TAUBnTOL TAUBnTOL1 buf TAUBnCDR0 TAUBnCDR0 buf TAUBnCDR1 TAUBnCDR1 buf TAUBnRDT TAUBnRDTm TAUBnRSF TAUBnRSFm 1 3 4...

Page 418: ...e reload data trigger bit TAUBnRDT TAUBnRDTm is set to 1 which sets the status flag TAUBnRSF TAUBnRSFm 1 enabling simultaneous rewrite 5 Simultaneous rewrite does not take place at the bottom of the triangular cycle 6 Simultaneous rewrite takes place at the top of the triangular cycle The TAUBnCDRm value is loaded into the TAUBnCDRm buffer the TAUBnTOL TAUBnTOLm value is loaded into the TAUBnTOL T...

Page 419: ...C TAUBnRDCm Setting CH1 is an upper channel used counting down CH2 is a master channel and CH3 is the slave channel The simultaneous rewrite method C1 is applied The TAUBnRDC register specifies a channel which generates simultaneous rewrite triggers TAUBnTS TAUBnTSm TAUBnTE TAUBnTEm TAUBnCNT1 INTTAUBnI1 TAUBnCNT2 INTTAUBnI2 TAUBnCDR1 TAUBnCDR1 buf TAUBnCDR2 TAUBnCDR2 buf TAUBnCDR3 TAUBnCDR3 buf TA...

Page 420: ...DTm to 1 the status flag is set TAUBnRSF TAUBnRSFm 1 to enable simultaneous rewrite 4 Simultaneous rewrite is triggered only by a CH1 interrupt Therefore simultaneous rewrite is not conducted even if enabled 5 Simultaneous rewrite is triggered by INTTAUBnI1 which is generated when TAUBnCNT1 reaches 0000H The TAUBnCDRm values are loaded into the corresponding TAUBnCDRm buffers 6 The counter counts ...

Page 421: ...an always be read to determine the current value of TAUBnTTOUTm regardless of whether the pin is controlled by software operated independently or operated synchronously Control bits The settings of the control bits required to select a specific channel output mode are listed in Table 13 10 Channel Output Modes The channel output modes are described in details below Section 13 8 2 Channel Output Mo...

Page 422: ...ing count operation TAUBnTE TAUBnTEm 1 TAUBnTOE TAUBnTOEm TAUBnTOM TAUBnTOMm TAUBnTOC TAUBnTOCm TAUBnTDE TAUBnTDEm Table 13 10 Channel Output Modes Channel Output Modes TAUBn TOE TAUBn TOEm TAUBn TOM TAUBn TOMm TAUBn TOC TAUBn TOCm TAUBn TDE TAUBn TDEm By software Independent channel output mode controlled by software 0 X By TAUB signals independently Independent channel output mode 1 1 0 0 0 Inde...

Page 423: ...ounter is enabled Figure 13 9 General Change of the TAUBnTTOUTm Output TAUBnTO TAUBnTOm sets the initial value of TAUBnTTOUTm and can be changed while TAUBnTOE TAUBnTOEm 0 TAUBnTOL TAUBnTOLm specifies whether the set signal sets TAUBnTO TAUBnTOm to high TAUBnTOL TAUBnTOLm 0 or low inverted logic TAUBnTOL TAUBnTOLm 1 Hi Z TAUBnTTOUTm TAUBnTO TAUBnTOm 1 Set TAUBnTO TOm value Product pin 2 Set operat...

Page 424: ... Output Modes 1 Independent channel output mode 1 Set reset conditions In this output mode TAUBnTTOUTm toggles when INTTAUBnIm is detected The value of TAUBnTOL TAUBnTOLm is ignored Prerequisites None other than those in Table 13 10 Channel Output Modes 2 Independent channel output mode 2 Set reset conditions In this output mode TAUBnTTOUTm is set when INTTAUBnIm occurs upon count start and reset ...

Page 425: ...of the slave channel are generated at the same time INTTAUBnIm of the slave channel reset signal has priority over INTTAUBnIm set signal of master channel i e the master channel is ignored Prerequisites None other than those in Table 13 10 Channel Output Modes 2 Synchronous channel output mode 2 In this output mode the operating mode should be set to up down count mode The result is a triangle PWM...

Page 426: ...es Prerequisites Dead time control requires a set of three channels each operating in the following modes One master channel The master channel should be set to interval timer mode One even slave channel The even slave channel should be set up down count mode One odd slave channel even channel 1 The odd slave channel should be set to one count mode The values of the following bits should be the sa...

Page 427: ...this section is for your reference Actually the count start timing depends on the count clock timing 13 9 1 Interval Timer Mode Judge Mode Capture Mode and Up Down Count Mode The counter starts operating with the next count clock after TAUBnTS TAUBnTSm is set to 1 The value of data register is also loaded when the counter starts Figure 13 11 Start Timing in Interval Timer Mode Judge Mode Capture M...

Page 428: ...ming is triggered only upon detection of a valid edge of TAUBnTTINm Once the counter starts the value of data register TAUBnCDRm register is also loaded The count clock cycles which is irrelevant to start of counter operation determine the frequency with which all operations take place Figure 13 13 Start Timing in Other Operating Modes TAUBnCDRm value TAUBnCDRm value 1 Initial value TAUBnCNTm PCLK...

Page 429: ...ing count operation TAUBnTE TAUBnTEm 1 Refer to Table 13 126 Description of TAUBnCMORm Register for the role of the TAUBnMD0 bit as well Figure 13 14 INTTAUBnIm Generated When Counter Starts Table 13 11 Effect of CMOR TAUBnMD0 Bit on Generation of INTTAUBnIm when Counter Is Triggered Mode TAUBnCMOR MD0 Bit INTTAUBnIm Generated when Counter Is Started Restarted or Triggered by TINm Input Signal Int...

Page 430: ...2 PG4 L Section 13 Timer Array Unit B TAUB Figure 13 15 INTTAUBnIm Not Generated When Counter Starts Count operation start TAUBnCNTm TAUBnTE TAUBnTEm INTTAUBnIm TAUBnTTOUTm When TAUBnCMORm TAUBnMD0 is set to 0 INTTAUBnIm is not generated when the counter starts ...

Page 431: ...tection takes place Figure 13 16 Basic Edge Detection Timing Caution Figure 13 6 Basic Edge Detection Timing shows an operation timing image Actually a noise filter or synchronization circuit which is located between the TAUBnlm pin and TAUBn causes a delay time When using a noise filter Noise filter delay time edge detection delay time maximum one sampling clock When not using a noise filter Sync...

Page 432: ...nctions provided by the TAUB For a general overview of independent channel operation see Section 13 3 Functional Description 13 13 Independent Channel Interrupt Functions This section describes functions that generate interrupts at regular intervals or with a specified delay Section 13 13 1 Interval Timer Function Section 13 13 2 TAUBnTTINm Input Interval Timer Function Section 13 13 3 One Pulse O...

Page 433: ...nIm is generated and the TAUBnTTOUTm signal toggles The TAUBnCDRm value is loaded in TAUBnCNTm and subsequently operation continues The value of TAUBnCDRm can be rewritten at any time and the changed value of TAUBnCDRm is applied the next time the counter starts to count down The counter can be stopped by setting TAUBnTT TAUBnTTm to 1 This sets TAUBnTE TAUBnTEm to 0 TAUBnCNTm and TAUBnTTOUTm stop ...

Page 434: ...3 18 General Timing Diagram of Interval Timer Function TAUBnCNTm TAUBnTO TAUBnTOm TAUBnTRO TAUBnTROm TAUBnCDRm INT Trigger from upper channel Trigger from upper channel Start trigger from master Simultaneous rewrite INT from master INT from upper channe Clock selector Count clock edge selector Trigger selector Trigger from lower channel Start and capture trigger Interval timer mode TAUBnTS TAUBnTS...

Page 435: ...1 Operation clock CK1 10 Operation clock CK2 11 Operation clock CK3 TAUBnCCS 1 0 00 Uses an operation clock as a count clock TAUBnMAS 0 Unused Set to 0 TAUBnSTS 2 0 000 Triggers the counter by software TAUBnCOS 1 0 00 Unused Set to 00 TAUBnMD 4 1 0000 Interval timer mode TAUBnMD0 0 INTTAUBnIm is not generated to toggle TAUBnTTOUTm at the beginning of an operation 1 INTTAUBnIm is generated to toggl...

Page 436: ...re these registers should be set to 0 Table 13 14 Control Bit Settings in Independent Channel Output Mode 1 Bit Name Setting TAUBnTOE TAUBnTOEm 1 Enables independent channel output mode TAUBnTOM TAUBnTOMm 0 Independent channel output TAUBnTOC TAUBnTOCm 0 Operating mode 1 Toggle mode if TAUBnTOM TAUBnTOMm 0 TAUBnTOL TAUBnTOLm 0 Positive logic TAUBnTDE TAUBnTDEm 0 Disables dead time operation TAUBnT...

Page 437: ...ion is stopped Start Operation Set TAUBnTS TAUBnTSm to 1 TAUBnTS TAUBnTSm is a trigger bit which is automatically cleared to 0 TAUBnTE TAUBnTEm is set to 1 and the counter starts The TAUBnCDRm value is loaded in TAUBnCNTm When TAUBnCMORm MD0 1 INTTAUBnIm is generated and TAUBnTTOUTm toggles During Operation The TAUBnCDRm register value can be changed at any time The TAUBnCNTm register can be read ...

Page 438: ...esulting in TAUBnTTOUTm toggling every count clock b TAUBnCDRm 0000H count clock PCLK Figure 13 20 TAUBnCDRm 0000H Count Clock PCLK If TAUBnCDRm 0000H and the count clock PCLK the TAUBnCDRm value is loaded into TAUBnCNTm every PCLK clock meaning that TAUBnCNTm is always 0000H INTTAUBnIm is generated continuously resulting in TAUBnTTOUTm toggling every PCLK clock Count clock Count clock cycle TAUBn...

Page 439: ...UBnTSm to 1 d Forced restart Figure 13 22 Forced Restart Operation TAUBnCMORm TAUBnMD0 1 The counter can be forcibly restarted without stopping it first by setting TAUBnTS TAUBnTSm to 1 during operation If the TAUBnCMORm TAUBnMD0 bit is set to 1 the first interrupt after a start or restart is generated a a 1 Operation start Operation start TAUBnCNTm Counter TAUBnCDRm TAUBnTTOUTm INTTAUBnIm b 1 b T...

Page 440: ...de See Table 13 17 TAUBnCMORm Settings for TAUBnTTINm Input Interval Timer Function The channel output mode should be set to independent channel output mode 1 See Section 13 8 Channel Output Modes Description This function operates in an identical manner to the interval timer function see Section 13 13 1 Interval Timer Function except that this function is restarted by a valid TAUBnTTINm input edg...

Page 441: ...TIS 1 0 01B Figure 13 24 General Timing Diagram of TAUBnTTINm Input Interval Timer Function INT Trigger from upper channel Trigger from upper channe Start trigger from master Simultaneous rewrite INT from master INT from upper channe Clock selector Count clock edge selector Trigger selector Trigger from lower channel Start and capture trigger Interval timer mode TAUBnCNTm TAUBnTO TAUBnTOm TAUBnTRO...

Page 442: ...tion clock CK3 TAUBnCCS 1 0 00 Uses an operation clock as a count clock TAUBnMAS 0 Unused Set to 0 TAUBnSTS 2 0 001 Valid TAUBnTTINm input edge signal is used as an external start trigger TAUBnCOS 1 0 00 Unused Set to 00 TAUBnMD 4 1 0000 Interval timer mode TAUBnMD0 0 INTTAUBnIm is not generated to toggle TAUBnTTOUTm at the beginning of an operation 1 INTTAUBnIm is generated to toggle TAUBnTTOUTm ...

Page 443: ...ld be set to 0 Table 13 19 Control Bit Settings in Independent Channel Output Mode 1 Bit Name Setting TAUBnTOE TAUBnTOEm 1 Enables independent channel output mode TAUBnTOM TAUBnTOMm 0 Independent channel output TAUBnTOC TAUBnTOCm 0 Operating mode 1 Toggle mode if TAUBnTOM TAUBnTOMm 0 TAUBnTOL TAUBnTOLm 0 Positive logic TAUBnTDE TAUBnTDEm 0 Disables dead time operation TAUBnTDL TAUBnTDLm 0 When dis...

Page 444: ... is automatically cleared to 0 TAUBnTE TAUBnTEm is set to 1 and the counter starts The TAUBnCDRm value is loaded in TAUBnCNTm When TAUBnCMORm TAUBnMD0 1 INTTAUBnIm is generated and TAUBnTTOUTm toggles During Operation The values of the TAUBnCMURm TAUBnTIS 1 0 bits and the TAUBnCDRm register are changeable at any time The TAUBnCNTm register are readable at any time Detection of TAUBnTTINm edge TAUB...

Page 445: ... input edge without using this function Figure 13 25 Counter Triggered by Rising TAUBnTTINm Input Edge TAUBnCMURm TAUBnTIS 1 0 01B TAUBnCMORm TAUBnMD0 1 If a valid TAUBnTTINm input edge is detected an interrupt is generated which causes TAUBnTTOUTm to toggle In this example the valid edge is a rising edge TAUBnCMURm TAUBnTIS 1 0 01B a 1 a 1 b 1 b 1 TAUBnTS TAUBnTSm TAUBnTE TAUBnTEm TAUBnTTINm TAUB...

Page 446: ...BnTEm 1 enabling count operation The counter starts when a valid TAUBnTTINm input edge is detected The value of TAUBnCDRm is loaded into TAUBnCNTm and the counter starts to count down from the TAUBnCDRm value An interrupt is generated and TAUBnTTOUTm toggles When the counter reaches 0001H an interrupt is generated and TAUBnTTOUTm is set to the inactive level The counter stops at 0000H and awaits t...

Page 447: ...e general timing diagram Detection of falling edge TAUBnCMURm TAUBnTIS 1 0 00B Figure 13 27 General Timing Diagram of One Pulse Output Function Trigger Start Capture INTm Clock Sel Trigger Sel Count Clock TAUBnTS TAUBnTSm TAUBnTTINm TAUBn CNTm TAUBn CDRm INTTAUBnIm TAUBnTTOUTm TAUBnTO TAUBnTOm TAUBnTRO TAUBnTROm Trigger from Lower a b 0001H 0000H TAUBnTS TAUBnTSm TAUBnTE TAUBnTEm TAUBnTTINm TAUBnC...

Page 448: ...k CK1 10 Operation clock CK2 11 Operation clock CK3 TAUBnCCS 1 0 00 Uses an operation clock as the count clock TAUBnMAS 0 Unused Set to 0 TAUBnSTS 2 0 001 Valid TAUBnTTINm input edge signal is used as an external start trigger TAUBnCOS 1 0 00 Unused Set to 00 TAUBnMD 4 1 1010 Pulse one count mode TAUBnMD0 0 Disables a start trigger during operation 7 6 5 4 3 2 1 0 TAUBnTIS 1 0 Table 13 23 TAUBnCMU...

Page 449: ...t to 0 Table 13 24 Control Bit Settings in Independent Channel Output Mode 1 Bit Name Setting TAUBnTOE TAUBnTOEm 1 Enables independent channel output mode controlled by software TAUBnTOM TAUBnTOMm 0 Independent channel output TAUBnTOC TAUBnTOCm 1 Independent channel output mode TAUBnTOL TAUBnTOLm 0 Positive logic 1 Inverted logic TAUBnTDE TAUBnTDEm 0 Disables dead time operation TAUBnTDL TAUBnTDLm...

Page 450: ...rigger bit which is automatically cleared to 0 Detection of TAUBnTTINm start edge TAUBnTE TAUBnTEm is set to 1 and TAUBnCNTm waits for detection of the TAUBnTTINm start edge When a start edge is detected TAUBnCNTm loads the TAUBnCDRm value During Operation The value of TAUBnCDRm is changeable at any time The TAUBnCNTm register are readable at any time INTTAUBnIm is generated when TAUBnCNTm starts ...

Page 451: ...ve TAUBnTTINm pulses It also describes functions that measure the interval of the signal or that compare the width of a pulse with a reference value Section 13 14 1 TAUBnTTINm Input Pulse Interval Measurement Function Section 13 14 2 TAUBnTTINm Input Signal Width Measurement Function Section 13 14 3 TAUBnTTINm Input Period Count Detection Function Section 13 14 4 TAUBnTTINm Input Pulse Interval Ju...

Page 452: ...0000H and subsequently continues operation The values transferred to TAUBnCDRm and TAUBnCSRm TAUBnOVF respectively depend on the values of bits TAUBnCMORm TAUBnCOS 1 0 When TAUBnCMORm TAUBnCOS 0 1 the overflow bit TAUBnCSRm TAUBnOVF can be cleared only by setting TAUBnCSCm TAUBnCLOV 1 The combination of the value of TAUBnCDRm and TAUBnCSRm TAUBnOVF can be used to deduce the interval of the TAUBnTT...

Page 453: ...alue of TAUBnCNTm is not loaded into TAUBnCDRm when the first valid TAUBnTTINm input edge occurs after an overflow However an interrupt is generated 2 Equations TAUBnTTINm input pulse interval count clock cycle TAUBnCSRm TAUBnOVFx FFFFH 1 TAUBnCDRm capture value 1 3 Block diagram and general timing diagram Figure 13 28 Block Diagram of TAUBnTTINm Input Pulse Interval Measurement Function Trigger S...

Page 454: ...ration TAUBnCMORm TAUBnMD0 0 Falling edge detection TAUBnCMURm TAUBnTIS 1 0 00B When a valid TAUBnTTINm input is detected after an overflow TAUBnCDRm is changed and TAUBnCSRm TAUBnOVF is set to 1 TAUBnCMORm TAUBnCOS 1 0 00B Figure 13 29 General Timing Diagram of TAUBnTTINm Input Pulse Interval Measurement Function TAUBnTS TAUBnTSm TAUBnTE TAUBnTEm TAUBnTTINm TAUBnCNTm TAUBnCDRm INTTAUBnIm TAUBnCSR...

Page 455: ...lock CK2 11 Operation clock CK3 TAUBnCCS 1 0 00 Uses an operation clock as a count clock TAUBnMAS 0 Unused Set to 0 TAUBnSTS 2 0 001 Valid edge of the TAUBnTTINm input signal is the external capture trigger TAUBnCOS 1 0 See Table 13 27 Effects of Overflow TAUBnMD 4 1 0010 Capture mode TAUBnMD0 0 INTTAUBnIm not generated at the beginning of operation 1 INTTAUBnIm generated at the beginning of opera...

Page 456: ...aneous rewrite The simultaneous rewrite registers TAUBnRDE TAUBnRDS TAUBnRDM and TAUBnRDC cannot be used with the TAUBnTTINm input pulse interval measurement function Therefore these registers should be set to 0 Table 13 30 Simultaneous Rewrite Settings for TAUBnTTINm Input Pulse Interval Measurement Function Bit Name Setting TAUBnRDE TAUBnRDEm 0 Disables simultaneous rewrite TAUBnRDS TAUBnRDSm 0 ...

Page 457: ...ger bit which is automatically cleared to 0 TAUBnTE TAUBnTEm is set to 1 and the counter starts TAUBnCNTm is cleared to 0000H INTTAUBnIm is generated when TAUBnCMORm MD0 is set to 1 During Operation Detection of TAUBnTTINm edges The TAUBnCMURm TAUBnTIS 1 0 bits can be changed at any time The TAUBnCDRm and TAUBnCSRm registers can be read at any time TAUBnCSCm TAUBnCLOV can be written to 1 TAUBnCSRm...

Page 458: ...TAUBnTTINm input edge with no overflow occurring TAUBnCSRm TAUBnOVF is cleared to 0 b TAUBnCMORm TAUBnCOS 1 0 01B Figure 13 31 TAUBnCMORm TAUBnCOS 1 0 01B TAUBnCMORm TAUBnMD0 0 TAUBnCMURm TAUBnTIS 1 0 00B When an overflow occurs the value of TAUBnCDRm remains unchanged and TAUBnCSRm TAUBnOVF is set to1 Upon detection of the next valid TAUBnTTINm input edge the value of TAUBnCNTm is loaded into TAU...

Page 459: ...nCOS 1 0 11B Figure 13 33 TAUBnCMORm TAUBnCOS 1 0 11B TAUBnCMORm TAUBnMD0 0 TAUBnCMURm TAUBnTIS 1 0 00B When an overflow occurs TAUBnCDRm is set to FFFFH and TAUBnCSRm TAUBnOVF is set to 1 Upon detection of the next valid TAUBnTTINm input edge TAUBnCNTm is reset to 0 but TAUBnCDRm and TAUBnCSRm TAUBnOVF remain unchanged Thus the next valid TAUBnTTINm input edge after the overflow is ignored TAUBnC...

Page 460: ...a valid TAUBnTTINm stop edge is detected it overflows The counter is reset to 0000H and subsequently continues operation The values transferred to TAUBnCDRm and TAUBnCSRm TAUBnOVF respectively depend on the values of bits TAUBnCMORm TAUBnCOS 1 0 When TAUBnCMORm TAUBnCOS 0 1 overflow bit TAUBnCSRm TAUBnOVF can be cleared only by setting TAUBnCSCm TAUBnCLOV to 1 The combination of the value of TAUBn...

Page 461: ...s detected after an overflow TAUBnCDRm is changed and TAUBnCSRm TAUBnOVF is set to 1 TAUBnCMORm TAUBnCOS 1 0 00B Figure 13 35 General Timing Diagram of TAUBnTTINm Input Signal Width Measurement Function INT Trigger from upper channel Trigger from upper channel Start trigger from master Simultaneous rewrite INT from master INT fromupper channe Clock selector Count clock edge selector Trigger select...

Page 462: ... Operation clock CK3 TAUBnCCS 1 0 00 Uses an operation clock as a count clock TAUBnMAS 0 Unused Set to 0 TAUBnSTS 2 0 010 Valid edge of the TAUBnTTINm input signal is used as an external start trigger and the reverse edge as a stop trigger TAUBnCOS 1 0 See Table 13 32 Effects or Overflow TAUBnMD 4 1 0110 Capture and one count mode TAUBnMD0 0 Disables the start trigger during operation 7 6 5 4 3 2 ...

Page 463: ...ultaneous rewrite The simultaneous rewrite registers TAUBnRDE TAUBnRDS TAUBnRDM and TAUBnRDC cannot be used with the TAUBnTTINm input signal width measurement function Therefore these registers should be set to 0 Table 13 35 Simultaneous Rewrite Settings for TAUBnTTINm Input Signal Width Measurement Function Bit Name Setting TAUBnRDE TAUBnRDEm 0 Disables simultaneous rewrite TAUBnRDS TAUBnRDSm 0 W...

Page 464: ...is automatically cleared to 0 TAUBnTE TAUBnTEm is set to 1 and TAUBnCNTm waits for detection of TAUBnTTINm start edge When a TAUBnTTINm start edge is detected TAUBnCNTm starts to count up During Operation Detection of TAUBnTTINm edges TAUBnCDRm TAUBnCNTm and TAUBnCSRm registers can be read at any time TAUBnCSC TAUBnCLOV bit can be set to 1 TAUBnCNTm starts to count up from 0000H When TAUBnTTINm va...

Page 465: ...lid TAUBnTTINm input edge with no overflow occurring TAUBnCSRm TAUBnOVF is cleared to 0 b TAUBnCMORm TAUBnCOS 1 0 01B Figure 13 37 TAUBnCMORm TAUBnCOS 1 0 01B TAUBnCMORm TAUBnMD0 0 TAUBnCMURm TAUBnTIS 1 0 11B When an overflow occurs the value of TAUBnCDRm remains unchanged and TAUBnCSRm TAUBnOVF is set to 1 Upon detection of the next valid TAUBnTTINm input edge the value of TAUBnCNTm is loaded int...

Page 466: ...11B When an overflow occurs TAUBnCDRm is set to FFFFH and TAUBnCSRm TAUBnOVF remains 0 Upon detection of the next valid TAUBnTTINm input edge TAUBnCNTm is reset to 0 but TAUBnCDRm and TAUBnCSRm TAUBnOVF remain unchanged Thus the next TAUBnTTINm input valid edge after the overflow is ignored TAUBnTS TAUBnTSm TAUBnTE TAUBnTEm TAUBnTTINm TAUBnCNTm TAUBnCDRm INTTAUBnIm TAUBnCSRm TAUBnOVF b c a FFFFH 0...

Page 467: ...m is set to FFFFH and TAUBnCSRm TAUBnOVF is set to 1 Upon detection of the next valid TAUBnTTINm input edge TAUBnCNTm is reset to 0 but TAUBnCDRm and TAUBnCSRm TAUBnOVF remain unchanged Thus the next valid TAUBnTTINm input edge after the overflow is ignored TAUBnCSRm TAUBnOVF is cleared by setting TAUBnCSCm TAUBnCLOV to 1 CPU TAUBnTS TAUBnTSm TAUBnTE TAUBnTEm TAUBnTTINm TAUBnCNTm TAUBnCDRm INTTAUB...

Page 468: ... detected the current TAUBnCNTm value is loaded into TAUBnCDRm and an interrupt INTTAUBnIm is generated The counter stops and retains its value until the next valid TAUBnTTINm input start edge is detected When the next valid TAUBnTTINm input start edge is detected the counter restarts to count from the value retained when stopped If the counter reaches FFFFH the counter restarts to count from 0000...

Page 469: ... Figure 13 41 General Timing Diagram of TAUBnTTINm Input Period Count Detection Function INT Trigger from upper channel Trigger from upper channel Start trigger from master Simultaneous rewrite INT from master INT fromupper channe Clock selector Count clock edge selector Trigger selector Trigger from lower channel Start and capture trigger TAUBnCNTm TAUBnTO TAUBnTOm TAUBnTRO TAUBnTROm TAUBnCDRm TA...

Page 470: ...n Function Bit Name Setting TAUBnCKS 1 0 00 Operation clock CK0 01 Operation clock CK1 10 Operation clock CK2 11 Operation clock CK3 TAUBnCCS 1 0 00 Uses an operation clock as a count clock TAUBnMAS 0 Unused Set to 0 TAUBnSTS 2 0 010 Valid edge of the TAUBnTTINm input signal is used as an external start trigger and the reverse edge as a stop trigge TAUBnCOS 1 0 01 Set this value TAUBnMD 4 1 1101 C...

Page 471: ...annel operation is stopped Start Operation Set TAUBnTS TAUBnTSm to 1 TAUBnTS TAUBnTSm is a trigger bit which is automatically cleared to 0 Detection of TAUBnTTINm start edge TAUBnTE TAUBnTEm is set to 1 and TAUBnCNTm waits for detection of the TAUBnTTINm start edge When a start edge is detected TAUBnCNTm is cleared to 0000H and starts counting up During Operation Detection of TAUBnTTINm edges The ...

Page 472: ...e counter can be stopped by setting TAUBnTT TAUBnTTm to 1 This sets TAUBnTE TAUBnTEm to 0 TAUBnCNTm stops and the current value is retained If the counter is stopped valid TAUBnTTINm input edges are ignored The counter can be restarted by setting TAUBnTS TAUBnTSm to 1 TAUBnCNTm restarts to count from 0000H TAUBnTS TAUBnTSm TAUBnTE TAUBnTEm TAUBnTT TAUBnTTm TAUBnTTINm TAUBnCNTm TAUBnCDRm INTTAUBnIm...

Page 473: ... operation The current value of TAUBnCDRm is loaded into TAUBnCNTm and the counter starts to count down from this value When a TAUBnTTINm valid edge is detected or TAUBnTS TAUBnTSm is set to 1 the function compares the current values of TAUBnCNTm and TAUBnCDRm An interrupt signal INTTAUBnIm is generated if the result of the comparison is true TAUBnCNTm reloads the value of TAUBnCDRm and subsequent...

Page 474: ...iming Diagram of TAUBnTTINm Input Pulse Interval Judgment Function Trigger from upper channel Trigger from upper channel Start trigger from master Simultaneous rewrite INT from master INT fromupper channe Clock selector Count clock edge selector Trigger selector Trigger fromlower channel Start and capture trigger Judge mode TAUBnTO TAUBnTOm TAUBnTRO TAUBnTROm TAUBnCDRm TAUBnTS TAUBnTSm CK3 0 TAUBn...

Page 475: ...rval Judgment Function Bit Name Setting TAUBnCKS 1 0 00 Operation clock CK0 01 Operation clock CK1 10 Operation clock CK2 11 Operation clock CK3 TAUBnCCS 1 0 00 Uses an operation clock as a count clock TAUBnMAS 0 Unused Set to 0 TAUBnSTS 2 0 001 Valid edge of the TAUBnTTINm input signal is used as an external start trigger TAUBnCOS 1 0 00 Unused Set to 00 TAUBnMD 4 1 0001 Judge mode TAUBnMD0 0 INT...

Page 476: ... TAUBnRDC cannot be used with this function Therefore these registers should be set to 0 Table 13 43 Simultaneous Rewrite Settings for TAUBnTTINm Input Pulse Interval Judgment Function Bit Name Setting TAUBnRDE TAUBnRDEm 0 Disables simultaneous rewrite TAUBnRDS TAUBnRDSm 0 When disabling simultaneous rewrite TAUBnRDE TAUBnRDEm 0 set these bits to 0 TAUBnRDM TAUBnRDMm TAUBnRDC TAUBnRDCm ...

Page 477: ...o 1 TAUBnTS TAUBnTSm is a trigger bit which is automatically cleared to 0 TAUBnTE TAUBnTEm is set to 1 and the counter starts TAUBnCDRm value is loaded into TAUBnCNTm During Operation Detection of TAUBnTTINm edge The value of TAUBnCDRm can be changed at any time The TAUBnCNTm register can be read at any time TAUBnCNTm counts down When a TAUBnTTINm input edge is detected TAUBnCNTm reloads TAUBnCDRm...

Page 478: ...etected the function compares the current values of TAUBnCNTm and TAUBnCDRm An interrupt signal INTTAUBnIm is generated if the result of the comparison is true The counter TAUBnCNTm retains its value until the next valid TAUBnTTINm start edge is detected regardless of the result of the comparison If the counter reaches 0000H before a valid TAUBnTTINm stop edge is detected TAUBnCNTm underflows and ...

Page 479: ...e falling edge TAUBnCMURm TAUBnTIS 1 0 11B Figure 13 46 General Timing Diagram of TAUBnTTINm Input Signal Width Judgment Function INT Trigger from upper channel Trigger from upper channel Start trigger from master Simultaneous rewrite INT from master INT fromupper channe Clock selector Count clock edge selector Trigger selector Trigger fromlower channel Start and capture trigger Capture and one co...

Page 480: ...UBnCKS 1 0 00 Operation clock CK0 01 Operation clock CK1 10 Operation clock CK2 11 Operation clock CK3 TAUBnCCS 1 0 00 Uses an operation clock as a count clock TAUBnMAS 0 Unused Set to 0 TAUBnSTS 2 0 010 Valid edge of the TAUBnTTINm input signal is used as an external start trigger and the reverse edge as a stop triggler TAUBnCOS 1 0 00 Unused Set to 00 TAUBnMD 4 1 0111 Judge and one count mode TA...

Page 481: ...d TAUBnRDC cannot be used with this function Therefore these registers should be set to 0 Table 13 47 Simultaneous Rewrite Settings for TAUBnTTINm Input Signal Width Judgment Function Bit Name Setting TAUBnRDE TAUBnRDEm 0 Disables simultaneous rewrite TAUBnRDS TAUBnRDSm 0 When disabling simultaneous rewrite TAUBnRDE TAUBnRDEm 0 set these bits to 0 TAUBnRDM TAUBnRDMm TAUBnRDC TAUBnRDCm ...

Page 482: ...y cleared to 0 Detection of TAUBnTTINm start edge TAUBnTE TAUBnTEm is set to 1 and TAUBnCNTm waits for detection of TAUBnTTINm start edge When a TAUBnTTINm start edge is detected TAUBnCDRm value is loaded into TAUBnCNTm During Operation Detection of TAUBnTTINm edge The value of TAUBnCDRm can be changed at any time The TAUBnCNTm register can be read at any time TAUBnCNTm counts down When TAUBnTTINm...

Page 483: ...2014 V850E2 PG4 L Section 13 Timer Array Unit B TAUB 13 15 Independent Channel Simultaneous Rewrite Functions This section describes functions that carry out simultaneous rewrite Section 13 15 1 Simultaneous Rewrite Trigger Generation Function Type 1 ...

Page 484: ...r for upper channels TAUBnCDRm buf is loaded into the counter TAUBnCNTm and the counter starts to count down from this value The counter for lower channels start to count according to the selected operating mode Once the counter reaches 0000 H an interrupt occurs on the channel The current value of the corresponding TAUBnCDRm buffer is loaded into TAUBnCNTm to continue operation subsequently If th...

Page 485: ...s rewrite Start trigger from master Simultaneous rewrite INT from master INT fromupper channe Start trigger from master INT from master INT fromupper channe Start trigger from master INT from master INT fromupper channe Trigger from upper channel Trigger from upper channel Clock selector edge selector Trigger selector Clock selector edge selector Trigger selector Clock selector edge selector Trigg...

Page 486: ...Tm is set to 1 which sets the status flag TAUBnRSF TAUBnRSFm 1 enabling simultaneous rewrite 4 Simultaneous rewrite is triggered only by a CH1 interrupt Therefore simultaneous rewrite is not conducted even if enabled 5 Simultaneous rewrite is triggered by INTTAUBnI1 which is generated when TAUBnCNT1 reaches 0000H The TAUBnCDRm values are loaded into the corresponding TAUBnCDRm buffers 6 The counte...

Page 487: ...BnMD 4 1 TAUB nMD0 Table 13 49 TAUBnCMORm Settings for Simultaneous Rewrite Trigger Generation Function Type 1 Bit Name Setting TAUBnCKS 1 0 00 Operation clock CK0 01 Operation clock CK1 10 Operation clock CK2 11 Operation clock CK3 TAUBnCCS 1 0 00 Uses an operation clock as a count clock TAUBnMAS 0 Unused Set to 0 TAUBnSTS 2 0 000 Triggers the counter by software TAUBnCOS 1 0 00 Unused Set to 00 ...

Page 488: ...wer channels Table 13 51 Simultaneous Rewrite Settings for Simultaneous Rewrite Trigger Generation Function Type 1 Bit Name Setting TAUBnRDE TAUBnRDEm 1 Enables simultaneous rewrite TAUBnRDS TAUBnRDSm 1 Selects one of upper channels as simultaneous rewrite control channel TAUBnRDM TAUBnRDMm 0 Loads a simultaneous rewrite control signal when the master channel starts to count TAUBnRDC TAUBnRDCm 1 M...

Page 489: ...e of TAUBnCDRm register Channel operation is stopped Start Operation Set TAUBnTS TAUBnTSm to 1 TAUBnTS TAUBnTSm is a trigger bit which is automatically cleared to 0 TAUBnTE TAUBnTEm is set to 1 and the counter starts TAUBnCDRm value is loaded into TAUBnCNTm If TAUBnCMORm TAUBnMD0 1 INTTAUBnIm occurs During Operation TAUBnRDT TAUBnRDTm and TAUBnCDR CDRm is changeable TAUBnRSF TAUBnRSFm can be alway...

Page 490: ...that generates an interrupt when a certain number of TAUBnTTINm pulses has occurred a function that divides the frequency of TAUBnTTINm and a function that measures the duration between the function start and a TAUBnTTINm input signal Section 13 16 1 External Event Count Function Section 13 16 2 Clock Divide Function Section 13 16 3 TAUBnTTINm Input Position Detection Function ...

Page 491: ...UBnTTINm input edge is detected or the counter is restarted When the counter value reaches 0000H INTTAUBnIm is generated TAUBnCNTm then reloads the TAUBnCDRm value and subsequently continues operation The counter can be stopped by setting TAUBnTT TAUBnTTm to 1 which in turn sets TAUBnTE TAUBnTEm to 0 TAUBnCNTm stops and retains its value The counter can be restarted by setting TAUBnTS TAUBnTSm to ...

Page 492: ...o the general timing diagram Rising edge detection TAUBnCMURm TAUBnTIS 1 0 01B Figure 13 50 General Timing Diagram for External Event Count Function l e S r e g g i r T l e S k c o l C INTm TAUBnTE TAUBnTEm TAUBnTTINm INTTAUBnIm TAUBnTTOUTm TAUBnTRO TAUBnTROm TAUBnTO TAUBnTOm TAUBn CNTm TAUBn CDRm Trigger from Lower 0000H 0003H 0002H 4 events 4 events 3 events TAUBnTS TAUBnTSm TAUBnTE TAUBnTEm TAU...

Page 493: ...13 54 TAUBnCMORm Settings for External Event Count Function Bit Name Setting TAUBnCKS 1 0 00 Operation clock CK0 01 Operation clock CK1 10 Operation clock CK2 11 Operation clock CK3 TAUBnCCS 1 0 01 Valid TAUBnTTINm input edge is used as the count clock TAUBnMAS 0 Unused Set to 0 TAUBnSTS 2 0 000 Triggers the counter by software TAUBnCOS 1 0 00 Unused Set to 00 TAUBnMD 4 1 0011 Event count mode TAU...

Page 494: ...nd TAUBnRDC cannot be used with the external event count function Therefore these registers should be set to 0 Table 13 56 Simultaneous Rewrite Settings for External Event Count Function Bit Name Setting TAUBnRDE TAUBnRDEm 0 Disables simultaneous rewrite TAUBnRDS TAUBnRDSm 0 When disabling simultaneous rewrite TAUBnRDE TAUBnRDEm 0 set these bits to 0 TAUBnRDM TAUBnRDMm TAUBnRDC TAUBnRDCm ...

Page 495: ...m is a trigger bit so it is automatically cleared to 0 TAUBnTE TAUBnTEm is set to 1 and the counter starts TAUBnCNTm loads the TAUBnCDRm value and waits for detection of the TAUBnTTINm input edge During operation Detection of TAUBnTTINm edges The value of TAUBnCDRm can be changed at any time The TAUBnCNTm register can be read at any time TAUBnCNTm performs count down operation each time a TAUBnTTI...

Page 496: ...ation stop and restart Figure 13 52 Operation Stop and Restart TAUBnCMURm TIS 1 0 01B The counter can be stopped by setting TAUBnTT TAUBnTTm to 1 which in turn sets TAUBnTE TAUBnTEm to 0 TAUBnCNTm stops and the current value is retained TAUBnTTINm continues and TAUBnCNTm ignores the valid edge The counter can be restarted by setting TAUBnTS TAUBnTSm to 1 TAUBnCNTm loads the TAUBnCDRm value and res...

Page 497: ...plies a change to TAUBnCDRm immediately The counter can be restarted without stopping it first by setting TAUBnTS TAUBnTSm to 1 during operation The value of TAUBnCDRm is loaded into TAUBnCNTm and the counter awaits the next valid TAUBnTTINm input edge Operation starts Forced restart 4 events 5 events 0003H 0000H 0004H TAUBnTS TAUBnTSm TAUBnTE TAUBnTEm TAUBnTTINm TAUBnCNTm TAUBnCDRm INTTAUBnIm ...

Page 498: ...written at any time and the changed value of TAUBnCDRm is applied the next time the function starts to count down The counter can be stopped by setting TAUBnTT TAUBnTTm 1 which in turn sets TAUBnTE TAUBnTEm 0 TAUBnCNTm and TAUBnTTOUTm stop but retain their values The function can be restarted by setting TAUBnTS TAUBnTSm 1 The counter can also be forcibly restarted without stopping it first by sett...

Page 499: ...tion start TAUBnCMORm TAUBnMD0 1 Rising edge detection TAUBnCMURm TAUBnTIS 1 0 01B Figure 13 55 General Tming Diagram for Clock Divide Function INTn Start Capture Trigger l e S r e g g i r T Count Clock l e S k c o l C Edge Sel TAUBnTS TAUBnTSm TAUBnTTINm TAUBn CNTm TAUBn CDRm INTTAUBnIm TAUBnTTOUTm TAUBnTO TAUBnTOm TAUBnTRO TAUBnTROm Trigger from Lower Divided by 6 Divided by 4 0001H 0002H 0001H ...

Page 500: ... 11 Operation clock CK3 TAUBnCCS 1 0 1 Valid TAUBnTTINm input edge is used as the count clock TAUBnMAS 0 Unused Set to 0 TAUBnSTS 2 0 000 Triggers the counter by software TAUBnCOS 1 0 00 Unused Set to 00 TAUBnMD 4 1 0000 Interval timer mode TAUBnMD0 0 INTTAUBnIm is not generated and TAUBnTTOUTm is not toggled at the beginning of operation 1 INTTAUBnIm is generated and TAUBnTTOUTm is toggled at the...

Page 501: ... 0 Table 13 60 Control Bit Settings for Independent Channel Output Mode 1 Bit Name Setting TAUBnTOE TAUBnTOEm 1 Eables independent channel output mode controlled by software TAUBnTOM TAUBnTOMm 0 Independent channel output TAUBnTOC TAUBnTOCm 0 Operation mode 1 Toggle mode if TAUBnTOM TAUBnTOMm 0 TAUBnTOL TAUBnTOLm 0 Positive logic TAUBnTDE TAUBnTDEm 0 Disables dead time operation TAUBnTDL TAUBnTDLm...

Page 502: ...on Set TAUBnTS TAUBnTSm to 1 TAUBnTS TAUBnTSm is a trigger bit so it is automatically cleared to 0 TAUBnTE TAUBnTEm is set to 1 and the counter starts TAUBnCNTm loads TAUBnCDRm value If TAUBnCMORm TAUBnMD0 is set to 1 INTTAUBnIm occurs and TAUBnTTOUTm is toggled During operation The value of TAUBnCDRm can be changed at any time The TAUBnCNTm register can be read at all times When a TAUBnTTINm inpu...

Page 503: ... output because of the delay time of a noise filter or synchronization circuit placed between the TAUBnlm pin and TAUBn b Restart Figure 13 57 Restart TAUBnCMORm TAUBnMD0 1 TAUBnCMURm TAUBnTIS 1 0 01B To reset the value of TAUBnTTOUTm Set TAUBnTOE TAUBnTOEm 0 when the counter is stopped TAUBnTE TAUBnTEm 0 Then write either 0 or 1 to TAUBnTO TAUBnTOm to set the new start value of TAUBnTTOUTm Divide...

Page 504: ...1 0 01B To reset the value of TAUBnTTOUTm The counter can be forcibly restarted without stopping it first by setting TAUBnTS TAUBnTSTSm 1 during operation The value of TAUBnCDRm is written to TAUBnCNTm and the count operation restarts TAUBnTTOUTm restarts at the same level as before the forced restart TAUBnTS TAUBnTSm TAUBnTE TAUBnTEm TAUBnTTINm TAUBnCNTm TAUBnCDRm TAUBnTTOUTm INTTAUBnIm ...

Page 505: ...n The counter starts to count from 0000H When a valid TAUBnTTINm input edge is detected the current TAUBnCNTm value is loaded into TAUBnCDRm and an interrupt INTTAUBnIm is generated The counter continues to count When the counter reaches FFFFH the counter restarts from 0000H Note TAUBnTTINm input signal is sampled at the frequency of a sampling clock set by the TAUBnCMORm TAUBnCKS 1 0 bits As a re...

Page 506: ...nIm not generated at operation start TAUBnCMORm TAUBnMD0 0 Falling edge detection TAUBnCMURm TAUBnTIS 1 0 00B Figure 13 60 General Timing Diagram for TAUBnTTINm Input Position Detection Function Trigger Start Capture Count Clock INTm Clock Sel Trigger Sel TAUBnTS TAUBnTSm TAUBnTTINm INTTAUBnIm TAUBnTRO TAUBnTROm TAUBn CDRm TAUBn CNTm TAUBnTO TAUBnTOm TAUBnTTOUTm Trigger from Lower FFFFH 0000 H TAU...

Page 507: ...ion Bit Name Setting TAUBnCKS 1 0 00 Operation clock CK0 01 Operation clock CK1 10 Operation clock CK2 11 Operation clock CK3 TAUBnCCS 1 0 0 Uses an operation clock as the count clock TAUBnMAS 0 Unused Set to 0 TAUBnSTS 2 0 001 Valid TAUBnTTINm input edge signal is used as the external capture trigger TAUBnCOS 1 0 01 Set this value TAUBnMD 4 1 1011 Count capture mode TAUBnMD0 0 INTTAUBnIm is not g...

Page 508: ...ot be used with the TAUBnTTINm input position detection function Therefore these registers should be set to 0 Table 13 65 Simultaneous Rewrite Settings for TAUBnTTINm Input Position Detection Function Bit name Setting TAUBnRDE TAUBnRDEm 0 Disables simultaneous rewrite TAUBnRDS TAUBnRDSm 0 When simultaneous rewrite is disabled TAUBnRDE TAUBnRDEm 0 set these bits to 0 TAUBnRDM TAUBnRDMm TAUBnRDC TAU...

Page 509: ...BnTS TAUBnTSm to 1 TAUBnTS TAUBnTSm is a trigger bit so it is automatically cleared to 0 TAUBnTE TAUBnTEm is set to 1 and the counter starts INTTAUBnIm is generated when TAUBnCMORm TAUBnMD0 is set to 1 During operation The TAUBnCMURm TAUBnTIS 1 0 bits can be changed at any time The TAUBnCDRm and TAUBnCSRm registers can be read at any time TAUBnCNTm starts to count up from 0000H When a TAUBnTTINm v...

Page 510: ...can be stopped by setting TAUBnTT TAUBnTTm to 1 which in turn sets TAUBnTE TAUBnTEm to 0 TAUBnCNTm stops and the current value is retained If the counter is stopped valid TAUBnTTINm input edges are ignored The counter can be restarted by setting TAUBnTS TAUBnTSm to 1 TAUBnCNTm restarts to count from 0000H Operation starts Operation starts Operation stops 0000H FFFFH TAUBnTS TAUBnTSm TAUBnTT TAUBnT...

Page 511: ...on 13 Timer Array Unit B TAUB 13 17 Synchronous Channel Operation Functions This section lists all the synchronous channel operation functions provided by the timer array unit A For a general overview of synchronous channel operation see Section 13 3 Functional Description ...

Page 512: ...B TAUB 13 18 Synchronous PWM Signal Functions Triggered at Regular Intervals This section describes functions that generate PWM signals at regular intervals Section 13 18 1 PWM Output Function Section 13 18 2 Delay Pulse Output Function Section 13 18 3 AD Conversion Trigger Output Function Type 1 ...

Page 513: ...rom the TAUBnCDRm value If an INTTAUBnlm occurs on the master channel and TAUBnTTOUTm slave is set reset PWM output is made Master channel When the master channel counter reaches 0000H and the pulse cycle time has passed INTTAUBnIm occurs The counter loads TAUBnCDRm value into TAUBnCNTm and counts down Slave channels When INTTAUBnIm occurs on the master channel the counter operation of the slave c...

Page 514: ... mode Start trigger from master INT from master INT from master INT fromupper channe INT fromupper channe Simultaneous rewrite trigger from upper channels Slave Master Trigger from upper channel Trigger from upper channel Trigger from lower channel Trigger from lower channel Count clock Count clock Start and capture trigger Clock selector Clock selector Trigger selector Trigger selector Start and ...

Page 515: ...WM Output Function Note The interval between the slave channel starting to count and an interrupt being generated is the value of corresponding TAUBnCDRm whereas for the master channel the interval is the value of the corresponding TAUBnCDRm 1 c c a 1 a a 1 b 1 b b 1 c d d d Master Slave TAUBnTS TAUBnTSm TAUBnTE TAUBnTEm TAUBnTTOUTm TAUBnCNTm TAUBnCDRm INTTAUBnIm TAUBnTS TAUBnTSm TAUBnTE TAUBnTEm ...

Page 516: ...e Setting TAUBnCKS 1 0 00 Prescaler output CK0 01 Prescaler output CK1 10 Prescaler output CK2 11 Prescaler output CK3 TAUBnCKS 1 0 bits of master and slave channels should have the same value TAUBnCCS 1 0 00 Uses an operation clock as a count clock TAUBnMAS 1 Master channel TAUBnSTS 2 0 000 Triggers the counter by software TAUBnCOS 1 0 00 Unused Set to 00 TAUBnMD 4 1 0000 Interval timer mode TAUB...

Page 517: ...or this channel are as follows TAUBnCDR setting for the master channel targeted for simultaneous rewrite 1 interrupt count 1 Master channels TAUBnRDCm 0 TAUBnRDS 1 Slave channels TAUBnRDCm 0 TAUBnRDS 1 If TAUBnCDRm slave setting TAUBnCDRm master setting 1 100 duty output should be provided through aggregation Table 13 69 Simultaneous Rewrite Settings for Master Channels of the PWM Output Function ...

Page 518: ...me Setting TAUBnCKS 1 0 00 Prescaler output CK0 01 Prescaler output CK1 10 Prescaler output CK2 11 Prescaler output CK3 TAUBnCKS 1 0 bits of master and slave channels should have the same value TAUBnCCS 1 0 00 Uses an operation clock as a count clock TAUBnMAS 0 Slave channel TAUBnSTS 2 0 100 INTTAUBnIm of master channel is a start trigger TAUBnCOS 1 0 00 Unused Set to 00 TAUBnMD 4 1 0100 One count...

Page 519: ...bles dead time operation TAUBnTDL TAUBnTDLm 0 When disabling dead time operation TAUBnTDE TAUBnTDEm 0 set these bits to 0 Table 13 73 Simultaneous Rewrite Settings for Slave Channels of PWM Output Function Bit Name Setting TAUBnRDE TAUBnRDEm 1 Enables simultaneous rewrite TAUBnRDS TAUBnRDSm 0 Monitors master channel for simultaneous rewrite triggers 1 Monitors upper channel other than the channel ...

Page 520: ... is set to 1 and the counters of master and slave channels start INTTAUBnIm is generated on the master channel and TAUBnTTOUTm slave is set During Operation TAUBnCDRm can be changed at any time TAUBnCNTm and TAUBnRSF TAUBnRSFm can be read at any time TAUBnRDT TAUBnRDTm can be changed during operation TAUBnCNTm of master channel loads TAUBnCDRm value and counts down When the counter reaches 0000H I...

Page 521: ...e the master channel generates an interrupt INTTAUBnIm 0000H is loaded in to TAUBnCNTm slave Therefore TAUBnCNTm slave cannot start to count and TAUBnTTOUTm remains inactive TAUBnCDRm value is loaded into TAUBnCNTm slave to generate an interrupt Master Slave TAUBnTS TAUBnTSm TAUBnTE TAUBnTEm TAUBnCNTm TAUBnCDRm INTTAUBnIm TAUBnTS TAUBnTSm TAUBnTE TAUBnTEm TAUBnTTOUTm TAUBnCNTm TAUBnCDRm INTTAUBnIm...

Page 522: ...UBnTOL TAUBnTOLm Slave 0 If TAUBnCDRm slave value is greater than TAUBnCDRm master value the slave channel counter does not reach 0000H and consequently no interrupt occurs TAUBnTTOUTm remains active Master Slave TAUBnTS TAUBnTSm TAUBnTE TAUBnTEm TAUBnCNTm TAUBnCDRm INTTAUBnIm TAUBnTS TAUBnTSm TAUBnTE TAUBnTEm TAUBnTTOUTm TAUBnCNTm TAUBnCDRm INTTAUBnIm 0000H 0000H b a a 1 a 1 a 1 a 1 ...

Page 523: ... TAUBnTTOUTm of all channels stop and the current values are retained No interrupts are generated The counter can be restarted by setting TAUBnTS TAUBnTSm of master and slave channels to 1 TAUBnCNTm of master and slave channels reload the current values of TAUBnCDRm and start to count down from these values b b a 1 a 1 Master b Slave Operation start Operation start Operation stop TAUBnTS TAUBnTSm ...

Page 524: ... be set to pulse one count mode See Table 13 82 TAUBnCMORm Settings for Slave Channel 2 of Delay Pulse Output Function TAUBnTTOUTm is not used with the master channel and slave channel 2 The channel output mode for slave channel 1 should be set to synchronous channel output mode 1 See Section 13 8 Channel Output Modes The channel output mode for slave channel 3 should be set to independent channel...

Page 525: ... TAUBnCNTm and TAUBnTTOUTm of master and slave channels stop but their values are retained The counter can be restarted by setting TAUBnTS TAUBnTSm to 1 Conditions Simultaneous rewrite can be used with this function See Section 13 7 Simultaneous Rewrite Equations Pulse cycle TAUBnCDRm master 1 count clock cycle Duty width 1 TAUBnCDRm slave 1 count clock cycle Delay width TAUBnCDRm slave 2 1 count ...

Page 526: ...om lower channel Count clock Count clock Count clock Count clock Start and capture trigger Start and capture trigger Start and capture trigger Start and capture trigger edge selector edge selector edge selector edge selector Slave 1 Slave 1 Slave 2 Slave 2 Slave 3 Master Slave 3 Pulse one count mode Slave 2 One count mode Slave 1 One count mode Clock selector Trigger selector Clock selector Trigge...

Page 527: ...Diagram of Delay Pulse Output Function a c e g c e 1 e 1 h h g g c a 1 a 1 b 1 b 1 c d d h d f d b 0000H 0000H 0000H 0000H 0001H Slave 1 Slave 1 Slave 2 Slave 2 Slave 3 Master TAUBnTS TAUBnTSm TAUBnTE TAUBnTEm TAUBnCNTm TAUBnTTOUTm TAUBnCDRm INTTAUBnIm TAUBnTS TAUBnTSm TAUBnTE TAUBnTEm TAUBnCNTm TAUBnTTOUTm TAUBnCDRm INTTAUBnIm TAUBnTS TAUBnTSm TAUBnTE TAUBnTEm TAUBnCNTm TAUBnTTOUTm TAUBnCDRm INTT...

Page 528: ... 2 0 TAUBnCOS 1 0 TAUBnMD 4 1 TAUBn MD0 Table 13 75 TAUBnCMORm Settings for Master Channels of the Delay Pulse Output Function Bit Name Setting TAUBnCKS 1 0 00 Prescaler output CK0 01 Prescaler output CK1 10 Prescaler output CK2 11 Prescaler output CK3 TAUBnCKS 1 0 bits of master and slave channels should have the same value TAUBnCCS 1 0 00 Uses an operation clock as a count clock TAUBnMAS 1 Maste...

Page 529: ...e Output Function Bit Name Setting TAUBnRDE TAUBnRDEm 1 Enables simultaneous rewrite TAUBnRDS TAUBnRDSm 0 Master channel is simultaneous rewrite control channel TAUBnRDM TAUBnRDMm 0 Generates a simultaneous rewrite trigger signal when master channel starts to count TAUBnRDC TAUBnRDCm 0 INTTAUBnIm signal used to trigger a simultaneous rewrite is not monitored on the channel When TAUBnRDS TAUBnRDSm ...

Page 530: ... Name Setting TAUBnCKS 1 0 00 Prescaler output CK0 01 Prescaler output CK1 10 Prescaler output CK2 11 Prescaler output CK3 TAUBnCKS 1 0 bits of master and slave channels should have the same value TAUBnCCS 1 0 00 Uses an operation clock as a count clock TAUBnMAS 0 Slave channel TAUBnSTS 2 0 100 INTTAUBnIm of master channel is a start trigger TAUBnCOS 1 0 00 Unused Set to 00 TAUBnMD 4 1 0100 One co...

Page 531: ...ve logic 1 Inverted logic TAUBnTDE TAUBnTDEm 0 Disables dead time operation TAUBnTDL TAUBnTDLm 0 When disabling dead time operation TAUBnTDE TAUBnTDEm 0 set these bits to 0 Table 13 81 Simultaneous Rewrite Settings for Slave Channel 1 of Delay Pulse Output Function Bit Name Setting TAUBnRDE TAUBnRDEm 1 Enables simultaneous rewrite TAUBnRDS TAUBnRDSm 0 Master channel is simultaneous rewrite control...

Page 532: ... Name Setting TAUBnCKS 1 0 00 Prescaler output CK0 01 Prescaler output CK1 10 Prescaler output CK2 11 Prescaler output CK3 TAUBnCKS 1 0 bits of master and slave channels should have the same value TAUBnCCS 1 0 00 Uses an operation clock as a count clock TAUBnMAS 0 Slave channel TAUBnSTS 2 0 100 INTTAUBnIm of master channel is a start trigger TAUBnCOS 1 0 00 Unused Set to 00 TAUBnMD 4 1 0100 One co...

Page 533: ...uld have the same simultaneous rewrite settings Table 13 84 Simultaneous Rewrite Settings for Slave Channel 2 of Delay Pulse Output Function Bit Name Setting TAUBnRDE TAUBnRDEm 1 Enables simultaneous rewrite TAUBnRDS TAUBnRDSm 0 Master channel is simultaneous rewrite control channel TAUBnRDM TAUBnRDMm 0 Generates a simultaneous rewrite trigger signal when master channel starts to count TAUBnRDC TA...

Page 534: ...CKS 1 0 00 Prescaler output CK0 01 Prescaler output CK1 10 Prescaler output CK2 11 Prescaler output CK3 TAUBnCKS 1 0 bits of master and slave channels should have the same value TAUBnCCS 1 0 00 Uses an operation clock as a count clock TAUBnMAS 0 Slave channel TAUBnSTS 2 0 101 INTTAUBnIm of upper channel m 1 is a start trigger regardless of master setting TAUBnCOS 1 0 00 Unused Set to 00 TAUBnMD 4 ...

Page 535: ...Inverted logic TAUBnTDE TAUBnTDEm 0 Disables dead time operation TAUBnTDL TAUBnTDLm 0 When disabling dead time operation TAUBnTDE TAUBnTDEm 0 set these bits to 0 Table 13 88 Simultaneous Rewrite Settings for Slave channel 3 of Delay Pulse Output Function Bit Name Setting TAUBnRDE TAUBnRDEm 1 Enables simultaneous rewrite TAUBnRDS TAUBnRDSm 0 Master channel is simultaneous rewrite control channel TA...

Page 536: ... as described in 3 Register settings for master channels Slave channel 1 Set TAUBnCMORm and TAUBnCMURm registers and the channel output mode as described in 4 Register settings for slave channel 1 Slave channel 2 Set TAUBnCMORm and TAUBnCMURm registers and the channel output mode as described in 5 Register settings for slave channel 2 Slave channel 3 set the TAUBnCMORm and TAUBnCMURm registers and...

Page 537: ...0000H INTTAUBnIm master is generated TAUBnCDRm value is reloaded into TAUBnCNTm master to continue count operation TAUBnCDRm value is reloaded into TAUBnCNTm slave 1 2 to start countdown TAUBnTTOUTm slave 1 is set When TAUBnCNTm slave 1 reaches 0000H INTTAUBnIm slave 1 is generated TAUBnTTOUTm slave 1 is reset When TAUBnCNTm slave 2 reaches 0000H INTTAUBnIm slave 2 is generated TAUBnTTOUTm slave 3...

Page 538: ...m slave 2 0000H TAUBnCDRm slave 3 000BH Figure 13 69 Duty Cycle Slave 3 100 If the value of TAUBnCDRm slave 1 and 3 is higher than the value of TAUBnCDRm master the counter of the slave channels cannot reach 0000H and cannot generate interrupts TAUBnTTOUTm of channels 1 and 3 remain active Delay pulse 0000H 0000H 0001H 0000H 0000H TAUBnTS TAUBnTSm TAUBnCNTm INTTAUBnIm INTTAUBnIm INTTAUBnIm INTTAUB...

Page 539: ...ue of TAUBnCDRm master the counter of the slave channels cannot reach 0000H and cannot generate interrupts TAUBnTTOUTm of channels 1 and 3 remain active If TAUBnCDRm slave 2 0000H the counter of slave channel 3 starts counting one count clock later than the counter of slave channel 1 The reference pulse and the delay pulse are output with a delay of one clock count PCLK Operation clock Master Slav...

Page 540: ...ster Interval timer mode Start trigger from master Start trigger from master INT from master INT from master INT fromupper channe INT fromupper channe Trigger from upper channel Trigger from upper channel Simultaneous rewrite trigger from upper channels Trigger fromlower channel Trigger fromlower channel Count clock Count clock Start and capture trigger Start and capture trigger edge selector edge...

Page 541: ...general timing diagram Slave channels Positive logic TAUBnTOL TAUBnTOLm 0 Figure 13 72 General Timing Diagram of AD Conversion Trigger Output Function Type 1 c a 1 a b a 1 b 1 b 1 d 0000H 0000H c 1 c 1 d 1 d 1 Slave Master TAUBnCNTm TAUBnTS TAUBnTSm TAUBnTE TAUBnTEm TAUBnCDRm TAUBnTTOUTm INTTAUBnIm TAUBnTS TAUBnTSm TAUBnTE TAUBnTEm TAUBnCNTm TAUBnCDRm INTTAUBnIm ...

Page 542: ...PG4 L Section 13 Timer Array Unit B TAUB 13 19 Synchronous PWM Signal Functions Triggered by an External Signal This section describes functions that generate PWM signals and which are triggered by an external signal Section 13 19 1 One Shot Pulse Output Function ...

Page 543: ...ion The counters are enabled by setting the channel trigger bits TAUBnTS TAUBnTSm to 1 This sets TAUBnTE TAUBnTEm enabling count operation Master channel When the next valid TAUBnTTINm input edge is detected the current value of TAUBnCDRm is loaded into TAUBnCNTm The counter starts to count down from this value If TAUBnCMORm MD0 0 a trigger TAUBnTTINm which is detected within the delay time is ign...

Page 544: ... sampled at the frequency of a sampling clock set by the TAUBnCMORm TAUBnCKS 1 0 bits As a result the output cycle of TAUBnTTOUTm has an error of 1 operation clock cycle Conditions If TAUBnCMORn TAUBnMD0 of master channel is set to 0 TAUBnTTINm input edges detected during counting are ignored Simultaneous rewrite can be used with this function See Section 13 7 Simultaneous Rewrite Equations Delay ...

Page 545: ... master INT from master INT fromupper channe Start trigger from master INT from master INT fromupper channe Simultaneous rewrite trigger from upper channels Slave Master Trigger from upper channel Trigger from upper channel Trigger fromlower channel Trigger fromlower channel Count clock Count clock Start and capture trigger Start and capture trigger TAUBnTS TAUBnTSm CK3 0 TAUBnTTINm TAUBnTTOUTm IN...

Page 546: ... is disabled during counting TAUBnCMORm TAUBnMD0 0 Detection of falling edge TAUBnCMURm TAUBnTIS 1 0 00B Figure 13 74 General Timing Diagram of One Shot Pulse Output Function Slave Master a 1 b b a a 1 b TAUBnTS TAUBnTSm TAUBnTE TAUBnTEm TAUBnCNTm TAUBnTTINm TAUBnCDRm INTTAUBnIm TAUBnTS TAUBnTSm TAUBnTE TAUBnTEm TAUBnTTOUTm TAUBnTTOUTm TAUBnCNTm TAUBnCDRm INTTAUBnIm 0001H 0000H 0000H ...

Page 547: ... 1 0 bits of master and slave channels should have the same value TAUBnCCS 1 0 00 Uses an operation clock as a count clock TAUBnMAS 1 Master channel TAUBnSTS 2 0 001 Valid TAUBnTTINm input edge signal is used as a start trigger TAUBnCOS 1 0 00 Unused Set to 00 TAUBnMD 4 1 0100 One count mode TAUBnMD0 0 Disables detection of start trigger during count operation 1 Enables detection of start trigger ...

Page 548: ...r master and slave channel should be identical Table 13 92 Simultaneous Rewrite Settings for Master Channels of One Shot Pulse Output Function Bit Name Setting TAUBnRDE TAUBnRDEm 1 Enables simultaneous rewrite TAUBnRDS TAUBnRDSm 0 Master channel is simultaneous rewrite control channel TAUBnRDM TAUBnRDMm 0 Generates a simultaneous rewrite trigger signal when master channel starts to count TAUBnRDC ...

Page 549: ...Prescaler output CK2 11 Prescaler output CK3 TAUBnCKS 1 0 bits of master and slave channels should have the same value TAUBnCCS 1 0 00 Uses an operation clock as a count clock TAUBnMAS 0 Slave channel TAUBnSTS 2 0 100 INTTAUBnIm of master channel is a start trigger TAUBnCOS 1 0 00 Unused Set to 00 TAUBnMD 4 1 1010 Pulse one count mode TAUBnMD0 0 Disables detection of start trigger during count ope...

Page 550: ...erted logic TAUBnTDE TAUBnTDEm 0 Disables dead time operation TAUBnTDL TAUBnTDLm 0 When disabling dead time operation TAUBnTDE TAUBnTDEm 0 set this bit to 0 Table 13 96 Simultaneous Rewrite Settings for Slave Channels of One Shot Pulse Output Function Bit Name Setting TAUBnRDE TAUBnRDEm 1 Enables simultaneous rewrite TAUBnRDS TAUBnRDSm 0 Master channel is simultaneous rewrite control channel TAUBn...

Page 551: ...INm input During Operation TAUBnCDRm is changeable at any time TAUBnCNTm and TAUBnRSF TAUBnRSFm are readable at any time TAUBnRDT TAUBnRDTm is changeable during operation When valid TAUBnTTINm input edge is detected TAUBnCDRm value of master channel is loaded into TAUBnCNTm to start countdown When the counter reaches 0000H INTTAUBnIm master is generated TAUBnCNTm master returns to FFFFH again and ...

Page 552: ...AUBnCMURm TAUBnTIS 1 0 00B Figure 13 75 TAUBnCDRm Master 0000H When a valid TAUBnTTINm input edge is detected the value 0000H is written to TAUBnCNTm master The counter is set to 0000H for one count and returns to FFFFH Thus the slave channel starts to count down one count clock later than TAUBnTTINm master a a 0000H 0000H 0000H TAUBnTS TAUBnTSm TAUBnTS TAUBnTSm TAUBnTE TAUBnTEm TAUBnTE TAUBnTEm T...

Page 553: ...Falling edge detection TAUBnCMURm TAUBnTIS 1 0 00B Figure 13 76 TAUBnCDRm Slave 0000H The counter of the slave channel reloads the value 0000H and returns to FFFFH one clock count later TAUBnTTOUTm remains inactive because the pulse width is zero a 1 a 1 TAUBnTS TAUBnTSm TAUBnTS TAUBnTSm TAUBnTE TAUBnTEm TAUBnTE TAUBnTEm TAUBnTTOUTm TAUBnTTOUTm INTTAUBnIm INTTAUBnIm TAUBnTTINm TAUBnCDRm TAUBnCDRm ...

Page 554: ...AUBnMD0 1 If a valid TAUBnTTINm input edge is detected while the counter of the master channel counts down TAUBnCNTm reloads the value of TAUBnCDRm The counter restarts to count down This means the delay of interrupt generation interval is extended by the value of TAUBnCNTm at the time a valid TAUBnTTINm input edge is detected a 1 b b TAUBnTS TAUBnTSm TAUBnTS TAUBnTSm TAUBnTE TAUBnTEm TAUBnTE TAUB...

Page 555: ...errupt master is ignored If an interrupt of the master channel occurs when the counter of the slave channel waits for the next trigger the value of TAUBnCDRm slave is reloaded An interrupt is generated and TAUBnTTOUTm is toggled If TAUBnCNTm master has started to count down while the TAUBnCNTm slave is still counting 2 TAUBnTTOUTm is not output with the expected delay time To generate correct one ...

Page 556: ...y Unit B TAUB 13 20 Synchronous Triangle PWM Functions This chapter describes functions that generate a triangle PWM output Section 13 20 1 Triangle PWM Output Function Section 13 20 2 Triangle PWM Output Function with Dead Time Section 13 20 3 AD Conversion Trigger Output Function Type 2 ...

Page 557: ... Section 13 8 Channel Output Modes The channel output mode for slave channels should be set to synchronous channel output mode 2 See Section 13 8 Channel Output Modes The following settings allows TAUBnTTOUTm to be at high level during the down status of a carrier cycle If TAUBnCMORm TAUBnMD0 master bit is set to 0 TAUBnTO TAUBnTOm should be set to 1 while TAUBnTOE TAUBnTOEm is set to 0 recommende...

Page 558: ...L TAUBnTOLm allows TAUBnTTOUTm signal switching between normal phase and reverse phase during operation The counter can be stopped by setting TAUBnTT TAUBnTTm of master and slave channels to 1 This sets TAUBnTE TAUBnTEm 0 TAUBnCNTm and TAUBnTTOUTm of master and slave channels stop but retain their values Note If a forced restart is executed during operation TAUBnTTOUTm is not output as a triangle ...

Page 559: ...rom lower channel Start trigger from master Start trigger from master INT from master INT from master INT fromupper channe Simultaneous rewrite trigger from upper channels Count clock Count clock Start and capture trigger Start and capture trigger edge selector edge selector Slave Master Clock selector Trigger selector Clock selector Trigger selector TAUBnTS TAUBnTSm CK3 0 TAUBnTTINm TAUBnTTOUTm I...

Page 560: ...AUBnIm is generated at the beginning of operation TAUBnCMORm TAUBnMD0 1 Figure 13 80 General Timing Diagram of Triangle PWM Output Function b 1 f 2 a 1 e 2 e e f f Slave Master TAUBnTS TAUBnTSm TAUBnTE TAUBnTEm TAUBnCNTm TAUBnTTOUTm TAUBnCDRm INTTAUBnIm TAUBnTS TAUBnTSm TAUBnTE TAUBnTEm TAUBnCNTm TAUBnTTOUTm TAUBnCDRm INTTAUBnIm 0000H 0001H a a 1 Down a 1 Up b 1 Down b 1 Up b e f ...

Page 561: ... output CK1 10 Prescaler output CK2 11 Prescaler output CK3 TAUBnCKS 1 0 bits of master and slave channels should have the same value TAUBnCCS 1 0 00 Uses an operation clock as a count clock TAUBnMAS 1 Master channel TAUBnSTS 2 0 000 Triggers the counter by software TAUBnCOS 1 0 00 Unused Set to 00 TAUBnMD 4 1 0000 Interval timer mode TAUBnMD0 0 INTTAUBnIm is not generated and TAUBnTTOUTm is not t...

Page 562: ...Lm 0 Positive logic TAUBnTDE TAUBnTDEm 0 Disables dead time operation TAUBnTDL TAUBnTDLm 0 When disabling dead time operation TAUBnTDE TAUBnTDEm 0 set these bits to 0 Table 13 101 Simultaneous Rewrite Settings for Master Channels of Triangle PWM Output Function Bit Name Setting TAUBnRDE TAUBnRDEm 1 Enables simultaneous rewrite TAUBnRDS TAUBnRDSm 0 Monitors master channel for simultaneous rewrite t...

Page 563: ...TAUBnCKS 1 0 00 Prescaler output CK0 01 Prescaler output CK1 10 Prescaler output CK2 11 Prescaler output CK3 TAUBnCKS 1 0 bits of master and slave channels should have the same value TAUBnCCS 1 0 00 Uses an operation clock as a count clock TAUBnMAS 0 Slave channel TAUBnSTS 2 0 111 Up down output trigger signal of master channel TAUBnCOS 1 0 00 Unused Set to 00 TAUBnMD 4 1 1001 Up down count mode T...

Page 564: ...UBnTDLm 0 When disabling dead time operation TAUBnTDE TAUBnTDEm 0 set these bits to 0 Table 13 105 Simultaneous Rewrite Settings for Slave Channels of Triangle PWM Output Function Bit Name Setting TAUBnRDE TAUBnRDEm 1 Enables simultaneous rewrite TAUBnRDS TAUBnRDSm 0 Monitors master channel for simultaneous rewrite triggers 1 Monitors upper channel other than the channel group for simultaneous rew...

Page 565: ...l starts INTTAUBnIm master is generated on the master channel if TAUBnCMORm TAUBnMD0 is set to 1 During Operation TAUBnCDRm can be changed at any time TAUBnCNTm and TAUBnRSF TAUBnRSFm can be read at any time TAUBnRDT TAUBnRDTm can be changed during operation TAUBnCDRm value of master and slave channels is loaded into TAUBnCNTm to perform counting down When the counter of master channel reaches 000...

Page 566: ...Rm a 5H Slave channels TAUBnCDRm 6H Figure 13 81 TAUBnCDRm Slave TAUBnCDRm Master 1 If TAUBnCDRm slave value is greater than TAUBnCDRm master value INTTAUBnIm is not generated while the counter of slave channel is counting down TAUBnTTOUTm remains at the inactive level because there is no set signal of TAUBnTTOUTm to be detected TAUBnTTOUTm TAUBnCNTm INTTAUBnIm TAUBnTTOUTm TAUBnCNTm INTTAUBnIm Sla...

Page 567: ...BnMD0 1 TAUBnCDRm a 5H Slave channels TAUBnCDRm 0H Figure 13 82 TAUBnCDRm Slave 0000H If TAUBnCDRm slave 0000H INTTAUBnlm is not generated while the counter of slave channel is counting up TAUBnTTOUTm remains at the active level because there is no reset signal of TAUBnTTOUTm to be detected TAUBnTTOUTm TAUBnCNTm INTTAUBnIm TAUBnTTOUTm TAUBnCNTm INTTAUBnIm Slave Master Up down switching Up down swi...

Page 568: ...ORm Settings for Master Channels of Triangle PWM Output Function with Dead Time Slave channel 1 is not used for this function Be sure to select an even channel for slave channel 2 and an odd channel for slave channel 3 The operating mode for slave channel 2 should be set to up down count mode See Table 13 112 TAUBnCMORm Settings for Slave Channel 2 of Triangle PWM Output Function with Dead Time Sl...

Page 569: ...of TAUBnCDRm slave 3 is loaded into TAUBnCNTm slave 3 and the counter starts to count down from the TAUBnCDRm value When the counter reaches 0000H INTTAUBnIm occurs The counter returns to FFFFH and waits for the next INTTAUBnlm of slave channel 2 As described in Table 13 107 Operation of TAUBnTTOUTm upon Occurrence of an Interrupt on Slave Channel 2 the set reset timing right after occurrence of a...

Page 570: ...DRm slave 2 2 TAUBnCDRm slave 3 1 count clock cycle PWM signal width reverse phase TAUBnCDRm master 1 TAUBnCDRm slave 2 2 TAUBnCDRm slave 3 1 count clock cycle Table 13 107 Operation of TAUBnTTOUTm upon Occurrence of an Interrupt on Slave Channel 2 TAUBnTDL TAUBnTDLm Count Direction of Slave Channel 2 upon Occurrence of Interrupt TAUBnTTOUTm Set Reset Timing 0 Down Set after elapse of dead time Up...

Page 571: ... channel Trigger from lower channel Start trigger from master Start trigger from master Start trigger from master INT from master INT from master INT from master INT from master INT from upper channel INT from upper channel INT from lower channel INT from lower channel Simultaneous rewrite trigger from upper channels Slave 1 Master Slave 2 Slave 1 Slave 2 Slave 3 Clock selector Trigger selector Cl...

Page 572: ... INTTAUBnIm is generated at the beginning of operation TAUBnCMORm TAUBnMD0 1 Slave channel 2 INTTAUBnIm is not generated at the beginning of operation TAUBnCMORm TAUBnMD0 0 TAUBnTDL TAUBnTDLm 0 Positive logic TAUBnTOL TAUBnTOLm 0 Slave channel 3 INTTAUBnIm is generated at the beginning of operation TAUBnCMORm TAUBnMD0 1 TAUBnTDL TAUBnTDLm 1 Negative logic TAUBnTOL TAUBnTOLm 1 ...

Page 573: ...nTOLm 0 TAUBnTDL TAUBnTDLm 1 TAUBnTOL TAUBnTOLm 0 TAUBnTTOUTm Slave 2 3 g 1 g 1 g 1 g 1 g 1 a 1 a b a 1 b 1 b 1 Down Up Down Up a 1 e 2 b 1 f 2 e e f f f g e Slave 1 Slave 2 Slave 2 Slave 2 Slave 3 Slave 3 Slave 3 Master TAUBnTS TAUBnTSm TAUBnTE TAUBnTEm TAUBnCNTm TAUBnTTOUTm TAUBnCDRm INTTAUBnIm TAUBnTS TAUBnTSm TAUBnTE TAUBnTEm TAUBnCNTm TAUBnCDRm INTTAUBnIm TAUBnTS TAUBnTSm TAUBnTE TAUBnTEm TAU...

Page 574: ... output CK1 10 Prescaler output CK2 11 Prescaler output CK3 TAUBnCKS 1 0 bits of master and slave channels should have the same value TAUBnCCS 1 0 00 Uses an operation clock as a count clock TAUBnMAS 1 Master channel TAUBnSTS 2 0 000 Triggers the counter by software TAUBnCOS 1 0 00 Unused Set to 00 TAUBnMD 4 1 0000 Interval timer mode TAUBnMD0 0 INTTAUBnIm is not generated and TAUBnTTOUTm is not t...

Page 575: ...ive logic TAUBnTDE TAUBnTDEm 0 Disables dead time operation TAUBnTDL TAUBnTDLm 0 When disabling dead time operation TAUBnTDE TAUBnTDEm 0 set these bits to 0 Table 13 111 Simultaneous Rewrite for Master Channels of Triangle PWM Output Function with Dead Time Bit Name Setting TAUBnRDE TAUBnRDEm 1 Enables simultaneous rewrite TAUBnRDS TAUBnRDSm 0 Monitors master channels for simultaneous rewrite trig...

Page 576: ... TAUBnCKS 1 0 00 Prescaler output CK0 01 Prescaler output CK1 10 Prescaler output CK2 11 Prescaler output CK3 TAUBnCKS 1 0 bits of master and slave channels should have the same value TAUBnCCS 1 0 00 Uses an operation clock as a count clock TAUBnMAS 0 Slave channel TAUBnSTS 2 0 111 Up down output trigger signal of master channel TAUBnCOS 1 0 00 Unused Set to 00 TAUBnMD 4 1 1001 Up down count mode ...

Page 577: ...dead time operation TAUBnTDL TAUBnTDLm 0 Adds dead time to normal phase 1 Adds dead time to reverse phase Table 13 115 Simultaneous Rewrite Settings for Slave Channel 2 of Triangle PWM Output Function Bit Name Setting TAUBnRDE TAUBnRDEm 1 Enables simultaneous rewrite TAUBnRDS TAUBnRDSm 0 Monitors master channels for simultaneous rewrite triggers 1 Monitors upper channels other than the channel gro...

Page 578: ... Time Bit Name Setting TAUBnCKS 1 0 00 Prescaler output CK0 01 Prescaler output CK1 10 Prescaler output CK2 11 Prescaler output CK3 TAUBnCKS 1 0 bits of master and slave channels should have the same value TAUBnCCS 1 0 00 Uses an operation clock as a count clock TAUBnMAS 0 Slave channel TAUBnSTS 2 0 110 Dead time trigger TAUBnCOS 1 0 00 Unused Set to 00 TAUBnMD 4 1 0100 One count mode TAUBnMD0 1 E...

Page 579: ...Enables dead time operation TAUBnTDL TAUBnTDLm 0 Adds dead time to normal phase 1 Adds dead time to reverse phase Table 13 119 Simultaneous Rewrite Settings for Slave Channel 3 of Triangle PWM Output Function Bit Name Setting TAUBnRDE TAUBnRDEm 1 Enables simultaneous rewrite TAUBnRDS TAUBnRDSm 0 Monitors master channels for simultaneous rewrite triggers 1 Monitors upper channels other than the cha...

Page 580: ...ls is set to 1 and the counter of master slave channel starts INTTAUBnIm master is generated on the master channel if TAUBnCMORm TAUBnMD0 is set to 1 During Operation TAUBnCDRm can be changed at any time TAUBnCNTm and TAUBnRSF TAUBnRSFm can be read at any time TAUBnRDT TAUBnRDTm can be changed during operation TAUBnCDRm value of master channel and slave channel 2 is loaded into TAUBnCNTm to perfor...

Page 581: ...enerated while the counter of slave channel 2 or 3 is counting down TAUBnTTOUTm remains at the inactive level because there is no set signal of TAUBnTTOUTm to be detected TAUBnCNTm master TAUBnTTOUTm master INTTAUBnIm master TAUBnTTOUTm slave 3 TAUBnTTOUTm slave 3 TAUBnCNTm slave 2 INTTAUBnIm slave 2 TAUBnCNTm slave 3 INTTAUBnIm slave 3 CDRm 1 master CDRm 1 master CDRm 1 master CDRm 1 master CDRm ...

Page 582: ...6 TAUBnCDRm Slave 2 0000H TAUBnCNTm master TAUBnTTOUTm master INTTAUBnIm master TAUBnTTOUTm slave 2 TAUBnTDL TAU BnTDLm 0 TAUBnTTOUTm slave 3 TAUBnTDL TAU BnTDLm 1 TAUBnCNTm slave 2 INTTAUBnIm slave 2 TAUBnCNTm slave 3 INTTAUBnm slave 3 TAUBnTTOUTm Slave 2 3 Up down switching Up down switching CDRm load slave 2 CDRm load slave 2 CDRm 1 master CDRm 1 master CDRm 1 master CDRm 1 master Slave 1 Slave...

Page 583: ...cibly set and remains at the active level thereafter positive phase output is set after securing dead time and remains at the active level thereafter The set conditions for a channel with TAUBnTDL TAUBnTDLm 0 are met after elapse of dead time TAUBnTTOUTm is left in a newly set state even if a set reset is made because no reset conditions are satisfied on such a channel Slave channel 3 in the above...

Page 584: ...master 0005H TAUBnCDRm slave 2 0005H TAUBnCDRm slave 3 0004H CDRm 1 master down up CDRm load slave 2 CDRm load slave 2 CDRm load slave 3 CDRm load slave 3 Up down switching INT does not occur INT slave 2 Slave 3 Slave 2 Slave 3 Master Slave 2 Slave 1 INT slave 3 No change TAUBnCNTm master INTTAUBnIm master TAUBnTTOUTm master TAUBnCNTm slave 2 INTTAUBnIm slave 2 TAUBnCNTm slave 3 INTTAUBnIm slave 3...

Page 585: ...g down from this value In the diagram above the first interrupt on channel 2 occurs while the counter is counting down and the second whilst it is counting up After the first interrupt a slave for which TAUBnTDL TDLm 0 waits for dead time to elapse before setting However before the dead time has elapsed another interrupt occurs on slave 2 this time while the counter is counting up This acts as a r...

Page 586: ...H PWM signal width negative phase Carrier cycle Slave 3 Slave 2 Slave 3 Master Slave 2 Slave 1 CDRm 1 master CDRm load slave 2 down up CDRm load slave 2 CDRm load slave 3 CDRm load slave 3 CDRm load slave 3 CDRm load slave 3 Up down switching INT slave 2 INT slave 2 INT slave 2 INT slave 3 INT slave 3 No change INT does not occur TAUBnCNTm master INTTAUBnIm master TAUBnTTOUTm master TAUBnCNTm slav...

Page 587: ...time to elapse before resetting However before the dead time has elapsed another interrupt occurs on slave 2 this time while the counter is counting up This acts as a set signal meaning that a channel for which TAUBnTDL TDLm 1 always remains active TAUBnTTOUTm of a slave channel for which TAUBnTDL TDLm 0 is set and reset as normal when the corresponding INTTAUBnIm is generated ...

Page 588: ...BnCDRm slave 3 0001H PWM signal width positive phase 0 CDRm master 1 CDRm slave 2 load CDRm slave 2 load CDRm slave 3 load CDRm slave 3 load down up Up down switching INT slave 2 Reset INT slave 3 Set Slave 3 Slave 2 Slave 3 Master Slave 2 Slave 1 INT slave 3 INT slave 2 Concurrent occurrence Reset takes priority No change TAUBnCNTm master INTTAUBnIm master TAUBnTTOUTm master TAUBnCNTm slave 2 INT...

Page 589: ...TAUBnIm to set the TAUBnTTOUTm of slave channel for which TAUBnTDL TDLm 0 slave channel 2 in this example If channel 2 generates an INTTAUBnIm to reset TAUBnTTOUTm simultaneously this reset signal has priority assuming TAUBnTOL TOLm 0 otherwise the set signal has priority Therefore TAUBnTTOUTm of a slave channel for which TAUBnTDL TDLm 0 remains in its initial state ...

Page 590: ...nal width negative phase carrier cycle Slave 2 Slave 3 Master Slave 2 Slave 1 CDRm slave 3 load CDRm slave 3 load CDRm slave 3 load CDRm slave 3 load CDRm slave 2 load CDRm slave 2 load CDRm master 1 INT slave 2 INT slave 3 INT slave 2 INT slave 3 INT slave 2 Set INT slave 3 Reset INT slave 2 Concurrent occurrence Set takes priority No change Slave 3 0001H 0000H 0000H TAUBnCNTm master INTTAUBnIm m...

Page 591: ...an INTTAUBnIm to set the TAUBnTTOUTm of slave channel for which TAUBnTDL TDLm 1 slave 3 in this example If channel 2 generates an INTTAUBnIm to reset TAUBnTTOUTm simultaneously the set signal has priority assuming TAUBnTOL TOLm 1 otherwise the reset signal has priority Therefore TAUBnTTOUTm of slave channel for which TAUBnTDL TDLm 1 remains in its initial state ...

Page 592: ...us rewrite trigger from upper channels Trigger from upper channel Trigger from upper channel Count clock Count clock Trigger from lower channel Trigger from lower channel Start and capture trigger Start and capture trigger Slave Master edge selector edge selector INTm INTm Master Interval timer mode Slave Up down count mode Start trigger from master INT from master INT from upper channel Start tri...

Page 593: ...BnIm is generated at the beginning of operation TAUBnCMORm TAUBnMD0 0 Figure 13 92 General Timing Diagram of AD Conversion Trigger Output Function Type 2 Down Up Up Down TAUBnTE TAUBnTEm TAUBnTS TAUBnTSm TAUBnTE TAUBnTEm TAUBnTS TAUBnTSm INTTAUBnIm INTTAUBnIm a 1 e 2 e e f f b 1 f 2 TAUBnCNTm TAUBnCDRm TAUBnCNTm TAUBnCDRm TAUBnTTOUTm Master Slave 0000H 0001H a 1 a 1 b 1 a b e f b 1 ...

Page 594: ...140H m 4H TAUBn channel status clear trigger register m TAUBnCSCm TAUBn_base1 180H m 4H TAUBn channel start trigger register TAUBnTS TAUBn_base1 1C4H TAUBn channel enable status register TAUBnTE TAUBn_base1 1C0H TAUBn channel stop trigger register TAUBnTT TAUBn_base1 1C8H TAUBn output registers TAUBn channel output enable register TAUBnTOE TAUBn_base1 5CH TAUBn channel output register TAUBnTO TAUB...

Page 595: ... 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TAUBnPRS3 3 0 TAUBnPRS2 3 0 TAUBnPRS1 3 0 TAUBnPRS0 3 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Table 13 122 Description of TAUBnTPS Register 1 4 Bit Position Bit Name Function 15 to 12 TAUBnPRS3 3 0 Specifies CK3 clock TAUBnPRS3 3 0 CK3 Clock 0000B PCLK 20 0001B PCLK 21 0010B PCLK 22 0011B PCLK 23 0100B PCLK 24 0101B PCLK 25 0110B PCLK 26 0...

Page 596: ...00B PCLK 20 0001B PCLK 21 0010B PCLK 22 0011B PCLK 23 0100B PCLK 24 0101B PCLK 25 0110B PCLK 26 0111B PCLK 27 1000B PCLK 28 1001B PCLK 29 1010B PCLK 210 1011B PCLK 211 1100B PCLK 212 1101B PCLK 213 1110B PCLK 214 1111B PCLK 215 The above bits are rewritable only when all the counters using CK2 are stopped TAUBnTE TAUBnTEm 0 Table 13 122 Description of TAUBnTPS Register 2 4 Bit Position Bit Name Fu...

Page 597: ...0B PCLK 20 0001B PCLK 21 0010B PCLK 22 0011B PCLK 23 0100B PCLK 24 0101B PCLK 25 0110B PCLK 26 0111B PCLK 27 1000B PCLK 28 1001B PCLK 29 1010B PCLK 210 1011B PCLK 211 1100B PCLK 212 1101B PCLK 213 1110B PCLK 214 1111B PCLK 215 The above bits are rewritable only when all the counters using CK1 are stopped TAUBnTE TAUBnTEm 0 Table 13 122 Description of TAUBnTPS Register 3 4 Bit Position Bit Name Fun...

Page 598: ... CK0 clock TAUBnPRS0 3 0 Prescaler Output CK0 Clock 0000B PCLK 20 0001B PCLK 21 0010B PCLK 22 0011B PCLK 23 0100B PCLK 24 0101B PCLK 25 0110B PCLK 26 0111B PCLK 27 1000B PCLK 28 1001B PCLK 29 1010B PCLK 210 1011B PCLK 211 1100B PCLK 212 1101B PCLK 213 1110B PCLK 214 1111B PCLK 215 The above bits are rewritable only when all the counters using CK0 are stopped TAUBnTE TAUBnTEm 0 Table 13 122 Descrip...

Page 599: ...n TAUBnCMORm TAUBnMD 4 1 Access Readable writable in 16 bit units Readable in capture mode Any write operation is ignored Readable writable in compare mode Address TAUBn_base1 0H m 4H Initial value 0000H This register is initialized by any reset source 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TAUBnCDR 15 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Table 13 123 Description of TAU...

Page 600: ...UBnTS TAUBnTSm or TAUBnTT TAUBnTTm bit value The initial read value of the counter depends on an operating mode and how the counter is stopped Stop by a reset Stop by a counter stop trigger TAUBnTT TAUBnTTm 1 The following table lists the initial counter read values after the counter is stopped TAUBnTE TAUBnTEm 0 and re enabled TAUBnTS TAUBnTSm 1 The table also contains the counter read value one ...

Page 601: ...eset After Stop Trigger After One Count Interval timer mode Count down FFFFH Stop value Judge mode Count down FFFFH Stop value Capture mode Count up 0000H Stop value Event count mode Count dow FFFFH Stop value One count mode Count down FFFFH Stop value FFFFH Capture and one count mode Count up 0000H Stop value Capture value 1 TAUBnCDRm Judge and one count mode Count down FFFFH Stop value TAUBnCNTm...

Page 602: ...ORm Register 1 4 Bit Position Bit Name Function 15 14 TAUBnCKS 1 0 Selects a sampling clock An operation clock is used for the TAUBnTTINm input edge detection circuit TAUBnCMORm TAUBnCCS 1 0 bit setting enables use as a counter clock TAUBn CKS1 TAUBn CKS0 Selection of Operation Clock 0 0 Prescaler output CK0 0 1 Prescaler output CK1 1 0 Prescaler output CK2 1 1 Prescaler output CK3 12 TAUBnCCS0 Se...

Page 603: ...l which is specified by TAUBnCMURm TAUBnTIS 1 0 0 1 0 Valid edge of TAUBnTTINm input signal is used as a start trigger and the opposite edge as a stop trigger 0 1 1 Simultaneous rewrite trigger 1 0 0 INT of master channel 1 0 1 INT of upper channel m 1 regardless of master setting 1 1 0 Dead time output signal of TAUBnTTOUTm generating unit 1 1 1 Up down output trigger signal of master channel Tab...

Page 604: ...ast detection of valid edge set TAUBnCSRm TAUBnOVF If no counter overflow has occurred since the last detection of valid edge clear TAUBnCSRm TAUBnOVF 0 1 Set when a counter overflow occurs and cleared when TAUBnCSCm TAUBnCLOV is set to 1 1 0 Updated upon detection of valid edge of TAUBnTTINm input and at the occurrence of counter overflow Detection of valid edge of TAUBnTTINm input Counter value ...

Page 605: ...Setting prohibited 1 1 0 1 0 Capture and gate count mode Mode Role of TAUBnMD0 Bit Interval timer mode Capture mode Count capture mode Specifies whether INTTAUBnIm is generated at the beginning of count operation when a start trigger is entered or not 0 INTTAUBnIm is not generated 1 INTTAUBnIm is generated Event count mode Up down count mode This bit should be set to 0 One count mode Pulse one cou...

Page 606: ... W R W Table 13 127 Description of TAUBnCMURm Register Bit Position Bit Name Function 1 0 TAUBnTIS 1 0 Specifies a valid edge of TAUBnTTINm input signal TAUBn TIS1 TAUBn TIS0 Functional Description 0 0 Falling edge 0 1 Rising edge 1 0 Detects both of falling and rising edges Selects low width measurement Start trigger Falling edge Stop trigger capture Rising edge 1 1 Detects both of falling and ri...

Page 607: ...y any reset source 7 6 5 4 3 2 1 0 TAUBnCSF TAUBnOVF R R R R R R R R Table 13 128 Description of TAUBnCSRm Register Bit Position Bit Mame Function 1 TAUBnCSF Indicates a count direction 0 Count up 1 Count down The read value of this bit is valid only in the following mode Up down count 0 TAUBnOVF Indicates counter overflow status 0 No overflow occurs 1 Overflow occurs This bit is used only in the ...

Page 608: ...AUBnCLOV R R R R R R R W Table 13 129 Description of TAUBnCSCm Register Bit Position Bit Name Function 0 TAUBnCLOV 0 Invalid Setting 0 does not affect the overflow flag TAUBnCSRm TAUBnOVF 1 Clears overflow flag TAUBnCSRm TAUBnOVF 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TAUB nTS 15 TAUB nTS 14 TAUB nTS 13 TAUB nTS 12 TAUB nTS 11 TAUB nTS 10 TAUB nTS 09 TAUB nTS 08 TAUB nTS 07 TAUB nTS 06 TAUB nTS 05 ...

Page 609: ... R R R R R R R R Table 13 131 Description of TAUBnTE Register Bit Position Bit Name Function 15 to 0 TAUBnTEm Enables disables the counter operation of channel m 0 Disables counter operation 1 Enables counter operation This bit is set to 1 when trigger input of TAUBnTSSTm synchronous channel start trigger signal is detected or when TAUBnTS TAUBnTSm is set to 1 This bit is set to 0 when TAUBnTT TAU...

Page 610: ...B nTOE 10 TAUB nTOE 09 TAUB nTOE 08 TAUB nTOE 07 TAUB nTOE 06 TAUB nTOE 05 TAUB nTOE 04 TAUB nTOE 03 TAUB nTOE 02 TAUB nTOE 01 TAUB nTOE 00 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Table 13 133 Description of TAUBnTOE Register Bit Position Bit Name Function 15 to 0 TAUBnTOEm Enables disables the independent timer output function 0 Disables the independent timer output functi...

Page 611: ...TAUBn TOC 01 TAUBn TOC 00 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Table 13 135 Description of TAUBnTOC Register Bit Position Bit Name Function 15 to 0 TAUBn TOCm Specifies an output mode 0 Operating mode 1 1 Operating mode 2 As listed below the output mode depends on the setting of TAUBnTOM TAUBnTOMm TOMm TOCm Functional Description 0 0 Toggle mode Toggle operation is condu...

Page 612: ... 1 0 TAUB nTDE 15 TAUB nTDE 14 TAUB nTDE 13 TAUB nTDE 12 TAUB nTDE 11 TAUB nTDE 10 TAUB nTDE 09 TAUB nTDE 08 TAUB nTDE 07 TAUB nTDE 06 TAUB nTDE 05 TAUB nTDE 04 TAUB nTDE 03 TAUB nTDE 02 TAUB nTDE 01 TAUB nTDE 00 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Table 13 136 Description of TAUBnTDE Register Bit Position Bit Name Function 15 to 0 TAUBnTDEm Enables disables the dead ti...

Page 613: ...gister is initialized by any reset source 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TAUB nTDL 15 TAUB nTDL 14 TAUB nTDL 13 TAUB nTDL 12 TAUB nTDL 11 TAUB nTDL 10 TAUB nTDL 09 TAUB nTDL 08 TAUB nTDL 07 TAUB nTDL 06 TAUB nTDL 05 TAUB nTDL 04 TAUB nTDL 03 TAUB nTDL 02 TAUB nTDL 01 TAUB nTDL 00 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Table 13 137 Description of TAUBnTDL Register Bi...

Page 614: ...TAUB nTO 09 TAUB nTO 08 TAUB nTO 07 TAUB nTO 06 TAUB nTO 05 TAUB nTO 04 TAUB nTO 03 TAUB nTO 02 TAUB nTO 01 TAUB nTO 00 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Table 13 138 Description of TAUBnTO Register Bit Position Bit Name Function 15 to 0 TAUBnTOm Specifies reads a TAUBnTTOUTm level 0 Low level 1 High level TAUBnTOm bit is writable when independent channel output funct...

Page 615: ... 12 11 10 9 8 7 6 5 4 3 2 1 0 TAUB nRDE 15 TAUB nRDE 14 TAUB nRDE 13 TAUB nRDE 12 TAUB nRDE 11 TAUB nRDE 10 TAUB nRDE 09 TAUB nRDE 08 TAUB nRDE 07 TAUB nRDE 06 TAUB nRDE 05 TAUB nRDE 04 TAUB nRDE 03 TAUB nRDE 02 TAUB nRDE 01 TAUB nRDE 00 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Table 13 140 Description of TAUBnRDE Register Bit Position Bit Name Function 15 to 0 TAUBnRDEm Ena...

Page 616: ...DM 06 TAUB nRDM 05 TAUB nRDM 04 TAUB nRDM 03 TAUB nRDM 02 TAUB nRDM 01 TAUB nRDM 00 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Table 13 142 Description of TAUBnRDM Register Bit Position Bit Name Function 15 to 0 TAUBnRDMm Selects the timing for generating a simultaneous rewrite trigger signal 0 When the master channel counter starts to count 1 At the peak of cycle of triangula...

Page 617: ...DT 13 TAUB nRDT 12 TAUB nRDT 11 TAUB nRDT 10 TAUB nRDT 09 TAUB nRDT 08 TAUB nRDT 07 TAUB nRDT 06 TAUB nRDT 05 TAUB nRDT 04 TAUB nRDT 03 TAUB nRDT 02 TAUB nRDT 01 TAUB nRDT 00 W W W W W W W W W W W W W W W W Table 13 144 Description of TAUBnRDT Register Bit Position Bit Name Function 15 to 0 TAUBnRDTm Triggers a simultaneous rewrite pending state 0 Invalid Setting 0 does not trigger the simultaneou...

Page 618: ...8 7 6 5 4 3 2 1 0 TAUB nRSF 15 TAUB nRSF 14 TAUB nRSF 13 TAUB nRSF 12 TAUB nRSF 11 TAUB nRSF 10 TAUB nRSF 09 TAUB nRSF 08 TAUB nRSF 07 TAUB nRSF 06 TAUB nRSF 05 TAUB nRSF 04 TAUB nRSF 03 TAUB nRSF 02 TAUB nRSF 01 TAUB nRSF 00 R R R R R R R R R R R R R R R R Table 13 145 Description of TAUBnRSF Register Bit Position Bit Name Function 15 to 0 TAUBnRSFm Indicates simultaneous rewrite status 0 Indicat...

Page 619: ... Throughout this section the individual instances of a timer array unit J is identified by the index n n 0 such as the TAUJn channel output mode register TAUJnTOM Channel index m The timer array unit J has 4 channels Throughout this section the individual channels are identified by the index m m 0 to 3 thus a certain channel is denoted as CHm The even numbered channels m 0 2 are denoted as CHm_eve...

Page 620: ...ected to TAUJ0 PCLK Clock controller Table 14 4 TAUJn Interrupt and DMA Requests TAUJn Signals Function Connected to INTTAUJ0I0 INTTAUJ0I3 Channels 0 to 3 interrupt Interrupt Controllers INTTAUJ0I0 to INTTAUJ0I3 DMA Controller triggers 19 to 22 Table 14 5 TAUJn I O Signals TAUJ Signal Function Connected to TAUJnTTINm Channel m input Port TAUJnlm TAUJnTTOUTm Channel m output Port TAUJnOm TAUJnTSSTm...

Page 621: ...nd 32 bit data register per channel Independent channel operation Synchronous channel operation master and slave operations Generation of different types of output signals Counter can be triggered by external signals Interrupt generation Caution The timing diagrams shown in this section are operation timing images To the timer input delay time is added For details see Section 14 11 TAUJnTTINm Edge...

Page 622: ...RG CK0 CK1 CK2 CK3 CK3_pre Simultaneous rewrite trigger from master Start trigger from master INT from master INT from upper channel Clock selector Edge detector TINm Count clock selector Trigger selector sel sel CMORm STS2 0 CMORm CCS1 0 CMORm CKS1 0 CMORm TIS1 0 CMORm MD4 0 TSm TTm TOMm TOCm TOLm TOEm TOm TOUTm TO controller INT Controller CNTm 32 bit count register INTm CDRm 32 bit data registe...

Page 623: ...defines the basic operation and features of a channel In synchronous channel operation every channel in the channel group can operate in a different operating mode Examples are capture mode and interval timer mode Channel output mode The channel output mode defines the operation of TAUJnTTOUTm of a single channel independent output operation or all channels in a channel group synchronous output op...

Page 624: ...outputs CK0 to CK2 are derived from PCLK by a configurable prescaler division factor of 20 to 215 The fourth prescaler output CK3 can be adjusted more precisely by an additional division factor that is not a power of 2 Count clock selection For every channel the count clock selector selects which of the following is used as the clock source One of the prescaler outputs CK0 to CK3 selected by the c...

Page 625: ...nation of channels Table 14 6 TAUJ Operation Functions Independent Operation Function Synchronous Operation Function Independent channel operation function Synchronous channel operation function Interval timer function PWM output function TAUJnTTINm input interval timer function Independent channel signal measurement function TAUJnTTINm input pulse interval measurement function TAUJnTTINm input si...

Page 626: ...equency of CK0 to CK3 2 Configure the desired TAUJn function Set the operating mode Set the channel output mode Set any other control bits 3 Enable the counter by setting the TAUJnTS TAUJnTSm bit to 1 The counter starts counting immediately or when an appropriate trigger is detected depending on the bit settings 4 If desired and if possible for the configured function stop the counter or perform a...

Page 627: ...even operating modes One operating mode can be set for each channel It is specified using the TAUJnCMORm TAUJnMD 4 0 bits Note Depending on the operation functions some of the registers and bits have fixed values and the other can be set by the user For the values of registers and bits see the sections of the corresponding operation functions ...

Page 628: ...hannels Only even channels CH0 CH2 can be set as master channels Any channel apart from CH0 can be set as a slave channel Only channels lower than the master channel can be set as slave channels and several slave channels can be set for one master channel Example If CH2 is a master channel CH3 can be set as slave channel If two master channels are used slave channels cannot cross the master Exampl...

Page 629: ...1 Independent channel operation function CH2 Independent channel operation function Channel group 1 operated by CK0 Channel group 2 operated by CK2 The count clock can be set separately for each channel group CH0 Master CH2 Master CH3 Slave CH1 Slave CK0 CK2 TAUJn A channel that operates independently can also be set between the master and slave channels of channel group 1 Its count clock can be s...

Page 630: ...d be set at the same time To simultaneously stop synchronized channels the TAUJnTT TAUJnTTm bits of the channels should be set at the same time Setting 1 in the TAUJnTS TAUJnTSm bits sets the corresponding TAUJnTE TAUJnTEm bits to 1 enabling counting The count start timing of the counter depends on the operating mode 2 Simultaneous start between TAUJ units Counters in different TAUJ units can also...

Page 631: ...TAUJnCDRm and TAUJnTOLm can be written at any time The new value does not affect the counter operation or the output signal until simultaneous rewrite is triggered Simultaneous rewrite can be triggered by the counter on the master channel reaching a certain value The following table shows the settings for simultaneous rewrite TAUJnRDM TAUJnRDMm 0 Table 14 7 Simultaneous Rewrite Settings Method Sim...

Page 632: ...Initial settings TAUJnTS TAUJnTS settings Update the buffer of data register TAUJnCDRn TAUJnTOL TAUJnTOLm Yes No Read simultaneous rewrite pending flag TAUJnRSF TAUJnRSFm Simultaneous rewrite pending flag TAUJnRSF TAUJnRSFm 0 Write TAUJnCDRn or TAUJnTOL TAUJnTOLm Write to simultaneous rewrite specification trigger bit TAUJnRDT TAUJnRDTm Simultaneous rewrite pending flag TAUJnRSF TAUJnRSFm becomes ...

Page 633: ...RSFm 1 If enabled simultaneous rewrite is carried out Otherwise simultaneous rewrite is not carried out and the system waits for detection of the next simultaneous rewrite trigger 3 Simultaneous rewrite When the simultaneous rewrite trigger is detected and simultaneous rewrite is enabled TAUJnRSF TAUJnRSFm 1 the current values of the data registers are copied to their buffers These values are then...

Page 634: ...cribed in the following figure Figure 14 5 Simultaneous Rewrite When the Master Channel Starts Restarts to Count Setting CH0 is a master channel used to count down and CH1 represents an arbitrary slave channel Simultaneous rewrite is applied when the master channel starts counting TAUJnTS TSm TAUJnTE TEm TAUJnCNT0 INTTAUJnI0 TAUJnCNT1 INTTAUJnI1 TAUJnTTOUT1 TAUJnTOL TOL1 TAUJnTOL TOL1 buf TAUJnCDR...

Page 635: ...taneous rewrite does not occur because it is disabled TAUJnRSF TAUJnRSFm 0 4 The reload data trigger bit TAUJnRDT TAUJnRDTm is set to 1 which sets the status flag TAUJnRSF TAUJnRSFm 1 enabling simultaneous rewrite 5 Simultaneous rewrite is triggered when CH0 restarts counting because simultaneous rewrite is enabled The TAUJnCDRm value is loaded into the TAUJnCDRm buffer and the TAUJnTOL TAUJnTOLm ...

Page 636: ...s affected by settings of channel m and those of other channels Therefore synchronous channel operation should be selected for all synchronizing channels TAUJnTOM TAUJnTOMm 1 The TAUJnTO TAUJnTOm bit can always be read to determine the current value of TAUJnTTOUTm regardless of whether the pin is controlled by software or operated independently or synchronously Control bits The settings of the con...

Page 637: ...us Rewrite The channel output modes and the channel output control bits are listed in the following table TAUJnTOC TAUJnTOCm 0 Caution1 The combinations not listed in this table are forbidden Caution 2 The bit marked with an x can be set to any value Caution 3 The following bits should not be changed during count operation TAUJnTE TAUJnTEm 1 TAUJnTOE TAUJnTOEm TAUJnTOM TAUJnTOMm TAUJnTOC TAUJnTOCm...

Page 638: ... of the TAUJnTTOUTm output 2 Set channel output mode according to Table 14 8 Channel Output Modes and set the output logic using the TAUJnTOL TAUJnTOLm bit 3 Start the counter TAUJnTS TAUJnTSm 1 Figure 14 6 General Procedure for Specifying a TAUJnTTOUTm Channel Output Mode Hi Z TAUJnTTOUTm TAUJnTO TAUJnTOm 1 Set TAUJnTO TAUJnTOm value Product pin 2 Set operating mode and port 3 Start timer operati...

Page 639: ... modes that are controlled independently by TAUJn signals The control bits used to specify a mode are listed in Table 14 8 Channel Output Modes 1 Independent channel output mode 1 Set reset conditions In this output mode TAUJnTTOUTm toggles when INTTAUJnIm is detected The value of TAUJnTOL TAUJnTOLm is ignored Prerequisites There are no prerequisites other than those shown in Table 14 8 Channel Ou...

Page 640: ...Output Modes 1 Synchronous channel output mode 1 Set reset conditions In this output mode INTTAUJnIm of the master channel serves as the set signal and INTTAUJnIm of the slave channel as the reset signal If INTTAUJnIm of the master channel and INTTAUJnIm of the slave channel are generated at the same time INTTAUJnIm of the slave channel reset signal has priority over INTTAUJnIm set signal of the m...

Page 641: ...n The count start timing described in this section is for your reference Actually the count start timing depends on count clock timing 14 9 1 Interval Timer Mode and Capture Mode The counter starts operating with the next count clock after TAUJnTS TAUJnTSm is set to 1 The value of data register is also loaded when the counter starts Figure 14 7 Start Timing in Interval Timer Mode and Capture Mode ...

Page 642: ...e The value of data register is also loaded when the counter starts The count clock cycles which are unrelated to counter operation start determine the frequency with which all operations take place Figure 14 8 Count Start Timing in Other Operating Modes PCLK Count clock TAUJnTE TAUJnTEm Start trigger detection signal TAUJnCNTm Load value Initial value TAUJnTTINm edge detection signal Start trigge...

Page 643: ... Table 14 9 Effect of TAUJnCMORm TAUJnMD0 Bit on Generation of INTTAUJnIm When Counter Is Triggered Mode TAUJnCMO Rm TAUJn MD0 Bit INTTAUJnIm Generated When Counter Starts Restarts or TAUJnTTINm Input Signal Trigger Is Detected Interval timer mode Capture mode Count capture mode 0 Not generated 1 Generated Capture one count mode Capture gate count mode 0 Not generated One count mode 0 1 Not genera...

Page 644: ...n Timing Caution Figure 14 11 Basic Edge Detection Timing shows an image of operation timing In the actual operation delay time occurs due to noise filter and synchronization circuit between the TAUJnIm pin and TAUJn When the noise filter is used Delay time at the noise filter delay time in edge detection maximum 1 sampling clock When the noise filter is not used Delay time at the synchronization ...

Page 645: ...m is loaded into TAUJnCNTm and the counter starts to count down from this value When the counter reaches 0000 0000H INTTAUJnIm is generated and the TAUJnTTOUTm signal toggles Then the TAUJnCDRm value is loaded in TAUJnCNTm and the counter subsequently continues operation The value of TAUJnCDRm can be rewritten at any time and the changed value of TAUJnCDRm is applied the next time the counter star...

Page 646: ... Figure 14 13 General Timing Diagram of Interval Timer Function TAUJnCNTm TAUJnTO TAUJnTOm TAUJnTRO TAUJnTROm TAUJnCDRm INT Trigger from upper Trigger from upper Start trigger from master Simultaneous rewrite INT from master INT from upper Clock selector Count clock Edge selector Trigger selector Trigger from lower Start and capture trigger Interval timer mode TAUJnTS TAUJnTSm CK3 0 TAUJnTTINm TAU...

Page 647: ... CK0 01 Prescaler output CK1 10 Prescaler output CK2 11 Prescaler output CK3 TAUJnCCS 1 0 00 Sampling clock is used as a count clock TAUJnMAS 0 Unused Set to 0 TAUJnSTS 2 0 000 Counter triggered by software TAUJnCOS 1 0 00 Unused Set to 00 TAUJnMD 4 1 0000 Interval Timer Mode TAUJnMD0 0 INTTAUJnIm is not generated and TAUJnTTOUTm does not toggle at the beginning of operation 1 INTTAUJnIm is genera...

Page 648: ...th the Interval Timer Function Therefore these registers should be set to 0 Table 14 12 Control Bit Settings for Independent Channel Output Mode 1 Bit Name Setting TAUJnTOE TAUJnTOEm 1 Enables independent channel output mode TAUJnTO TAUJnTOm 0 Low level 1 High level TAUJnTOM TAUJnTOMm 0 Independent channel output TAUJnTOC TAUJnTOCm 0 Operating mode 1 Toggle mode if TAUJnTOM TAUJnTOMm 0 TAUJnTOL TA...

Page 649: ...peration is stopped Start operation Set TAUJnTS TAUJnTSm to 1 TAUJnTS TAUJnTSm is a trigger bit which is automatically cleared to 0 TAUJnTE TAUJnTEm is set to 1 and the counter starts TAUJnCDRm value is loaded in TAUJnCNTm When TAUJnCMORm TAUJnMD0 1 INTTAUJnIm is generated and TAUJnTTOUTm toggles During operation The TAUJnCDRm register value can be changed at any time The TAUJnCNTm register can be...

Page 650: ...TAUJnTTOUTm toggling every count clock b TAUJnCDRm 0000 0000H count clock PCLK Figure 14 15 TAUJnCDRm 0000 0000H Count Clock PCLK If TAUJnCDRm 0000 0000H and the count clock PCLK the TAUJnCDRm value is loaded into TAUJnCNTm every PCLK clock meaning that TAUJnCNTm is always 0000 0000H INTTAUJnIm is generated continuously resulting in TAUJnTTOUTm toggling every PCLK clock Count clock Count clock cyc...

Page 651: ...TS TAUJnTSm to 1 d Forced restart Figure 14 17 Forced Restart Operation TAUJnCMORm TAUJnMD0 1 The counter can be forcibly restarted without stopping it first by setting TAUJnTS TAUJnTSm to 1 during operation If the TAUJnCMORm TAUJnMD0 bit is set to 1 the first interrupt after a start or restart is generated a a 1 Operation start Operation start TAUJnCNTm Counter TAUJnCDRm TAUJnTTOUTm INTTAUJnIm b ...

Page 652: ...manner as the interval timer function see Section 14 12 1 Interval Timer Function except that this function is restarted by a valid TAUJnTTINm input edge The type of edge used as the trigger is specified using the TAUJnCMURm TAUJnTIS 1 0 bits Either rising edge falling edge or rising and falling edge can be selected 2 Equations INTTAUJnIm cycle Count clock cycle TAUJnCDRm 1 TAUJnTTOUTm rectangular...

Page 653: ...neral timing diagram INTTAUJnIm is generated at the beginning of operation TAUJnCMORm TAUJnMD0 1 Rising edge detection TAUJnCMURm TAUJnTIS 1 0 01B Figure 14 19 General Timing Diagram of TAUJnTTINm Input Interval Timer Function a 1 a 1 b 1 b 1 TAUJnTS TAUJnTSm TAUJnTE TAUJnTEm TAUJnTTINm TAUJnCNTm TAUJnCDRm INTTAUJnIm TAUJnTTOUTm 0000 0000H ...

Page 654: ...ler output CK3 TAUJnCCS 1 0 00 Sampling clock is used as the count clock TAUJnMAS 0 Unused Set to 0 TAUJnSTS 2 0 001 Valid TAUJnTTINm input edge signal is used as the external start trigger TAUJnCOS 1 0 00 Unused Set to 00 TAUJnMD 4 1 0000 Interval Timer Mode TAUJnMD0 0 INTTAUJnIm is not generated and TAUJnTTOUTm does not toggle at the beginning of operation 1 INTTAUJnIm is generated and TAUJnTTOU...

Page 655: ... Input Interval Timer Function Therefore these registers should be set to 0 Table 14 17 Control Bit Settings for Independent Channel Output Mode 1 Bit Name Setting TAUJnTOE TAUJnTOEm 1 Enables Independent Channel Output Mode TAUJnTO TAUJnTOm 0 Low level 1 High level TAUJnTOM TAUJnTOMm 0 Independent channel output TAUJnTOC TAUJnTOCm 0 Operating mode 1 Toggle mode if TAUJnTOM TAUJnTOMm 0 TAUJnTOL TA...

Page 656: ...rigger bit which is automatically cleared to 0 TAUJnTE TAUJnTEm is set to 1 and the counter starts TAUJnCDRm value is loaded in TAUJnCNTm When TAUJnCMORm TAUJnMD0 1 INTTAUJnIm is generated and TAUJnTTOUTm toggles During operation The values of the TAUJnCMURm TAUJnTIS 1 0 and the TAUJnCDRm register can be changed at any time The TAUJnCNTm register can be read at all times Detection of TAUJnTTINm ed...

Page 657: ...dge by excluding this function to restart the counter Figure 14 20 Counter Triggered by Rising TAUJnTTINm Input Edge TAUJnCMURm TAUJnTIS 1 0 01B TAUJnCMORm TAUJnMD0 1 If a valid TAUJnTTINm input edge is detected an interrupt is generated which causes TAUJnTTOUTm to toggle In this example the valid edge is a rising edge TAUJnCMURm TAUJnTIS 1 0 01B a 1 a 1 b 1 b 1 TAUJnTS TAUJnTSm TAUJnTE TAUJnTEm T...

Page 658: ...alues transferred to TAUJnCDRm and TAUJnCSRm TAUJnOVF respectively depend on the values of TAUJnCMORm TAUJnCOS 1 0 bits When TAUJnCMORm TAUJnCOS 0 1 the overflow bit TAUJnCSRm TAUJnOVF can be cleared only by setting the TAUJnCSCm TAUJnCLOV bit to 1 The combination of the values of TAUJnCDRm and TAUJnCSRm TAUJnOVF can be used to deduce the interval of the TAUJnTTINm signal However if multiple overf...

Page 659: ...nCSRm TAUJnOVF FFFF FFFFH 1 TAUJnCDRm capture value 1 3 Block diagram and general timing diagram Figure 14 21 Block Diagram of TAUJnTTINm Input Pulse Interval Measurement Function INT Trigger from upper channel Trigger from upper channel Start trigger from master Simultaneous rewrite INT from master INT from upper channel Clock selector Count clock Edge selector Trigger selector Trigger from lower...

Page 660: ...Rm TAUJnMD0 0 Falling edge detection TAUJnCMURm TAUJnTIS 1 0 00B When a valid TAUJnTTINm input is detected after an overflow TAUJnCDRm is changed and TAUJnCSRm TAUJnOVF is set to 1 TAUJnCMORm TAUJnCOS 1 0 00B Figure 14 22 General Timing Diagram of TAUJnTTINm Input Pulse Interval Measurement Function TAUJnTS TAUJnTSm TAUJnTE TAUJnTEm TAUJnTTINm TAUJnCNTm TAUJnCDRm INTTAUJnIm TAUJnCSRm TAUJnOVF 0000...

Page 661: ... output CK2 11 Prescaler output CK3 TAUJnCCS 1 0 00 Sampling clock is used as a count clock TAUJnMAS 0 Unused Set to 0 TAUJnSTS 2 0 001 Valid edge of TAUJnTTINm input signal is used as an external capture trigger TAUJnCOS 1 0 See Table 14 20 Effects of an Overflow TAUJnMD 4 1 0010 Capture mode TAUJnMD0 0 INTTAUJnIm is not generated at the beginning of operation 1 INTTAUJnIm is generated at the beg...

Page 662: ...trolled by software d Simultaneous rewrite The simultaneous rewrite registers TAUJnRDE and TAUJnRDM cannot be used with the TAUJnTTINm Input Pulse Interval Measurement Function Therefore these registers should be set to 0 Table 14 23 Simultaneous Rewrite Settings for TAUJnTTINm Input Pulse Interval Measurement Function Bit Name Setting TAUJnRDE TAUJnRDEm 0 Disables simultaneous rewrite TAUJnRDM TA...

Page 663: ...bit which is automatically cleared to 0 TAUJnTE TAUJnTEm is set to 1 and the counter starts TAUJnCNTm is cleared to 0000 0000H When TAUJnCMORm TAUJnMD0 1 INTTAUJnIm is generated During operation Detection of TAUJnTTINm edge The values of the TAUJnCMURm TAUJnTIS 1 0 bits can be changed at any time TAUJnCDRm and TAUJnCSRm registers are readable at any time TAUJnCSCm TAUJnCLOV can be set to 1 TAUJnCS...

Page 664: ...AUJnTTINm input edge with no overflow occurring TAUJnCSRm TAUJnOVF is cleared to 0 b TAUJnCMORm TAUJnCOS 1 0 01B Figure 14 24 TAUJnCMORm TAUJnCOS 1 0 01B TAUJnCMORm TAUJnMD0 0 TAUJnCMURm TAUJnTIS 1 0 00B When an overflow occurs the value of TAUJnCDRm remains unchanged and TAUJnCSRm TAUJnOVF is set to 1 Upon detection of the next valid TAUJnTTINm input edge the value of TAUJnCNTm is loaded into TAU...

Page 665: ...ut edge TAUJnCNTm is reset to 0 but TAUJnCDRm and TAUJnCSRm TAUJnOVF remain unchanged Thus the next valid TAUJnTTINm input edge after an overflow is ignored d TAUJnCMORm TAUJnCOS 1 0 11B Figure 14 26 TAUJnCMORm TAUJnCOS 1 0 11B TAUJnCMORm TAUJnMD0 0 TAUJnCMURm TAUJnTIS 1 0 00B TAUJnTS TAUJnTSm TAUJnTE TAUJnTEm TAUJnTTINm TAUJnCNTm TAUJnCDRm INTTAUJnIm TAUJnCSRm TAUJnOVF FFFF FFFFH 0000 0000H 0000 ...

Page 666: ...m is set to FFFF FFFFH and TAUJnCSRm TAUJnOVF is set to 1 Upon detection of the next valid TAUJnTTINm input edge TAUJnCNTm is reset to 0 but TAUJnCDRm and TAUJnCSRm TAUJnOVF remain unchanged Thus the next valid TAUJnTTINm input edge after the overflow is ignored TAUJnCSRm TAUJnOVF is cleared by setting the TAUJnCSCm TAUJnCLOV bit to 1 ...

Page 667: ...TTINm stop edge is detected it overflows The counter is reset to 0000 0000H and subsequently continues operation The values transferred to TAUJnCDRm and TAUJnCSRm TAUJnOVF respectively depend on the values of TAUJnCMORm TAUJnCOS 1 0 bits When TAUJnCMORm TAUJnCOS 0 1 overflow bit TAUJnCSRm TAUJnOVF can be cleared only by setting TAUJnCSCm TAUJnCLOV to 1 The combination of the values of TAUJnCDRm an...

Page 668: ...detected after an overflow TAUJnCDRm is changed and TAUJnCSRm TAUJnOVF is set to 1 TAUJnCMORm TAUJnCOS 1 0 00B Figure 14 28 General Timing Diagram of TAUJnTTINm Input Signal Width Measurement Function INT Trigger from upper channel Trigger from upper channel Start trigger from master Simultaneous rewrite INT from master INT from upper channel Clock selector Count clock Edge selector Trigger select...

Page 669: ...Prescaler output CK2 11 Prescaler output CK3 TAUJnCCS 1 0 00 Sampling clock is used as a count clock TAUJnMAS 0 Unused Set to 0 TAUJnSTS 2 0 010 Valid edge of TAUJnTTINm input signal is used as an external start trigger and the reverse edge as a stop trigger TAUJnCOS 1 0 See Table 14 25 Effects of Overflow TAUJnMD 4 1 0110 Capture one count mode TAUJnMD0 0 Disables the start trigger during operati...

Page 670: ...controlled by software d Simultaneous rewrite The simultaneous rewrite registers TAUJnRDE and TAUJnRDM cannot be used with the TAUJnTTINm Input Signal Width Measurement Function Therefore these registers should be set to 0 Table 14 28 Simultaneous Rewrite Settings for TAUJnTTINm Input Signal Width Measurement Function Bit Name Setting TAUJnRDE TAUJnRDEm 0 Disables simultaneous rewrite TAUJnRDM TAU...

Page 671: ...S TAUJnTSm to 1 TAUJnTS TAUJnTSm is a trigger bit which is automatically cleared to 0 TAUJnTE TAUJnTEm is set to 1 and TAUJnCNTm awaits TAUJnTTINm start edge detection When TAUJnTTINm start edge is detected TAUJnCNTm starts to count up During operation Detection of TAUJnTTINm edge TAUJnCDRm TAUJnCNTm and TAUJnCSRm registers are readable at any time TAUJnCSC CLOV bit can be set to 1 TAUJnCNTm start...

Page 672: ...AUJnTTINm input edge with no overflow occurring TAUJnCSRm TAUJnOVF is cleared to 0 b TAUJnCMORm TAUJnCOS 1 0 01B Figure 14 30 TAUJnCMORm TAUJnCOS 1 0 01B TAUJnCMORm TAUJnMD0 0 TAUJnCMURm TAUJnTIS 1 0 11B When an overflow occurs the value of TAUJnCDRm remains unchanged and TAUJnCSRm TAUJnOVF is set to 1 Upon detection of the next valid TAUJnTTINm input edge the value of TAUJnCNTm is loaded into TAU...

Page 673: ...ut edge TAUJnCNTm is reset to 0 but TAUJnCDRm and TAUJnCSRm TAUJnOVF remain unchanged Thus the next valid TAUJnTTINm input edge after the overflow is ignored d TAUJnCMORm TAUJnCOS 1 0 11B Figure 14 32 TAUJnCMORm TAUJnCOS 1 0 11B TAUJnCMORm TAUJnMD0 0 TAUJnCMURm TAUJnTIS 1 0 11B TAUJnTS TAUJnTSm TAUJnTE TAUJnTEm TAUJnTTINm TAUJnCNTm TAUJnCDRm INTTAUJnIm TAUJnCSRm TAUJnOVF 0000 0000H FFFF FFFFH 0000...

Page 674: ...m is set to FFFF FFFFH and TAUJnCSRm TAUJnOVF is set to 1 Upon detection of the next valid TAUJnTTINm input edge TAUJnCNTm is reset to 0 but TAUJnCDRm and TAUJnCSRm TAUJnOVF remain unchanged Thus the next valid TAUJnTTINm input edge after the overflow is ignored TAUJnCSRm TAUJnOVF is cleared by setting the TAUJnCSCm TAUJnCLOV bit to 1 ...

Page 675: ...op edge is detected the current TAUJnCNTm value is loaded into TAUJnCDRm and an interrupt INTTAUJnIm is generated The counter stops and retains its value until the next valid TAUJnTTINm input start edge is detected When the next TAUJnTTINm input start edge is detected the counter restarts counting from the stop value When the counter reaches FFFF FFFFH the counter restarts counting from 0000 0000H...

Page 676: ...Figure 14 34 General Timing Diagram of TAUJnTTINm Input Period Count Detection Function INT Trigger from upper channel Trigger from upper channel Start trigger from master Simultaneous rewrite INT from master INT from upper channel Clock selector Count clock Edge selector Trigger selector Trigger from lower channel Start and capture trigger TAUJnCNTm TAUJnTO TAUJnTOm TAUJnTRO TAUJnTROm TAUJnCDRm T...

Page 677: ... 4 1 TAUJn MD0 Table 14 30 TAUJnCMORm Settings for TAUJnTTINm Input Period Count Detection Function Bit Name Setting TAUJnCKS 1 0 Selects a sampling clock 00 Prescaler output CK0 01 Prescaler output CK1 10 Prescaler output CK2 11 Prescaler output CK3 TAUJnCCS 1 0 00 Sampling clock is used as a count clock TAUJnMAS 0 Unused Set to 0 TAUJnSTS 2 0 010 Valid edge of the TAUJnTTINm input signal is used...

Page 678: ...is automatically cleared to 0 Detection of TAUJnTTINm start edge TAUJnTE TAUJnTEm is set to 1 and TAUJnCNTm awaits TAUJnTTINm start edge detection When TAUJnTTINm start edge is detected TAUJnCNTm is cleared to 0000 0000H and starts to count up During operation Detection of TAUJnTTINm edge TAUJnCDRm TAUJnCNTm and TAUJnCSRm registers are readable at any time When a TAUJnTTINm start edge rising edge ...

Page 679: ... The counter can be stopped by setting TAUJnTT TAUJnTTm to 1 This sets TAUJnTE TAUJnTEm to 0 TAUJnCNTm stops and retains the current value If the counter is stopped valid TAUJnTTINm input edges are ignored The counter can be restarted by setting TAUJnTS TAUJnTSm to 1 TAUJnCNTm restarts counting from 0000 0000H TAUJnTS TAUJnTSm TAUJnTE TAUJnTEm TAUJnTT TAUJnTTm TAUJnTTINm TAUJnCNTm TAUJnCDRm INTTAU...

Page 680: ...the channel trigger bit TAUJnTS TAUJnTSm to 1 This in turn sets TAUJnTE TAUJnTEm 1 enabling count operation The counter starts to count from 0000 0000H When a valid TAUJnTTINm input edge is detected the current TAUJnCNTm value is loaded into TAUJnCDRm and an interrupt INTTAUJnIm is generated The count operation continues When the counter reaches FFFF FFFFH the counter restarts from 0000 0000H Cond...

Page 681: ...CMURm TAUJnTIS 1 0 00B Figure 14 37 General Timing Diagram of TAUJnTTINm Input Position Detection Function INT Trigger from upper channel Trigger from upper channel Start trigger from master Simultaneous rewrite INT from master INT from upper channel Clock selector Count clock Edge selector Trigger selector Trigger from lower channel Start and capture trigger TAUJnCNTm TAUJnTO TAUJnTOm TAUJnTRO TA...

Page 682: ...S 1 0 TAUJnMD 4 1 TAUJn MD0 Table 14 34 TAUJnCMORm Settings for TAUJnTTINm Input Position Detection Function Bit Name Setting TAUJnCKS 1 0 Selects a sampling clock 00 Prescaler output CK0 01 Prescaler output CK1 10 Prescaler output CK2 11 Prescaler output CK3 TAUJnCCS 1 0 00 Sampling clock is used as a count clock TAUJnMAS 0 Unused Set to 0 TAUJnSTS 2 0 001 Valid edge of the TAUJnTTINm input signa...

Page 683: ...ection Function TAUJnCDRm register operates as a capture register Channel operation is stopped Start operation Set TAUJnTS TAUJnTSm to 1 TAUJnTS TAUJnTSm is a trigger bit which is automatically cleared to 0 TAUJnTE TAUJnTEm is set to 1 and the counter is started When TAUJnCMORm TAUJnMD0 is set to 1 INTTAUJnlm is generated During operation The TAUJnCMURm TAUJnTIS 1 0 bits are changeable at any time...

Page 684: ...be stopped by setting TAUJnTT TAUJnTTm to 1 which in turn sets TAUJnTE TAUJnTEm to 0 TAUJnCNTm stops and retains the current value If the counter is stopped valid TAUJnTTINm input edges are ignored The counter can be restarted by setting TAUJnTS TAUJnTSm to 1 TAUJnCNTm restarts counting from 0000 0000H Operation start Operation start Operation stop TAUJnTS TAUJnTSm TAUJnTE TAUJnTEm TAUJnTT TAUJnTT...

Page 685: ... Section 14 Timer Array Unit J TAUJ 14 13 Synchronous Channel Functions This section describes about the PWM output function which generates PWM signals at a regular interval For the overview of the synchronous channel operation see Section 14 3 Functional Description ...

Page 686: ...e of TAUJnCDRm is loaded into TAUJnCNTm and the counters start to count down from these values PWM output is implemented by generating INTTAUJnIm on the master channel and setting resetting TAUJnTTOUTm slave Master channel When the counter of the master channel reaches 0000 0000H and pulse cycle time has elapsed INTTAUJnIm is generated The counter reloads the TAUJnCDRm value and counts down Slave ...

Page 687: ...er from master INT from master INT from master INT from upper channel INT from upper channel Simultaneous rewrite trigger from upper channel Slave Master Trigger from upper channel Trigger from upper chan Trigger from lower channel Trigger from lower channel Count clock Count clock Start and capture trigger Clock selector Clock selector Trigger selector Trigger selector Start and capture trigger S...

Page 688: ... of PWM Output Function Note The interval between the slave channel starting to count and an interrupt being generated is the value of corresponding TAUJnCDRm whereas for the master channel the interval is the corresponding TAUJnCDRm 1 c a 1 a 1 b 1 b 1 c d d Master Slave TAUJnTS TAUJnTSm TAUJnTE TAUJnTEm TAUJnTTOUTm TAUJnCNTm TAUJnCDRm INTTAUJnIm TAUJnTS TAUJnTSm TAUJnTE TAUJnTEm TAUJnTTOUTm TAUJ...

Page 689: ...UJnCKS 1 0 Selects a sampling clock 00 Prescaler output CK0 01 Prescaler output CK1 10 Prescaler output CK2 11 Prescaler output CK3 TAUJnCKS 1 0 bits of master and slave channels should have the same value TAUJnCCS 1 0 00 Sampling clock is used as a count clock TAUJnMAS 1 Channel is a master channel TAUJnSTS 2 0 000 Triggers the counter by software TAUJnCOS 1 0 00 Unused Set to 00 TAUJnMD 4 1 0000...

Page 690: ...on or in independent channel output mode controlled by software d Simultaneous rewrite for master channels Both master and slave channels should have the same simultaneous rewrite settings Table 14 40 Simultaneous Rewrite Settings for Master Channels of PWM Output Function Bit Name Setting TAUJnRDE TAUJnRDEm 1 Enables simultaneous rewrite TAUJnRDM TAUJnRDMm 0 Generates a simultaneous rewrite trigg...

Page 691: ...Setting TAUJnCKS 1 0 Selects a sampling clock 00 Prescaler output CK0 01 Prescaler output CK1 10 Prescaler output CK2 11 Prescaler output CK3 TAUJnCKS 1 0 bits of master and slave channels should have the same value TAUJnCCS 1 0 00 Sampling clock is used as a count clock TAUJnMAS 0 Channel is a slave channel TAUJnSTS 2 0 100 INTTAUJnIm of master channel is a start trigger TAUJnCOS 1 0 00 Unused Se...

Page 692: ...Mode 1 Bit Name Setting TAUJnTOE TAUJnTOEm 1 Enables independent channel output mode TAUJnTO TAUJnTOm 0 Low level 1 High level TAUJnTOM TAUJnTOMm 1 Synchronous channel operation TAUJnTOC TAUJnTOCm 0 Operating mode 1 TAUJnTOL TAUJnTOLm 0 Positive logic 1 Inverted logic Table 14 44 Simultaneous Rewrite Settings for Slave Channels of the PWM Output Function Bit Name Setting TAUJnRDE TAUJnRDEm 1 Enabl...

Page 693: ...ve channels is set to 1 and the counters of master and slave channels are started INTTAUJnlm is generated on the master channel and TAUJnTTOUTm slave is set During operation TAUJnCDRm is changeable at any time TAUJnCNTm and TAUJnRSF TAUJnRSFm is readable at any time TAUJnRDT TAUJnRDTm is changeable during operation TAUJnCNTm of master channel loads TAUJnCDRm value and counts down When the counter ...

Page 694: ...e master channel generates an interrupt INTTAUJnIm 0000 0000H is loaded into TAUJnCNTm slave Therefore TAUJnCNTm slave cannot start to count and TAUJnTTOUTm remains inactive The value of TAUJnCDRm is loaded into TAUJnCNTm slave to generate an interrupt Master Slave TAUJnTS TAUJnTSm TAUJnTE TAUJnTEm TAUJnCNTm TAUJnCDRm INTTAUJnIm TAUJnTS TAUJnTSm TAUJnTE TAUJnTEm TAUJnTTOUTm TAUJnCNTm TAUJnCDRm INT...

Page 695: ...UJnTOLm Slave 0 If the TAUJnCDRm slave value is greater than the TAUJnCDRm master value no interrupt occurs because the counter of the slave channel does not reach 0000 0000H TAUJnTTOUTm remains active a 1 a 1 a 1 a 1 Master Slave TAUJnTS TAUJnTSm TAUJnTE TAUJnTEm TAUJnCNTm TAUJnCDRm INTTAUJnIm TAUJnTS TAUJnTSm TAUJnTE TAUJnTEm TAUJnTTOUTm TAUJnCNTm TAUJnCDRm INTTAUJnIm 0000 0000H 0000 0000H ...

Page 696: ...nd TAUJnTTOUTm of every channel stop and retain their current values No interrupt occurs The counter can be restarted by setting TAUJnTS TAUJnTSm of master and slave channels to 1 TAUJnCDRm value of master and slave channels is loaded into TAUJnCNTm The counter starts to count down from this value b b a 1 a 1 Master Slave Operation start Operation start Operation stop TAUJnTS TAUJnTSm TAUJnTE TAUJ...

Page 697: ...TAUJnCNTm TAUJn_base1 10H m 4H TAUJn channel mode OS register m TAUJnCMORm TAUJn_base0 80H m 4H TAUJn channel mode user register m TAUJnCMURm TAUJn_base1 20H m 4H TAUJn channel status register m TAUJnCSRm TAUJn_base1 30H m 4H TAUJn channel status clear trigger register m TAUJnCSCm TAUJn_base1 40H m 4H TAUJn channel start trigger register TAUJnTS TAUJn_base1 54H TAUJn channel enable status register...

Page 698: ... 4 3 2 1 0 TAUJnPRS3 3 0 TAUJnPRS2 3 0 TAUJnPRS1 3 0 TAUJnPRS0 3 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Table 14 47 Description of TAUJnTPS Register 1 3 Bit Position Bit Name Function 15 to 12 TAUJnPRS3 3 0 Specifies a CK3_PRE clock The CK3_PRE clock is an input clock of the BRG unit which supplies prescaler output CK3 to all channels TAUJnPRS3 3 0 CK3_PRE clock 0000B PC...

Page 699: ...1111B PCLK 215 The above bits are rewritable only when all the counters using CK2 are stopped TAUJnTE TAUJnTEm 0 7 to 4 TAUJnPRS1 3 0 Specifies prescaler output CK1 TAUJnPRS1 3 0 Prescaler Output CK1 0000B PCLK 20 0001B PCLK 21 0010B PCLK 22 0011B PCLK 23 0100B PCLK 24 0101B PCLK 25 0110B PCLK 26 0111B PCLK 27 1000B PCLK 28 1001B PCLK 29 1010B PCLK 210 1011B PCLK 211 1100B PCLK 212 1101B PCLK 213 ...

Page 700: ...LK 20 0001B PCLK 21 0010B PCLK 22 0011B PCLK 23 0100B PCLK 24 0101B PCLK 25 0110B PCLK 26 0111B PCLK 27 1000B PCLK 28 1001B PCLK 29 1010B PCLK 210 1011B PCLK 211 1100B PCLK 212 1101B PCLK 213 1110B PCLK 214 1111B PCLK 215 The above bits are rewritable only when all the counters using CK0 are stopped TAUJnTE TAUJnTEm 0 Table 14 47 Description of TAUJnTPS Register 3 3 Bit Position Bit Name Function ...

Page 701: ...ied in TAUJnTPS PRS3 3 0 Access Readable writable in 8 bit units Address TAUJn_base0 94H Initial value 00H Any reset source triggers initialization 7 6 5 4 3 2 1 0 TAUJnBRS 07 00 R W R W R W R W R W R W R W R W Table 14 48 Description of TAUJnBRS Register Bit Position Bit Name Function 7 to 0 TAUJnBRS 07 00 Specifies a CK3_PRE clock division factor for generating prescaler output CK3 TAUJnBRS 07 0...

Page 702: ...units Readable in capture mode Any write operation is ignored Readable writable in compare mode Address TAUJn_base1 m 4H Initial value 0000 0000H Any reset source triggers initialization 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TAUJnCDR 31 16 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TAUJnCDR 15 0 R W R W R W R W R W R W R W R W R ...

Page 703: ... value The initial counter read value depends on the operating mode and how the counter is stopped By a reset By a counter stop trigger TAUJnTT TAUJnTTm 1 The following table lists the initial counter read values after the counter is stopped TAUJnTE TAUJnTEm 0 and re enabled TAUJnTS TAUJnTSm 1 The table also contains the counter read value one count after the counter is enabled TAUJnTS TAUJnTSm 1 ...

Page 704: ... Read Values after Counter Is Re enabled Mode Name Count Method Up Down TAUJnCNTm Value After Changing Operating Mode after Reset After Stop Trigger After One Count Interval timer mode Count down FFFF FFFFH Stop value Capture mode Count up 0000 0000H Stop value One count mode Count down FFFF FFFFH Stop value FFFF FFFFH Capture and one count mode Count up 0000 0000H Stop value Capture value 1 TAUJn...

Page 705: ...on Bit Name Function 15 14 TAUJnCKS 1 0 Selects a sampling clock which is used with the TAUJnTTINm input edge detection circuit Setting of TAUJnCMORm TAUJnCCS 1 0 bit also allows the sampling clock to serve as a count clock TAUJn CKS1 TAUJn CKS0 Selection of Sampling Clock 0 0 Prescaler output CK0 0 1 Prescaler output CK1 1 0 Prescaler output CK2 1 1 Prescaler output CK3 13 12 TAUJnCCS 1 0 Selects...

Page 706: ...iption 0 0 0 Software trigger 0 0 1 Valid edge of TAUJnTTINm input signal which is specified by TAUJnCMURm TAUJnTIS 1 0 0 1 0 Valid edge of TAUJnTTINm input signal is used as a start trigger and the reverse edge as a stop trigger 0 1 1 Setting prohibited 1 0 0 INTTAUJnlm of master channel 1 0 1 Setting prohibited 1 1 0 1 1 1 Table 14 52 Description of TAUJnCMORm Register 2 4 Bit Position Bit Name ...

Page 707: ...has occurred since the last valid edge was detected Clear TAUJnCSRm TAUJnOVF if no counter overflow has occurred since the last valid edge was detected 0 1 Set when a counter overflow occurs and cleared by setting TAUJnCSCm TAUJnCLOV to 1 1 0 Updated when valid edge of TAUJnTTINm input is detected and when a counter overflow occurs Detection of valid edge of TAUJnTTINm input The counter value is w...

Page 708: ...prohibited 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 0 Count capture mode 1 1 0 0 1 0 Setting prohibited 1 1 0 1 0 Capture and gate count mode Mode Role of TAUJnMD0 Bit Interval timer mode Capture mode Count capture mode Specifies whether an INTTAUJnlm signal is generated or not at the beginning of count operation at the input of start trigger 0 INTTAUJnlm is not generated 1 INTTAUJnlm is generated One co...

Page 709: ...W Table 14 53 Description of TAUJnCMURm Register Bit Position Bit Name Function 1 0 TAUJnTIS 1 0 Specifies a valid edge of TAUJnTTINm input signal TAUJn TIS1 TAUJn TIS0 Functional Description 0 0 Falling edge 0 1 Rising edge 1 0 Detection of falling and rising edges selection of low width measurement Start trigger Falling edge Stop trigger capture Rising edge 1 1 Detection of falling and rising ed...

Page 710: ...se1 30H m 4H Initial value 00H Any reset source triggers initialization 7 6 5 4 3 2 1 0 TAUJnOVF R R R R R R R R Table 14 54 Description of TAUJnCSRm Register Bit Position Bit Name Function 0 TAUJn OVF Indicates the counter overflow status 0 No overflow occurs 1 Overflow occurs This bit is used only in the following modes Capture mode Capture and one count mode The function of this bit depends on ...

Page 711: ...ization 7 6 5 4 3 2 1 0 0 TAUJnCLOV R R R R R R R W Table 14 55 Description of TAUJnCSCm Register Bit Position Bit Name Function 0 TAUJnCLOV Controls a clear operation of the overflow flag TAUJnCSRm TAUJnOVF of channel m 0 No effect writing 0 to the bit does not affect the overflow flag i e the TAUJnCSRm TAUJnOVF bit 1 Clears the overflow flag TAUJnCSRm TAUJnOVF 7 6 5 4 3 2 1 0 TAUJnTS 03 TAUJnTS ...

Page 712: ...iption of TAUJnTE Register Bit Position Bit Name Function 3 to 0 TAUJnTEm Enables disables channel m s counter operation 0 Disables the counter operation 1 Enables the counter operation This bit is set to 1 when trigger input of TAUJnTSSTm synchronous channel start trigger signal is detected or when TAUJnTS TAUJnTSm is set to 1 This bit is set to 0 when TAUJnTT TAUJnTTm is set to 1 7 6 5 4 3 2 1 0...

Page 713: ...ly while the counter is stopped TAUJnTE TAUJnTEm 0 Address TAUJn_base0 98H Initial value 00H Any reset source triggers initialization 7 6 5 4 3 2 1 0 TAUJnTOE 03 TAUJnTOE 02 TAUJnTOE 01 TAUJnTOE 00 R W R W R W R W R W R W R W R W Table 14 59 Description of TAUJnTOE Register Bit Position Bit Name Function 3 to 0 TAUJnTOEm Enables disables the independent timer output function 0 Disables the indepen...

Page 714: ...cess Readable writable in 8 bit units Writable only while the counter is stopped TAUJnTE TAUJnTEm 0 Address TAUJn_base0 9CH Initial value 00H Any reset source triggers initialization 7 6 5 4 3 2 1 0 TAUJnTOC 03 TAUJnTOC 02 TAUJnTOC 01 TAUJnTOC 00 R W R W R W R W R W R W R W R W Table 14 61 Description of TAUJnTOC Register Bit Position Bit Name Function 3 0 TAUJn TOCm Specifies output mode 0 Operat...

Page 715: ...ble writable in 8 bit units Address TAUJn_base1 64H Initial value 00H Any reset source triggers initialization 7 6 5 4 3 2 1 0 TAUJnTO 03 TAUJnTO 02 TAUJnTO 01 TAUJnTO 00 R W R W R W R W R W R W R W R W Table 14 62 Description of TAUJnTO Register Bit Position Bit Name Function 3 to 0 TAUJnTOm Specifies and reads a TAUJnTTOUTm level 0 Low level 1 High level The TAUJnTOm bit is writable when TAUJnTO...

Page 716: ...itable only while the counter is stopped TAUJnTE TAUJnTEm 0 Address TAUJn_base0 A4H Initial value 00H Any reset source triggers initialization 7 6 5 4 3 2 1 0 TAUJnRDE 03 TAUJnRDE 02 TAUJnRDE 01 TAUJnRDE 00 R W R W R W R W R W R W R W R W Table 14 64 Description of TAUJnRDE Register Bit Position Bit Name Function 3 to 0 TAUJnRDEm Enables disables simultaneous rewrite of the data register of channe...

Page 717: ...Table 14 66 Description of TAUJnRDT Register Bit Position Bit Name Function 3 to 0 TAUJnRDTm Triggers a simultaneous rewrite pending state 0 No effect writing 0 to the bit does not also act as the trigger for entry to the rewrite pending state 1 Triggers a simultaneous rewrite pending state The simultaneous rewrite pending flag TAUJnRSFm is set to 1 The system waits for a simultaneous rewrite trig...

Page 718: ...the PCLK clock signal input I O signals The I O signals of the TSG2 are listed in Table 15 4 Table 15 1 TSG2 Channels TSG2 Number of instance 1 Name TSG20 Table 15 2 TSG2 Register Base Addresses TSG2n TSG2n_base0 Address TSG2n_base1 Address TSG20 FF82 E000H FFFF CC00H Table 15 3 TSG2 Clock Supply TSG2n Supplied Clock Connected to TSG20 PCLK Clock controller Table 15 4 List of TSG2 I O Signals TSG2...

Page 719: ...terrupt controller INTTSG2nI05 TSnCMP5 compare match interrupt Interrupt controller INTTSG2nI06 TSnCMP6 compare match interrupt Interrupt controller INTTSG2nI07 TSnCMP7 compare match interrupt Interrupt controller INTTSG2nI08 TSnCMP8 compare match interrupt Interrupt controller INTTSG2nI09 TSnCMP9 compare match interrupt Interrupt controller INTTSG2nI10 TSnCMP10 compare match interrupt Interrupt c...

Page 720: ...unction allows the high impedance control of the TSG2nO1 to TSG2nO6 pin output Compare value setting Reload simultaneous rewrite or anytime rewrite can be selected Reload mode Writing to TSnCMP1 setting the reload request flag TSnRSF enables reload and allows simultaneous transfer of the values of multiple registers Data can be transferred at peak valley peak or valley reload timing Reload request...

Page 721: ...TSnDTC0 TSG2nO1 TSG2nO2 TSG2nO3 TSG2nO4 TSG2nO5 TSG2nO6 INTTSG2nIER INTTSG2nIWN TSG2nO7 TSnADTRG0 1 INTTSG2nIPEK INTTSG2nIVLY TSnDTC1 TSnDTC0BF TSnDTC1BF TSnTT TSnTE TSnCKS TSnCTL5 6 Counter control Timer output control and pattern output control in 120 DC mode software output control U phase control V phase control W phase control Warning detection Reload control Interrupt control A D trigger con...

Page 722: ...s register 0 TSnSTR0 TSG2n_base1 010H TSG2n status register 1 TSnSTR1 TSG2n_base1 014H TSG2n status register 2 TSnSTR2 TSG2n_base1 018H TSG2n status clear trigger register TSnSTC TSG2n_base1 01CH TSG2n option register 0 TSnOPT0 TSG2n_base1 020H TSG2n option register 1 TSnOPT1 TSG2n_base1 024H TSG2n trigger register 0 TSnTRG0 TSG2n_base1 030H TSG2n trigger register 1 TSnTRG1 TSG2n_base1 034H TSG2n ...

Page 723: ...WM U phase compare register TSnCMPU TSG2n_base1 0B0H TSG2n HT PWM V phase compare register TSnCMPV TSG2n_base1 0B4H TSG2n HT PWM W phase compare register TSnCMPW TSG2n_base1 0B8H TSG2n SP PWM U phase active width setting register TSnUPW TSG2n_base1 0BCH TSG2n SP PWM V phase active width setting register TSnVPW TSG2n_base1 0C0H TSG2n SP PWM W phase active width setting register TSnWPW TSG2n_base1 0...

Page 724: ...timer operation TSnSTR0 TSnTE 1 If the different value is written to this register when TSnSTR0 TSnTE 1 timer operation cannot be guaranteed If this register is erroneously rewritten set this register again after stopping the timer 7 6 5 4 3 2 1 0 TSn DWD TSnMD 1 0 R R R R W R R R W R W Table 15 7 TSnCTL0 Register Contents Bit Position Bit Name Function 4 TSnDWD Selects the pulse width for the dia...

Page 725: ...s the flags of TSG2n Access This register can be read written in 16 bit units Address TSG2n_base0 20CH Initial value 0000H This register is initialized by a reset from any source 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TSn TBA2 TSn TBA1 TSn TBA0 TSn PPC TSn PEC TSn TDC TSn NDC TSn PRC TSnPTC 1 0 R R R R R R R W R W R W R W R W R W R W R W R W R W ...

Page 726: ... interrupt INTTSG2nIER is generated 8 TSnTBA1 Enables or disables detection of the simultaneous active states of the TSG2nO3 and TSG2nO4 pins 0 Disables detection of simultaneous active states of the TSG2nO3 and TSG2nO4 pins 1 Enables detection of simultaneous active states of the TSG2nO3 and TSG2nO4 pins If the simultaneous active state is detected when the TSnIOC1 TSnEOC bit and TSnTBA1 bit are ...

Page 727: ... the TSnOPCI0 and TSnOPCI1 signals 3 TSnNDC Enables or disables detection of the noise generation two or more pins change simultaneously TSnSTR2 TSnNDF on the TSG2nPTSI2 to TSG2nPTSI0 pins 0 Disables detection of the noise generation on the TSG2nPTSI2 to TSG2nPTSI0 pins 1 Enables detection of the noise generation on the TSG2nPTSI2 to TSG2nPTSI0 pins 2 TSnPRC Enables or disables detection of the re...

Page 728: ... set to peak reload timing set by TSnCTL4 TSnPRE and valley reload timing set by TSnCTL4 TSnVRE 1 The reload timing is set to peak interrupt timing and valley interrupt timing The setting of this bit is valid in reload mode TSnRMC 0 0 TSnRMC Selects the transfer timing of the compare register values 0 Reload mode simultaneous rewrite Writing to TSnCMP1 TSnCMP1W TSnCMPU TSnUPW enables reloading and...

Page 729: ...r timing of the 16 bit counter by compare match in any mode other than HT PWM mode When the reload operation at the peak timing of the 16 bit counter is disabled TSnPRE 0 reload is not executed in any mode other than HT PWM mode 7 TSnVRE Enables or disables the valley reload timing 0 Disables reload operation at the valley timing of the 16 bit counter 1 Enables reload operation at the valley timin...

Page 730: ... rate of the interrupts INTTSG2nIPEK and INTTSG2nIVLY and reload TSnRCC04 TSnRCC03 TSnRCC02 TSnRCC01 TSnRCC00 Skipping Rate 0 0 0 0 0 None 0 0 0 0 1 1 2 0 0 0 1 0 1 3 0 0 0 1 1 1 4 1 1 1 0 1 1 30 1 1 1 1 0 1 31 1 1 1 1 1 1 32 When a write access is made including a write of the same value to TSnRCC04 to TSnRCC00 to TSnCTL4 during timer operation TSnSTR0 TSnTE 1 the interrupt skipping counter is cl...

Page 731: ...TRG0 at the peak timing when the 16 bit sub counter switches from incrementing to decrementing 0 Disables generation of the A D conversion trigger at the peak timing of the 16 bit sub counter 1 Enables generation of the A D conversion trigger at the peak timing of the 16 bit sub counter The TSnAT09 bit can be set to 1 only in HT PWM mode In other modes the TSnAT09 bit should be set to 0 Do not set...

Page 732: ...D conversion trigger TSnADTRG0 at the match timing of the 16 bit counter value during incrementation with the TSnDCMP1 value 0 Disables generation of the A D conversion trigger at the match timing of the 16 bit counter value during incrementation with the TSnDCMP1 1 Enables generation of the A D conversion trigger at the match timing of the 16 bit counter value during incrementation with the TSnDC...

Page 733: ...crementing to incrementing 0 Disables generation of the A D conversion trigger at the timing of a valley interrupt INTTSG2nIVLY after being skipped 1 Enables generation of the A D conversion trigger at the timing of a valley interrupt INTTSG2nIVLY after being skipped This bit can be set to 1 only in HT PWM mode In other modes this bit should be set to 0 Table 15 11 TSnCTL5 Register Contents 3 3 Bi...

Page 734: ...1 at the peak timing when the 16 bit sub counter switches from incrementing to decrementing 0 Disables generation of the A D conversion trigger at the peak timing of the 16 bit sub counter 1 Enables generation of the A D conversion trigger at the peak timing of the 16 bit sub counter The TSnAT19 bit can be set to 1 only in HT PWM mode In other modes the TSnAT19 bit should be set to 0 Do not set th...

Page 735: ...e TSnDCMP1 value 1 Enables generation of the A D conversion trigger at the match timing of the 16 bit counter value during incrementation with the TSnDCMP1 value 3 TSnAT13 Specifies generation of A D conversion trigger TSnADTRG1 at the match timing of the 16 bit counter value during defragmentation with the TSnDCMP0 value 0 Disables generation of the A D conversion trigger at the match timing of t...

Page 736: ...alue can be written during timer operation TSnSTR0 TSnTE 1 If the different value is written to this register when TSnSTR0 TSnTE 1 timer operation cannot be guaranteed If this register is erroneously rewritten set this register again after stopping the timer 7 6 5 4 3 2 1 0 TSn TOE6 TSn TOE5 TSn TOE4 TSn TOE3 TSn TOE2 TSn TOE1 R R W R W R W R W R W R W R Table 15 13 TSnIOC0 Register Contents Bit P...

Page 737: ... Bit Position Bit Name Function 4 TSnPTS Enables or disables output of the edge detection signal TSnPTE of TSG2nPTSI0 to TSG2nPTSI2 and two phase encoder count signal TSnPEC 0 Disables output of the toggle signal by edge detection of TSG2nPTSI0 to TSG2nPTSI2 1 Enables output of the toggle signal by edge detection of TSG2nPTSI0 to TSG2nPTSI2 When TSnPTS is changed from 1 to 0 the levels of the TSnP...

Page 738: ... stopping the timer Table 15 14 TSnIOC1 Register Contents 2 2 Bit Position Bit Name Function 1 TSnTGS Selects the A D conversion trigger diagnostic output TSG2nO7 signal 0 Selects A D conversion trigger output 1 Selects diagnostic output 0 TSnTOS Selects the timer counter increment decrement status output TSG2nO0 signal 0 Outputs the up down count flag of the 16 bit counter 1 Outputs the up down c...

Page 739: ...tten when TSnIOC0 TSnTOEm 0 m 1 to 6 Note When TSG2nOm control is enabled TSnIOC0 TSnTOEm 0 by writing a new value to TSnIOC2 while the timer is stopped TSnSTR0 TSnTE 0 a desired level can be output on TSG2nOm by setting TSnOLm and TSnTOm in TSnIOC2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TSn OL6 TSn OL5 TSn OL4 TSn OL3 TSn OL2 TSn OL1 TSn TO6 TSn TO5 TSn TO4 TSn TO3 TSn TO2 TSn TO1 R R W R W R W R ...

Page 740: ...d be set to 0 in HT PWM mode 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TSn TOL6 TSn TOL5 TSn TOL4 TSn TOL3 TSn TOL2 TSn TOL1 R R R R R R R R R R W R W R W R W R W R W R Table 15 16 TSnIOC3 Register Contents Bit Position Bit Name Function 6 to 1 TSnTOL6 to TSnTOL1 Controls the set clear level of output 0 Outputs the normal ...

Page 741: ...nt direction of the 16 bit sub counter 0 The 16 bit sub counter is incremented 1 The 16 bit sub counter is decremented TSnSUF detects counting of the 16 bit sub counter from 0000H to TSnCMP0 value 0002H as up counting and counting from the TSnCMP0 value to 0002H as down counting This bit is valid only in HT PWM mode 1 TSnRSF Indicates whether there is a reload request 0 No reload request or reload...

Page 742: ...cates the pattern change order of TSG2nPTSI0 to TSG2nPTSI2 0 Indicates that patterns are input to TSG2nPTSI0 to TSG2nPTSI2 in the normal rotation pattern order 1 Indicates that patterns are input to TSG2nPTSI0 to TSG2nPTSI2 in the reverse rotation pattern order Normal Rotation Reverse Rotation TSG2nPTSI2 to TSG2nPTSI0 1 0 1 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 Normal or reverse rotation can be detected f...

Page 743: ...TSnSTC TSnTBR2 The simultaneous active state is not detected when TSnTBA2 0 8 TSnTBF1 Indicates whether the simultaneous active state of the positive phase and inverse phase is detected when TSnCTL1 TSnTBA1 is 1 0 Positive phase TSG2nO3 and inverse phase TSG2nO4 are not active simultaneously 1 Positive phase TSG2nO3 and inverse phase TSG2nO4 are active simultaneously TSnTBF1 is set to 1 when the s...

Page 744: ...TSnOPCI0 and TSnOPCI1 triggers is detected and a warning interrupt INTTSG2nIWN is generated TSnTDF can be cleared by writing 1 to TSnSTC TSnTDR 3 TSnNDF Indicates whether noise on TSG2nPTSI0 to TSG2nPTSI2 is detected 0 Noise on TSG2nPTSI0 to TSG2nPTSI2 due to simultaneous change of two or more pins not detected 1 Noise on TSG2nPTSI0 to TSG2nPTSI2 due to simultaneous change of two or more pins dete...

Page 745: ...SnTBF1 When TSnTBR1 writing and TSnSTR2 TSnTBF1 setting occur simultaneously TSnSTR2 TSnTBF1 setting has a priority and the flag is not cleared 7 TSnTBR0 This is a trigger bit that clears TSnSTR2 TSnTBF0 0 Does not clear TSnTBF0 1 Clears TSnTBF0 When TSnTBR0 writing and TSnSTR2 TSnTBF0 setting occur simultaneously TSnSTR2 TSnTBF0 setting has a priority and the flag is not cleared 6 TSnPPR This is ...

Page 746: ...RR This is a trigger bit that clears TSnSTR2 TSnPRF 0 Does not clear TSnPRF 1 Clears TSnPRF When TSnPRR writing and TSnSTR2 TSnPRF setting occur simultaneously TSnSTR2 TSnPRF setting has a priority and the flag is not cleared 1 TSnPTR This is a trigger bit that clears TSnSTR2 TSnPTF 0 Does not clear TSnPTF 1 Clears TSnPTF When TSnPTR writing and TSnSTR2 TSnPTF setting occur simultaneously TSnSTR2 ...

Page 747: ...isables the TSG2nPTSI0 to TSG2nPTSI2 and TSnOPCI0 and TSnOPCI1 inputs 1 Enables TSG2nPTSI0 to TSG2nPTSI2 and TSnOPCI0 and TSnOPCI1 inputs The pattern output trigger is selected by TSnPOT TSnSTE is valid in 120 DC mode and when software output control function is enabled 4 TSnPOT Selects the pattern output trigger 0 Switches the output pattern by the external pattern input pins TSG2nPTSI0 to TSG2nP...

Page 748: ...and TSnPSS 1 It is recommended to rewrite TSnPSC when TSnSTR0 TSnTE 0 or TSnPOT 0 If TSnPSC is rewritten when TSnPOT 1 the unexpected timer output pattern might be caused If the signal input to TSG2nPTSI0 to TSG2nPTSI2 changes with TSG2n operation being stopped TSnSTR0 TSnTE 0 the TSnTRG0 TSnTS bit should be set to 1 after matching the input signal change logic with the TSnPSC order For output ord...

Page 749: ... TSG2n_base1 024H Initial value 00H This register is initialized by a reset from any source 7 6 5 4 3 2 1 0 TSnSPC 2 0 R R R R R R W R W R W Table 15 22 TSnOPT1 Register Contents Bit Position Bit Name Function 2 to 0 TSnSPC 2 0 Specifies the timer output pattern when software output function is enabled and in 120 DC mode For the output pattern see Section 15 11 5 Software Output Control Function a...

Page 750: ...written in 8 bit units Address TSG2n_base1 030H Initial value 00H This register is initialized by a reset from any source 7 6 5 4 3 2 1 0 TSn TS R R R R R R R W Table 15 23 TSnTRG0 Register Contents Bit Position Bit Name Function 0 TSnTS This bit is a trigger bit that controls the start of the timer 0 The timer is not started 1 The timer is started restarted TSnSTR0 TSnTE 1 This bit is always read...

Page 751: ...nly be written in 8 bit units Address TSG2n_base1 034H Initial value 00H This register is initialized by a reset from any source 7 6 5 4 3 2 1 0 TSn TT R R R R R R R W Table 15 24 TSnTRG1 Register Contents Bit Position Bit Name Function 0 TSnTT This is a trigger bit that controls the stop of the timer 0 The timer is not stopped 1 The timer is stopped TSnSTR0 TSnTE 0 This bit is always read as 0 ...

Page 752: ... bit counter value can be read In HT PWM mode the 16 bit counter provides the triangle wave control in which the counter value is incremented and decremented by 2 Bit 0 is always read as 0 In other modes the 16 bit counter provides the sawtooth wave control in which the counter value is incremented by 1 Note Use with the set value of TSnDTC0 TSnCMP0 FFFFH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 16 b...

Page 753: ...er register from which the 16 bit sub counter value can be read In HT PWM mode the 16 bit sub counter provides the triangle wave control in which the counter value is incremented and decremented by 2 Bit 0 is always read as 0 This register can be used only in HT PWM mode Note Use with the set value of TSnDTC0 TSnDTC1 TSnCMP0 FFFFH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 16 bit sub counter R R R R R ...

Page 754: ...r is initialized by a reset from any source Note In HT PWM mode the LSB is ignored 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 16 bit compare register R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Table 15 27 TSnCMP0 Register Setting Operating Mode PWM Period Minimum Value Period Maximum Value Period HT PWM...

Page 755: ...ter R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TSnCMP1 16 bit compare register R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Table 15 28 TSnCMP1W Register Setting Operating Mode TSnCMP1 TSnCMP2 Minimum Value Maximum Value PWM mode TSG2nO1 clear timing TSG2nO1 set timing 0000H TSnCMP0 1 TSnCMP0 FFFFH or FFFFH HT PWM mode T...

Page 756: ...1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TSnCMP4 16 bit compare register R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TSnCMP3 16 bit compare register R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Table 15 29 TSnCMP3W Register Setting Operating Mode TSnCMP3 TSnCMP4 Minimum Value Maximum Value PWM mode TSG2nO2 clear ...

Page 757: ...r R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TSnCMP5 16 bit compare register R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Table 15 30 TSnCMP5W Register Setting Operating Mode TSnCMP5 TSnCMP6 Minimum Value Maximum Value PWM mode TSG2nO3 clear timing TSG2nO3 set timing 0000H TSnCMP0 1 TSnCMP0 FFFFH or FFFFH HT PWM mode TSG...

Page 758: ...1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TSnCMP8 16 bit compare register R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TSnCMP7 16 bit compare register R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Table 15 31 TSnCMP7W Register Setting Operating Mode TSnCMP7 TSnCMP8 Minimum Value Maximum Value PWM mode TSG2nO4 clear ...

Page 759: ...ter R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TSnCMP9 16 bit compare register R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Table 15 32 TSnCMP9W Register Setting Operating Mode TSnCMP9 TSnCMP10 Minimum Value Maximum Value PWM mode TSG2nO5 clear timing TSG2nO5 set timing 0000H TSnCMP0 1 TSnCMP0 FFFFH or FFFFH HT PWM mode ...

Page 760: ...1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TSnCMP12 16 bit compare register R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TSnCMP11 16 bit compare register R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Table 15 33 TSnCMP11W Register Setting Operating Mode TSnCMP11 TSnCMP12 Minimum Value Maximum Value PWM mode TSG2nO6 clea...

Page 761: ...nCMP7 TSG2n_base1 0A0H TSnCMP8 TSG2n_base1 0A4H TSnCMP9 TSG2n_base1 090H TSnCMP10 TSG2n_base1 094H TSnCMP11 TSG2n_base1 0A8H TSnCMP12 TSG2n_base1 0ACH Initial value 0000H This register is initialized by a reset from any source The function of this register is the same as the function of the corresponding registers with the same name in TSnCMP1W TSnCMP3W TSnCMP5W TSnCMP7W TSnCMP9W and TSnCMP11W Whe...

Page 762: ...tialized by a reset from any source Setting of this register is used to control the diagnostic output or A D conversion trigger timing in all the modes A pulse is generated by a match of this register value with the 16 bit counter value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TSnDCMP1 16 bit compare register R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 15 14 13 12 11 10 ...

Page 763: ... 00000000H This register is initialized by a reset from any source Setting of this register is used to control the diagnostic output or A D conversion trigger timing in all the modes A pulse is generated by a match of this register value with the 16 bit counter value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TSnDCMP2 16 bi...

Page 764: ...ls UT VT WT output in 120 DC mode m 0 1 2 3 4 5 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PAT5T R R R R R R R R R R R R R R R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PAT5T PAT4T PAT3T PAT2T PAT1T PAT0T R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Table 15 34 TSnPAT0W Set Value and Output Control PATmT value Output Control 000 Fixed to low 001 PWM output set by TSnCMP1 ...

Page 765: ...s UB VB WB output in 120 DC mode m 0 1 2 3 4 5 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PAT5B R R R R R R R R R R R R R R R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PAT5B PAT4B PAT3B PAT2B PAT1B PAT0B R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Table 15 35 TSnPAT1W Set Value and Output Control PATmB value Output Control 000 Fixed to low 001 PWM output set by TSnCMP3 0...

Page 766: ...nitialized by a reset from any source To rewrite TSnDTC0W 0 9 set bit 14 to bit 0 and TSnDTCM to 0 in TSnDTPR and rewrite the TSnDTC0W At this time when the rewritten value of TSnDTC0W 30 16 and the TSnDTPR value match TSnDTC0W is rewritten During timer operation TSnSTR0 TSnTE 1 rewriting should be performed in reload mode TSnCTL3 TSnRMC 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Write prot...

Page 767: ...ialized by a reset from any source To rewrite TSnDTC1W 0 9 set bit 30 to bit 16 and TSnDTCM to 0 in TSnDTPR and rewrite the TSnDTC1W At this time when the rewritten value of TSnDTC1W 30 16 and the TSnDTPR value match TSnDTC1W is rewritten During timer operation TSnSTR0 TSnTE 1 rewriting should be performed in reload mode TSnCTL3 TSnRMC 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Write protec...

Page 768: ...tually read 36 TSG2n HT PWM V Phase Compare Register TSnCMPV This register sets the compare value for V phase in HT PWM mode Access This register can be read written in 16 bit units Address TSG2n_base1 0B4H Initial value 0000H This register is initialized by a reset from any source Note 1 This register can be used only in HT PWM mode Note 2 The TSnCMPV set value is indicated on TSnCMP5W TSnCMP5 TS...

Page 769: ...n in 16 bit units Address TSG2n_base1 0B8H Initial value 0000H This register is initialized by a reset from any source Note 1 This register can be used only in HT PWM mode Note 2 The TSnCMPW set value is indicated on TSnCMP9W TSnCMP9 TSnCMP10 Note 3 When the TSnCMPW is read the TSnCMP9 value is actually read 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TSnCMPW 16 bit compare register R W R W R W R W R W ...

Page 770: ...ctually read 39 TSG2n SP PWM V Phase Active Width Setting Register TSnVPW This register sets the active width for V phase in SP PWM mode Access This register can be read written in 16 bit units Address TSG2n_base1 0C0H Initial value 0000H This register is initialized by a reset from any source Note 1 This register can be used only in SP PWM mode Note 2 The sum of the TSnVPW set value and the TSnCM...

Page 771: ...n 16 bit units Address TSG2n_base1 0C4H Initial value 0000H This register is initialized by a reset from any source Note 1 This register can be used only in SP PWM mode Note 2 The sum of the TSnWPW set value and the TSnCMP10 set value is indicated on TSnCMP9 Note 3 When the TSnWPW is read the TSnCMP9 value is actually read 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TSnWPW 16 bit compare register R W R ...

Page 772: ...TSnDTC1 and the write protection code of TSnDTPR and the TSnDTCM setting Caution This register should be set when the timer is stopped TSnSTR0 TSnTE 0 Only the same value can be written during timer operation TSnSTR0 TSnTE 1 If the different value is written to this register when TSnSTR0 TSnTE 1 timer operation cannot be guaranteed If this register is erroneously rewritten set this register again ...

Page 773: ...ing Modes Counting start The 16 bit counter of TSG2n starts counting from the initial value 0000H in all modes except for HT PWM mode The counter increments from 0000H 0001H 0002H 0003H in all modes except for HT PWM mode Counter clear The 16 bit counter is cleared by the match of the counter value and the compare register set value Counter read during counting In the TSG2n the 16 bit counter valu...

Page 774: ...he TSnCMP5 buffer register INTTSG2nI06 A compare match interrupt of the 16 bit counter value with the TSnCMP6 buffer register INTTSG2nI07 A compare match interrupt of the 16 bit counter value with the TSnCMP7 buffer register INTTSG2nI08 A compare match interrupt of the 16 bit counter value with the TSnCMP8 buffer register INTTSG2nI09 A compare match interrupt of the 16 bit counter value with the T...

Page 775: ...etting PWM period TSnCMP1 Setting TSG2nO1 clear timing and TSG2nO2 set timing TSnCMP2 Setting TSG2nO1 set timing and TSG2nO2 clear timing TSnCMP5 Setting TSG2nO3 clear timing and TSG2nO4 set timing TSnCMP6 Setting TSG2nO3 set timing and TSG2nO4 clear timing SP PWM mode Setting PWM period TSnCMP1 Setting TSG2nO1 clear timing and TSG2nO2 set timing TSnCMP2 Setting TSG2nO1 set timing and TSG2nO2 clea...

Page 776: ... timing See TSNCMP1W to TSnCMP11W HT PWM mode TSnCMP9 Setting TSG2nO5 clear timing and TSG2nO6 set timing TSnCMP10 Setting TSG2nO5 set timing and TSG2nO6 clear timing See TSnCMP1W TSnCMP5W and TSnCMP9W SP PWM mode TSnCMP9 Setting TSG2nO5 clear timing and TSG2nO6 set timing TSnCMP10 Setting TSG2nO5 set timing and TSG2nO6 clear timing See TSnCMP1W TSnCMP5W and TSnCMP9W 120 DC mode TSnCMP7 TSnCMP8 Se...

Page 777: ...nCMP5 TSnCMP6 set value SP PWM mode Setting diagnostic output or A D conversion trigger timing Setting diagnostic output or A D conversion trigger timing 120 DC mode Setting diagnostic output or A D conversion trigger timing Setting diagnostic output or A D conversion trigger timing Table 15 37 Compare Register Functions in Each Mode 4 4 Operating Mode TSnCMPW TSnUPW TSnVPW TSnWPW PWM mode HT PWM ...

Page 778: ... the 16 bit sub counter If the rewrite is performed while the 16 bit counter is counting down the value is reflected at the next valley timing of the 16 bit sub counter Reload mode simultaneous rewrite function Writing to TSnCMP1 TSnCMP1W TSnCMPU TSnUPW enables reload sets the reload request flag TSnSTR0 TSnRSF and the values of all the pertinent registers are updated simultaneously at the next re...

Page 779: ...e TSG2n_base1 040H TSnCMP1W TSG2n_base1 044H TSnCMP5W TSG2n_base1 048H TSnCMP9W TSG2n_base1 04CH TSnCMP3W TSG2n_base1 050H TSnCMP7W TSG2n_base1 054H TSnCMP11W TSG2n_base1 058H TSnCMP0 TSG2n_base1 05CH TSnDCMP0W TSG2n_base1 060H TSnDCMP2 TSG2n_base1 064H TSnPAT0W TSG2n_base1 068H TSnPAT1W TSG2n_base1 06CH TSnDTC0W TSG2n_base1 070H TSnDTC1W Table 15 39 Duty Setting in HT PWM Mode Address Register Na...

Page 780: ...PWM mode of the 16 bit counter after being written to the compare registers or at the match timing of the TSnCMP0 value with the 16 bit counter value in any mode other than HT PWM mode Figure 15 2 Anytime Rewrite Timing Example in PWM Mode Note 1 D01 D02 TSnCMP0 setting value 0000H to FFFFH D11 D12 TSnCMP1 setting value 0000H to FFFFH D21 TSnCMP5 setting value 0000H to FFFFH D31 TSnCMP9 setting va...

Page 781: ...se is cleared while the 16 bit counter is counting up the 16 bit sub counter is counting down the inverse phase is set if the rewritten value is TSnCMPm TSnCNT The dead time is inserted after clearance of the positive phase If anytime rewrite is performed before the positive phase is cleared while the 16 bit counter is counting up the 16 bit sub counter is counting down the positive phase is clear...

Page 782: ... 3 Basic Operation Flow in Reload Mode Simultaneous Rewrite Function Example of PWM Mode Caution Writing to TSnCMP1 also enables reloading Therefore TSnCMP1 should be rewritten after TSnCMP0 and TSnCMP2 to TSnCMP12 registers have been rewritten START An INTTSG2nI00 interrupt is generated TSnSTR0 TSnRSF 0 NO YES Initial setting Enable timer operation When TSnTRG0 TSnTS is set to 1 TSnCMP0 to TSnCMP...

Page 783: ... TSnCMP6 buffer 16 bit counter INTTSG2nIVLY INTTSG2nIPEK TSnRSF Reload rewrite timing Reload by writing to TSnCMP1 Updated simultaneously at reload timing The flag is cleared after reloading Reload request flag is set 16 bit counter Reload rewrite timing TSnCMP0 buffer TSnCMP1 buffer TSnCMP2 buffer TSnCMP3 buffer TSnCMP4 buffer TSnCMP5 buffer TSnCMP6 buffer TSnCMP0 TSnCMP1 TSnCMP2 TSnCMP3 TSnCMP4 ...

Page 784: ...K or INTTSG2nIVLY is generated Table 15 42 List of Reload Settings when TSnCTL3 TSnRIA 1 Mode TSnCTL4 TSnPRE TSnCTL4 TSnVRE TSnCTL4 TSnPIE TSnCTL4 TSnVIE TSnCTL4 TSnRCC4 TSnRCC0 Reload PWM mode 0 0 1 0 1 0 1 Any value Setting prohibited SP PWM mode 1 0 0 0 1 Any value Setting prohibited 120 DC mode 1 0 1 0 1 Any value When INTTSG2nI00 is generated 1 1 0 0 1 Any value Setting prohibited 1 1 1 0 1 A...

Page 785: ...ignal by TSnCMP3W TSnCMP3 and TSnCMP4 TSnCMP7W TSnCMP7 and TSnCMP8 and TSnCMP11W TSnCMP11 and TSnCMP12 Table 15 43 List of Timer Outputs in Each Mode 2 3 Operating Mode TSG2nO3 Pin TSG2nO4 Pin TSG2nO5 Pin PWM mode Outputs a PWM signal by compare match of TSnCMP5W TSnCMP5 and TSnCMP6 Outputs a PWM signal by compare match of TSnCMP7W TSnCMP7 and TSnCMP8 Outputs a PWM signal by compare match of TSnCM...

Page 786: ... and TSnCMP12 Outputs a diagnostic signal or A D conversion trigger HT PWM mode Outputs an inverse phase PWM signal with dead time to TSG2nO5 pin Outputs a diagnostic signal or A D conversion trigger SP PWM mode Outputs an inverse phase PWM signal with dead time to TSG2nO5 pin Outputs a diagnostic signal or A D conversion trigger 120 DC mode Outputs a PWM signal by TSnCMP3W TSnCMP3 and TSnCMP4 TSn...

Page 787: ...ins active When the TSnADTRG1 signal is detected while the TSG2nO7 pin is inactive the TSG2nO7 pin remains inactive If TSnADTRG0 and TSnADTRG1 signal triggers occur simultaneously the TSG2nO7 pin is inactivated Figure 15 5 Example of A D Trigger Output Timing of TSG2nO7 Pin TSnIOC1 TSnTGS 0 Note 1 When TSnDCMP0 TSnDCMP1 TSnCTL5 0004H and TSnCTL6 0010H 2 When TSnDCMP0 TSnDCMP1 TSnCTL5 0004H and TSn...

Page 788: ...output width specified by TSnDWD causing their active level widths to be overlapped the TSG2nO7 pin outputs a pulse within 16 clock cycles PCLK Figure 15 6 Example of TSG2nO7 Pin Diagnostic Pulse Output Timing 1 TSnIOC1 TSnTGS 1 Figure 15 7 Example of TSG2nO7 Pin Diagnostic Pulse Output Timing 2 with Pulse Output Width Overlapped TSnDCMP1 TSG2nO7 output pulse width is set to 8 clock cycles PCLK TS...

Page 789: ...h interrupt 1 TSnCMP2 compare match interrupt 1 TSnCMP3 compare match interrupt 1 HT PWM mode Period interrupt TSnCMP1 compare match interrupt 2 TSnCMP2 compare match interrupt 2 SP PWM mode TSnCMP0 compare match interrupt TSnCMP1 compare match interrupt 1 TSnCMP2 compare match interrupt 1 120 DC mode TSnCMP0 compare match interrupt TSnCMP1 compare match interrupt 1 TSnCMP2 compare match interrupt...

Page 790: ... SP PWM mode TSnCMP9 compare match interrupt 1 TSnCMP10 compare match interrupt 1 120 DC mode TSnCMP8 compare match interrupt 1 TSnCMP9 compare match interrupt 1 TSnCMP10 compare match interrupt 1 TSnCMP11 compare match interrupt 1 Table 15 44 List of Interrupts in Each Mode 4 5 Operating Mode INTTSG2nI12 INTTSG2nIPEK INTTSG2nIVLY PWM mode TSnCMP12 compare match interrupt Peak interrupt at the sam...

Page 791: ...C mode it is generated after the 16 bit counter value has matched with the TSnCMP0 buffer register value A compare match interrupt INTTSG2nIm is generated by a match of the TSnCMPm buffer register value with the 16 bit counter value depending on the compare register to be used in each operating mode m 01 to 12 A peak interrupt INTTSG2nIPEK is generated in all the modes In HT PWM mode it is generat...

Page 792: ...HT PWM Mode l j k l j k l j k k 16 bit counter d0 TSnDTC0 0000H TSnCMP0 TSnCMP1 TSnCMP2 TSnCMP5 TSnCMP6 TSnCMP9 TSnCMP10 TSnDTC0 TSnDTC1 INTTSG2nI01 INTTSG2nI02 INTTSG2nI05 INTTSG2nI06 INTTSG2nI09 INTTSG2nI10 INTTSG2nIPEK peak interrupt INTTSG2nIVLY valley interrupt x p d0 p for period setting I U phase duty j V phase duty k W phase duty d0 d1 x ...

Page 793: ...2 TSG20 Figure 15 8 Interrupt Generation Example 2 2 Example of PWM Mode 16 bit counter 0000H TSnCMP0 TSnCMP1 TSnCMP2 TSnCMP3 TSnCMP4 INTTSG2nI00 INTTSG2nI01 INTTSG2nI02 INTTSG2nI04 INTTSG2nI03 INTTSG2nIPEK peak interrupt INTTSG2nIVLY valley interrupt p p i j k p l i j k l i j k l L ...

Page 794: ...l operating modes 5 Pattern order detection flag TSnTSF TSnSTR1 All operating modes 6 Pattern error detection flag TSnPEF TSnSTR2 All operating modes 7 Pattern reversal detection flag TSnPRF TSnSTR2 All operating modes 8 TSG2nPTSI2 to TSG2nPTSI0 pin abnormal toggle detection flag TSnPTF TSnSTR2 All operating modes 9 TSnOPCI0 and TSnOPCI1 signal simultaneous trigger detection flag TSnTDF TSnSTR2 Al...

Page 795: ...both TSnCUF and TSnSUF 0 means increment and 1 means decrement TSnCUF and TSnSUF can be used only in HT PWM mode Example of operation Figure 15 9 Example of Up Count Flag Operation Note 1 TSnCUF value is 0 up count when TSnDTC0 16 bit counter TSnCMP0 TSnDTC0 2 1 down count when TSnCMP0 TSnDTC0 2 16 bit counter TSnDTC0 2 Note 2 TSnSUF value is 0 up count when 0 16 bit sub counter TSnCMP0 TSnDTC0 TS...

Page 796: ...perating mode TSnCUF and TSnSUF can be used only in HT PWM mode 16 bit counter 16 bit sub counter TSnCUF TSnCMP0 TSnDTC0 TSnCMP0 TSnDTC0 TSnDTC1 TSG2nO0 pin TSnDTC0 TSnSUF 0000H TSnTOS 0 TSnTOS 1 TSG2nO0 pin Outputs the up down counting state of the 16 bit counter to the TSG2nO0 pin Outputs up down counting state of the 16 bit sub counter to the TSG2nO0 pin ...

Page 797: ... phase of the TSG2n is detected the corresponding TSnTBF0 to TSnTBF2 flags are set to 1 and an error interrupt INTTSG2nIER is generated The flags are cleared when 1 is written to TSnSTC TSnTBR0 to TSnTBR2 respectively Example of operation Figure 15 11 Example of Positive Phase and Inverse Phase Simultaneous Active State Detection Flag Operation Operating mode TSnTBF0 to TSnTBF2 can be used in all ...

Page 798: ...he value is transferred to all the buffer registers Example of operation Figure 15 12 Example of Reload Request Flag Operation Figure 15 13 Reload Request Flag and Reload Skipping Period Operating Mode TSnRSF can be used in all operating modes 16 bit counter 16 bit counter x y x y TSnCMP1 TSnRSF TSnCMP1 TSnCMP1 buffer TSnRSF x y x y TSnCMP1 buffer Reload timing Reload timing Reload request Reload ...

Page 799: ... TSG2nPTSI0 have changed simultaneously a noise is generated and a warning interrupt INTTSG2nIWN is generated The TSnNDF flag is cleared to 0 when 1 is written to the TSnSTC TSnNDR bit Example of operation Figure 15 14 Example of Noise Detection Flag Operation Operating mode TSnNDF can be used in all operating modes Caution TSnNDF is valid only when TSnCTL1 TSnNDC 1 and TSnSTR0 TSnTE 1 TSG2nPTSI2 ...

Page 800: ... pins as shown in the table below Example of operation a When Normal Input to TSG2nPTSI2 to TSG2nPTSI0 Pins is Detected As shown in Figure 15 15 if the TSG2nPTSI2 to TSG2nPTSI0 pins change in the normal order 0 or 1 is set according to the change order at the change timing Figure 15 15 Example of Pattern Order Detection Flag Operation Normal Operation TSnTSF Values input to TSG2nPTSI2 to TSG2nPTSI...

Page 801: ...7 Example of Operation when Values Input to Two Pins of TSG2nPTSI2 to TSG2nPTSI0 Change Abnormal Operation 1 TSnTSF does not change at this point because it expects the input pattern change to 0 1 0 or 0 0 1 if values of two pins change TSnTSF does not change 2 TSG2nPTSI2 to TSG2nPTSI0 pins are determined to have been changed from 1 0 1 to 0 0 1 and TSnTSF is set to 1 Operating Mode TSnTSF can be ...

Page 802: ...SI0 pins are 111 or 000 and a warning interrupt INTTSG2nIWN is generated TSnPEF is cleared to 0 when 1 is written to TSnSTC TSnPER Example of operation Figure 15 18 Example of Pattern Error Detection Flag Operation TSG2nPTSI2 to TSG2nPTSI0 Pins 111 Note 111 is detected Operating mode TSnPEF can be used in all operating modes Caution TSnPEF is valid only when TSnCTL1 TSnPEC 1 and TSnSTR0 TSnTE 1 IN...

Page 803: ...leared to 0 when 1 is written to the TSnSTC TSnPRR bit Example of operation Figure 15 19 Example of Pattern Reversal Detection Flag Operation Figure 15 20 Example of Operation immediately after TSnTE Flag in TSnSTR0 is Set to 1 Note 1 Operation starts Note 2 If TSnTSF is set to 1 by the first change in the TSG2nPTSI2 to TSG2nPTSI0 pins immediately after TSnTE is set to 1 reversal is not detected O...

Page 804: ... 1 is written to TSnSTC TSnPTR Example of operation Figure 15 21 Example of TSG2nPTSI2 to TSG2nPTSI0 Pin Abnormal Toggle Detection Flag Operation Operating mode TSnPTF can be used in all operating modes Caution1 TSnPTF is valid only when TSnCTL1 TSnPTC1 bit 1 and TSnSTR0 TSnTE 1 Caution 2 When TSnPTC0 bit 1 and TSnPTC1 bit 1 TSG2nO1 to TSG2nO6 pin output switch control is automatically switched to...

Page 805: ...1 when the TSnOPCI0 and TSnOPCI1 signals are generated simultaneously and a warning interrupt INTTSG2nIWN is generated TSnTDF is cleared to 0 when 1 is written to TSnSTC TSnTDR Example of operation Figure 15 22 Operation of TSG2nPTSI2 to TSG2nPTSI0 Pin Abnormal Toggle Detection Flag Operation Operating mode TSnTDF can be used in all operating modes Caution TSnTDF is valid only when TSnCTL1 TSnTDC ...

Page 806: ...PCLK TSnPPF should be cleared to 0 when no phase difference occurs Example of operation Figure 15 23 Example of Pattern Difference Detection Flag Operation Operating mode TSnPPF can be used in all operating modes Caution1 TSnPPF is valid only when TSnCTL1 TSnPPC 1 and TSnSTR0 TSnTE 1 Caution 2 When 000 or 111 is input to the TSG2nPTSI2 to TSG2nPTSI0 pins or when TSnOPF2 to TSnOPF0 are set to 000 o...

Page 807: ...Flag TSnOPF2 to TSnOPF0 Name Timer output pattern flag TSnSTR1 TSnOPF2 to TSnOPF0 Description TSnOPF2 to TSnOPF0 flags indicate the timer output patterns For details see Section 15 11 4 120 DC Mode and Section 15 11 5 Software Output Control Function Operating mode TSnOPF2 to TSnOPF0 can be used in all operating modes ...

Page 808: ... pins changes The toggle pattern is determined by the TSnPSC bit TSnOPT0 TSnPSS 1 TSnPSC 0 TSG2nPTSI2 to TSG2nPTSI0 Pins after Change 000 111 101 100 110 010 011 001 Current TSG2nPTSI2 to TSG2nPTSI0 pins 000 111 101 Toggle 100 Toggle 110 Toggle 010 Toggle 011 Toggle 001 Toggle TSnPSC 1 TSG2nPTSI2 to TSG2nPTSI0 Pins after Change 000 111 101 100 110 010 011 001 Current TSG2nPTSI2 to TSG2nPTSI0 pins ...

Page 809: ...ample of operation Figure 15 24 Example of Pattern Switch Detection Signal Operation Operating mode The TSnPTE signal can be used in all operating modes Caution The TSnPTE signal is valid only when TSnIOC1 TSnPTS 1 and TSnSTR0 TSnTE 1 TSG2nPTSI2 pin TSG2nPTSI1 pin TSG2nPTSI0 pin TSnPTE signal ...

Page 810: ... skip the interrupts When TSnCTL3 TSnRIA is set to 1 with reload skipping reload is executed at the same timing as the interrupt after being skipped When TSnCTL3 TSnRIA is set to 0 without reload skipping reload is executed at the specified reload timing regardless of interrupt skipping Caution When a value is written to TSnCTL4 and TSnRCC04 to TSnRCC00 are transferred to the buffer register the i...

Page 811: ...TSG2nIVLY Interrupt TSnRCC04 TSnRCC00 bit 00H No skipping INTTSG2nIPEK Interrupt INTTSG2nIVLY Interrupt TSnRCC04 TSnRCC00 bit 01H 1 mask INTTSG2nIPEK Interrupt INTTSG2nIVLY Interrupt TSnRCC04 TSnRCC00 bit 02H 2 mask INTTSG2nIPEK Interrupt INTTSG2nIVLY Interrupt TSnRCC04 TSnRCC00 bit 03H 3 mask INTTSG2nIPEK Interrupt INTTSG2nIVLY Interrupt TSnRCC04 TSnRCC00 bit 04H 4 mask INTTSG2nIPEK Interrupt INT...

Page 812: ...2nIPEK interrupt INTTSG2nIVLY interrupt TSnRCC04 to TSnRCC00 bits 02H INTTSG2nTIPEK interrupt INTTSG2nIVLY interrupt two masks TSnRCC04 to TSnRCC00 bits 03H three masks INTTSG2nIPEK interrupt INTTSG2nIVLY interrupt TSnRCC04 to TSnRCC00 bits 04H INTTSG2nIPEK interrupt INTTSG2nIVLY interrupt four masks 16 bit counter TSnRCC04 to TSnRCC00 bits 00H no skipping INTTSG2nIPEK interrupt INTTSG2nIVLY inter...

Page 813: ...ter is cleared Caution Interrupt interval might be longer 16 bit counter INTTSG2nIPEK interrupt Interrupt skipping counter Interrupt interval TSnRCC04 to TSnRCC00 Reload timing TSnRCC04 to TSnRCC00 buffers INTTSG2nIVLY interrupt 1 1 1 1 1 02 03 02 03 2 2 00 02 01 02 00 01 00 03 L Start Normal Normal 16 bit counter INTTSG2nIPEK interrupt Interrupt skipping counter Interrupt interval TSnRCC04 to TSn...

Page 814: ... the reload timing The interrupt skipping counter is cleared when the value is transferred to the TSnRCC04 to TSnRCC00 buffers not when the pertinent register is rewritten 16 bit counter INTTSG2nIPEK interrupt Interrupt skipping counter TSnRCC04 to TSnRCC00 Interrupt interval TSnRCC04 to TSnRCC00 buffers INTTSG2nIVLY interrupt Start Normal 02 03 00 02 01 00 03 01 02 00 00 1 2 02 03 L 1 1 1 1 2 2 T...

Page 815: ...skipped Caution When a value is written to TSnCTL4 and TSnRCC04 to TSnRCC00 are transferred to the buffer register the interrupt skipping counter is cleared Therefore when the interrupt skipping function is used interrupt interval may be long temporarily To avoid this the interrupt skipping count should be changed with the reload timing being set to the interrupts skipped TSnCTL3 TSnRIA 1 1 Exampl...

Page 816: ...identical A D conversion trigger control circuits which can be controlled independently TSG2n also provides the A D conversion trigger skipping function with the skipping rate of 1 1 1 2 1 4 or 1 8 TSnADTRG0 signal TSnCTL5 TSnAT09 to TSnAT00 07 06 05 04 03 02 01 00 09 08 TSnADTRG0 skipping circuit TSnACC01 and TSnACC00 bits TSnCTL6 TSnAT09 to TSnAT00 TSnACC11 and TSnACC 10 bits 0 1 TSG2nO7 pin 07 ...

Page 817: ...ed by TSnCTL4 TSnPIE and TSnVIE A D conversion trigger is not output TSnAT00 TSnAT10 1 A valley interrupt INTTSG2nIVLY causes an A D conversion trigger pulse to be generated TSnAT01 TSnAT11 1 A peak interrupt INTTSG2nIPEK causes an A D conversion trigger pulse to be generated TSnAT02 TSnAT12 1 While the 16 bit counter is counting up a TSnDCMP0 compare match enables A D conversion trigger to be gen...

Page 818: ...signal TSnADTRG0 signal TSnADTRG0 signal TSnADTRG0 signal TSnADTRG0 signal TSnADTRG0 signal TSnADTRG0 signal TSnADTRG0 signal When TSnAT09 to TSnAT00 bits 0000000001B an INTTSG2nIVLY interrupt causes a trigger pulse to be generated When TSnAT09 to TSnAT00 bits 1000000000B a peak of sub counter causes a trigger pulse to be generated When TSnAT09 to TSnAT00 bits 0000000011B both peak and valley caus...

Page 819: ...CTL4 and TSnACC01 and TSnACC00 00B and TSnAT09 to TSnAT00 00001001B in TSnCTL5 HT PWM Mode Note Skipped interrupt request L 16 bit counter INTTSG2nIPEK interrupt INTTSG2nIVLY interrupt When TSnAT09 to TSnAT00 bits 00000011B both INTTSG2nIVLY and INTTSG2nIPEK interrupts cause a trigger pulse to be generated but a peak interrupt is not generated since TSnPIE bit is 0 TSnADTRG0 signal 16 bit counter ...

Page 820: ...ction Note Broken lined pulses indicate A D conversion trigger pulses skipped by the A D conversion trigger skipping function 16 bit counter INTTSG2nIPEK interrupt INTTSG2nIVLY interrupt TSnADTRG0 signal TSnDCMP0 compare match TSnDCMP1 compare match When TSnAT09 to TSnAT00 bits 0000100101B TSnACC01 and TSnACC00 bits 01B TSnADTRG0 signal When TSnAT09 to TSnAT00 bits 0000100101B TSnACC01 and TSnACC0...

Page 821: ...SnADTRG0 signal Note Immediately after counting starts a valley timing of the 16 bit sub counter is not generated and thus the A D conversion trigger skipping counter is not incremented When TSnDTC0 0000H TSnDTC1 0000H TSnACC01 and TSnACC00 bits 10B and TSnAT09 to TSnAT00 bits 1000000000B in TSnCTL5 16 bit counter Peak of 16 bit sub counter A D conversion trigger skipping counter TSnADTRG0 signal ...

Page 822: ...ng counter is incremented by one and one trigger pulse is output upon a match of the 16 bit counter with these registers In PWM mode SP PWM mode and 120 DC mode a valley interrupt INTTSG2nIVLY is not generated Only a peak interrupt INTTSG2nIPEK is valid In 120 DC mode when the 16 bit counter is cleared during the carrier period due to switch of the output pattern the A D conversion trigger is not ...

Page 823: ...on 19 4 1 Hi Z Control Functions The following table shows whether or not the simultaneous active state of the positive phase and inverse phase can be detected in each mode Figure 15 35 Error Interrupt INTTSG2nIER Generation Control Circuit Caution When an error interrupt is generated the error status should be canceled within an error interrupt handling Otherwise subsequent error interrupts are n...

Page 824: ...e set so that the TSG2nO1 and TSG2nO2 pins output the active level simultaneously an error interrupt INTTSG2nIER is generated With the same setting the TSG2nO3 and TSG2nO4 and TSG2nO5 and TSG2nO6 pins also output the active level simultaneously an error interrupt INTTSG2nIER is generated Figure 15 36 Example of Error Interrupt INTTSG2nIER Generation PWM Mode Note TSG2nO3 and TSG2nO4 and TSG2nO5 an...

Page 825: ...r occurs when the dead time control function is used both TSnDTC0 and TSnDTC1 are not 0000H internal circuit failure may occur Figure 15 38 Example of Error Interrupt Operation Note TSG2nO2 pin control circuit failure occurs When TSnOL1 0 TSnOL2 0 When TSnOL1 1 TSnOL2 0 When TSnOL1 0 TSnOL2 1 When TSnOL1 1 TSnOL2 1 16 bit counter TSG2nO1 pin TSG2nO2 pin INTTSG2nIER interrupt 16 bit counter TSG2nO1...

Page 826: ...SI0 pins See Section 15 7 6 Pattern Error Detection Flag TSnPEF When a toggle of the TSnPTSI2 to TSG2nPTSI0 pins is generated three times or more between TSnOPCI0 and TSnOPCI1 signal triggers See Section 15 7 8 TSG2nPTSI2 to TSG2nPTSI0 Pin Abnormal Toggle Detection Flag TSnPTF When the TSnOPCI0 and TSnOPCI1 signal triggers are detected simultaneously See Section 15 7 9 TSnOPCI0 and TSnOPCI1 Signal...

Page 827: ... Jul 17 2014 V850E2 PG4 L Section 15 TSG2 TSG20 15 11 Operating Modes Table 15 47 List of Modes TSnCTL0 Register Timer Modes TSnMD1 TSnMD0 0 0 PWM mode 0 1 HT PWM mode HT PWM 1 0 Shifted pulse pulse width modulation mode SP PWM 1 1 120 DC mode ...

Page 828: ...r timing of the TSG2nO6 output Functional description Set the PWM period and set clear timing of the TSG2nO1 to TSG2nO6 outputs Set TSnTRG0 TSnTS 1 to start the timer counter The TSG2nO1 to TSG2nO6 outputs are set to the inactive state at the same time the counting begins The outputs are set to the active state by the match of the buffer registers TSnCMP2 TSnCMP4 TSnCMP6 TSnCMP8 TSnCMP10 and TSnCM...

Page 829: ...r and TSnCMPm m 2 4 6 8 10 12 buffer register set timing TSG2nO1 to TSG2nO6 output active level Initial setting Timer operation enabled TSnTRG0 TSnTS 1 Transfer the values of TSnCMP0 to TSnCMP12 registers to TSnCMP0 to TSnCMP12 buffer registers Upon match of 16 bit counter and TSnCMPk k 1 3 5 7 9 11 buffer register clear timing TSG2nO1 to TSG2nO6 output inactive level Upon match of 16 bit counter ...

Page 830: ...0 TSnMD1 and TSnMD0 00B Setting of compare registers TSnCMP0 to TSnCMP12 registers Setting of PWM output Setting of interrupt TSnCTL4 TSnPIE 1 Initial setting Timer operation enabled TSnTRG0 TSnTS 1 Transfer the values of TSnCMP0 to TSnCMP12 registers to TSnCMP0 to TSnCMP12 buffer registers TSnRSF flag 0 Rewriting of TSnCMP0 and TSnCMP2 to TSnCMP12 Rewriting of TSnCMP1 register Upon match of 16 bi...

Page 831: ...load Anytime rewrite Possible Diagnostic output or A D conversion trigger TSnDTC0 TSnDTC1 Reload Possible Setting dead time Table 15 50 Timer Output in PWM Mode Pin Function TSG2nOm m 1 to 6 PWM output by compare match of TSnCMPk buffer register and 16 bit counter k 1 to 12 TSG2nO7 Diagnostic signal output or pulse output by A D conversion trigger Table 15 51 Interrupt Requests in PWM Mode Interru...

Page 832: ... output TSnCMP0 1 count clock Output an inactive level throughout one period duty cycle 0 TSnCMPm TSnCMP m 1 or TSnCMP m 1 TSnCMP0 m 1 3 5 7 9 11 Output an active level of one count clock in one period TSnCMPm TSnCMP m 1 1 TSnCMP m 1 TSnCMPm 1 m 1 3 5 7 9 11 Output an inactive level of one count clock in one period TSnCMPm TSnCMP m 1 1 TSnCMP m 1 TSnCMPm 1 m 1 3 5 7 9 11 Output an active level thr...

Page 833: ...11 D12 and D13 Set values of TSnCMP2 0000H FFFFH Note 2 TSG2nO1 PWM duty cycle TSnCMP1 TSnCMP2 count clock TSG2nO1 PWM period TSnCMP0 1 count clock Note 3 TSG2nO2 to TSG2nO6 pins behave similarly to the TSG2nO1 pin Note 4 Write access Note 5 TSnCMP1 write access equivalent FFFFH D10 16 bit counter TSnTS TSnCMP0 TSnCMP1 TSnCMP0 TSnCMP1 buffer registers TSnCMP2 TSnCMP2 buffer register TSG2nO1 pin TS...

Page 834: ...D02 and D03 Set point of TSnCMP0 0000H FFFFH D10 D11 D12 and D13 Set point of TSnCMP1 0000H FFFFH D20 D21 D22 and D23 Set point of TSnCMP2 0000H FFFFH Note 2 Outputs from TSG2nO2 to TSG2nO6 behave similarly to the TSG2nO1 pin Note 3 Write access 16 bit counter TSnCMP0 buffer register TSnCMP2 buffer register TSG2nO1 pin Reload Reload Reload FFFFH 0000H 0000H 1 2 0000H D22 TSnCMP1 buffer register TS...

Page 835: ...led according to the switch timing of the TSG2nO1 output the TSG2nO2 output the TSG2nO3 output the TSG2nO4 output the TSG2nO5 output and the TSG2nO6 output Table 15 54 Dead Time in PWM Mode Switch Timing Dead Time TSG2nO1 High level to low level TSG2nO2 Low level to high level Value of TSnDTC1 register TSG2nO2 High level to low level TSG2nO1 Low level to high level Value of TSnDTC0 register TSG2nO...

Page 836: ...g when the dead time count operation ends At 2 the dead time counter starts counting at the falling edge of the TSG2nO1 output Even after the match of the 16 bit counter and TSnCMP4 the TSG2nO2 output stays inactive because the dead time counter is still operating The TSG2nO2 output becomes active at the timing when the dead time count operation ends Note 1 The TSG2nO1 and TSG2nO2 pin outputs are ...

Page 837: ...ve At 2 the INTTSG2nIER interrupt occurs because the TSnCMP2 register and the TSnCMP4 register are set so that the TSG2nO1 and TSG2nO2 outputs rise simultaneously Here the TSG2nO1 output and the TSG2nO2 output are inactive At 3 compare match with the TSnCMP4 register generates an INTTSG2nIER interrupt and both TSG2nO1 and TSG2nO2 outputs become inactive At 4 the falling edge inactive of the TSG2nO...

Page 838: ...become high simultaneously Note 1 TSG2nO1 and TSG2nO2 are set to active high Note 2 The TSG2nO3 to TSG2nO6 pin outputs behave similarly 4 Dead Time Rewriting during Timer Operation in PWM Mode In PWM mode it is possible to rewrite TSG2n dead time setting registers TSnDTC0 and TSnDTC1 while counting The new settings are active at reload timing It is not possible to change the dead time setting by r...

Page 839: ...ric triangular wave control Functional description Set the period of carrier wave and the duty cycle of the U phase the V phase and the W phase Counting up begins when TSnTRG0 TSnTS is set to 1 The 16 bit counter counts up from TSnDTC0 as the minimum value and counts down upon the match of the maximum value of TSnCMP0 TSnDTC0 The dead time is set with TSnDTC0 and TSnDTC1 TSnDTC0 sets the dead time...

Page 840: ...fer V phase output data TSnCMP9 TSnCMP10 buffer W phase output data TSnDTT3 counter TSG2nO0 TSG2nO1 U phase TSG2nO2 U phase TSG2nO3 V phase TSG2nO4 V phase TSG2nO5 W phase TSG2nO6 W phase TO6 TO5 TO4 TO3 TO2 TO1 SEL TSnTOS bit U D Sel1 INTTSG2nIPEK INTTSG2nIVLY TSnDTC0 register TSnDTC1 register TSnCMP0 TSnDTC1 SEL U D Sel0 TSnDTC0 register PWM period TSnCMP0 count clock U phase V phase W phase TSn...

Page 841: ...ers Timer operation enabled TSnTRG0 TSnTS 1 Transfer values of TSnCMP0 TSnCMP1 TSnCMP2 TSnCMP5 TSnCMP6 TSnCMP9 TSnCMP10 TSnDTC0 and TSnDTC1 to buffer registers Upon match of 16 bit counter and TSnCMP1 TSnCMP5 and TSnCMP9 buffer register values positive phase OFF inverse phase ON Upon match of 16 bit counter and TSnCMP2 TSnCMP6 and TSnCMP10 buffer registers positive phase ON inverse phase OFF Rewri...

Page 842: ...rom TSnDTC0 Up count Underflow Down count Compare match of TSnCMP0 TSnDTC0 TSnDTC1 buffer register and 16 bit sub counter Load TSnCMP0 TSnDTC0 When value of 16 bit counter matches the value of buffer register TSnCMP0 TSnDTC0 TSnDTC0 When value of 16 bit counter matches the value of the buffer register TSnDTC0 Clear Stop TSnTRG1 TSnTT 0 1 Table 15 56 Compare Register and Dead Time Setting Register ...

Page 843: ... count TSG2nO4 Inverse phase output to TSG2nO3 TSG2nO5 PWM output with dead time by compare match of TSnCMP9 buffer register and 16 bit counter down count and TSnCMP10 buffer register and 16 bit counter up count TSG2nO6 Inverse phase output to TSG2nO5 TSG2nO7 Diagnostic signal output or pulse output by A D conversion trigger Table 15 58 Interrupt Request in HT PWM Mode Interrupt Function INTTSG2nI...

Page 844: ...l of one count clock in one period TSnCMPm TSnCMP0 1 m U V W Output an inactive level of one count clock in one period TSnCMPm 0001H m U V W Active level during all period 100 duty TSnCMPm 0000H m U V W TSG2nO2 TSG2nO4 TSG2nO6 PWM output Inactive level during all period 0 duty TSnCMPm 0000H m U V W Output an active level of one count clock in one period TSnCMPm TSnDTC0 TSnDTC1 1 m U V W Output an ...

Page 845: ...g TSnIOC1 TSnEOC to 1 In HT PWM mode with any value set in the compare register the simultaneous active state of the positive phase and inverse phase is not possible Please refer for to Section 15 10 Error Warning Interrupt for details Setting register rewriting timing with reload function With TSnCTL3 TSnRMC reload simultaneous rewrite or rewrite anytime is specified for the registers with reload...

Page 846: ...2 to TSnDCMP0 set the compare value to the pertinent register The skipping function can be used for TSnADTRG0 and the TSnADTRG1 signals Use TSnACC00 TSnACC01 of TSnCTL5 TSnACC10 and TSnACC11 of TSnCTL6 to select the skipping rate among 1 1 1 2 1 4 and 1 8 Caution Set TSnCTL5 TSnCTL6 and TSnDCMP2 to TSnDCMP0 correctly when using the TSG2nO7 output for the A D conversion trigger timing pulse Setting...

Page 847: ...er value of A and B Duty PWM width setting The duty of the U phase the V phase and the W phase is set with TSnCMPm m U V W or 1 2 5 6 9 and 10 respectively The setting range of the compare registers is as follows 0000H TSnCMPm TSnCMP0 TSnDTC0 TSnDTC1 LSB least significant bit of TSnCMPU TSNCMPV and TSnCMPW indicates the setting of an additional pulse When TSnCMPU 0003H the change in the inverse ph...

Page 848: ...TSnTS 1 Afterwards counting is done by 2 After 16 bit counter reaches the value of TSnCMP0 TSnDTC0 counting is done by 2 Figure 15 84 shows 16 bit counter operation Figure 15 47 Example of 16 Bit Counter Operation in HT PWM Mod Note Minimum 16 bit counter value TSnDTC0 Maximum 16 bit counter value TSnCMP0 TSnDTC0 Carrier period TSnCMP0 x count clock period PCLK 2 counts 2 counts TSnTRG0 TSnTS 1 16...

Page 849: ...ounter into the down count Counting up by the 16 bit sub counter continues until the value reaches the value of TSnCMP0 TSnDTC0 TSnDTC1 and then counting by 2 begins Similarly when the 16 bit counter value matches the TSnDTC0 value the 16 bit counter value is loaded to the 16 bit sub counter and the down count is continued Figure 15 48 Example of 16 bit Sub Counter Operation in HT PWM Mode Note Mi...

Page 850: ...SnDTC1 0004H Note 2 TD0 Time depending on setting of the dead time in the TSnDTC0 register TD1 Time depending on setting of the dead time in the TSnDTC1 register TS1 Time decided by compare match of the 16 bit sub counter and TSnCMPU register when TSnCMPU 16 bit counter maximum value Note 3 Write access TD0 000EH for period setting 0000 002H for dead time setting 004H for dead time setting 16 bit ...

Page 851: ...TSnDTC1 register TS0 Time decided by compare match of 16 bit sub counter and the TSnCMPU register when TSnCMPU 16 bit counter minimum value TS1 Time decided by compare match of the 16 bit sub counter and the TSnCMPU register when TSnCMPU 16 bit counter maximum value 000EH for period setting Load 0002 16 bit counter 16 bit sub counter H 002H for dead time setting 004H for dead time setting TSnTS bi...

Page 852: ...ws the additional pulse control when an odd value is set to TSnCMPU The arrows and numerical values show the width of the duty cycle of the TSG2nO1 output in one period When the additional pulse control is used as shown in Figure 15 51 the width of the output of the TSG2nO1 duty cycle can be set within a range from the width of 12 clock cycles to the width of 0 clock cycles in one clock cycle step...

Page 853: ...tput can be set within a range from the width of 12 clock cycles to the width of 0 clock cycles in two clock cycle step In this case the change in duty cycle is larger than that in the case when the additional pulse control is used Figure 15 52 Example of Output when Additional Pulse Control Is Not Used in HT PWM Mode Note TSnCMP0 12 TSnDTC0 0 TSnDTC1 0 11 10 0 2 4 6 8 10 12 10 8 6 4 2 0 2 4 10 8 ...

Page 854: ...nDTC0 is used for setting a dead time from a change of the inverse phase to the inactive state to a change of the positive phase to the active state TSnDTC1 is used for setting a dead time from a change of the positive phase to the inactive state to a change of the inverse phase to the active state Figure 15 53 shows the output waveform when TSnDTC0 x and TSnDTC1 y Figure 15 53 Example of Output W...

Page 855: ...are updated at the peak of the 16 bit counter When a match occurs between the TSnCMPm set value and the updated TSnCMP0 TSnDTC1 new maximum value with the main counter the match interrupt INTTSG2nIm will not be generated immediately after reload m 02 06 10 Caution 4 When the TSnDTC0 is updated at the valley of the 16 bit counter When a match occurs between the TSnCMPm set value and the updated TSn...

Page 856: ...is set to 0 output control is retained When the reload timing is generated output control is switched to HT PWM mode output control For details refer to Section 15 11 5 Software Output Control Function Figure 15 54 Example of Software Output Control Switching in HT PWM Mode Caution Use reload simultaneous rewrite mode TSnCTL3 TSnRMC 0 when software output control function is used 16 bit counter HT...

Page 857: ...15 55 Flow of Software Output Control in HT PWM Mode Set the output pattern to TSnOPT1 TSnSPC2 TSnSPC0 Set TSnSOC to 1 simultaneously Change the setting of TSnSPC2 TSnSPC0 and switch the output pattern YES NO Repeat as required Set TSnSOC to 0 Reload 1 2 3 4 5 6 7 TSnSTR0 TSnRSF 0 Write to TSnCMPV and TSnCMPW Write to TSnCMPU END START ...

Page 858: ...SnCMPm m 0 1 2 5 6 9 10 TSnDTC0 and TSnDTC1 3 Confirm that reload request flag TSnSTR0 TSnRSF 0 In case TSnRSF 1 do not proceed to the following step until TSnRSF 0 4 By setting TSnSOC 0 the software control starts to be released it is not released here yet 5 After releasing the software output control set the necessary compare registers Proceed to the following step when the register setting is n...

Page 859: ... the U phase V phase and W phase is done by setting the set timing and the clear timing to the same value to the TSnCMPU TSnCMPV and TSnCMPW When an asymmetric triangular wave is used the output control of each phase is done by setting TSnCMPm as follows m 1 2 5 6 9 10 Prerequisites The clear timing of PWM of the voltage data signal of U V and W phases is set with TSnCMP1 TSnCMP5 and TSnCMP9 The s...

Page 860: ... m 1 or TSnCMPm TSnCMP m 1 2 it is possible to set TSnCMPm under the condition 0000H TSnCMPm TSnCMP0 TSnDTC0 TSnDTC1 which also applies to the case in which the symmetric triangular wave is used TSnCMP0 TS nDTC0 TSnDTC1 TSnCMP0 TSnDTC0 TSnCMP0 TSnCMP6 TSnCMP1 TSnCMP9 TSnCMP5 TSnSBC TSnCNT TSnDTC0 TSnDTC1 TSnDTC0 TSnDTC1 TSnDTC1 TSnDTC0 TSnCMP10 TSnCMP2 TSnDTC0 TSnDTC1 TSnCMP1 2 5 6 9 10 TSnCMP0 TS...

Page 861: ... TSnWPW are set to TSnCMP1 TSnCMP5 and TSnCMP9 respectively when set timing and active period are used for control Functional description Set the carrier period and the set timings and duty of U phase V phase and W phase The counting up begins when TSnTRG0 TSnTS is set to 1 The 16 bit counter counts up from 0000H and is cleared by match with TSnCMP0 The dead time is set with TSnDTC0 and TSnDTC1 TS...

Page 862: ...20 1 Basic Timing Chart Figure 15 56 Basic Timing in SP PWM Mode PWM period TSnCMP0 1 count clock TSnCNT TSnCMP0 TSnCMP1 TSnCMP9 TSnCMP5 TSnCMP10 TSnCMP6 TSnDTC0 TSnDTC0 TSnDTC0 TSnDTC1 TSnDTC 1 TSnDTC1 TSnCMP2 0000H TSG2nO1 U phase V phase W phase TSG2nO2 TSG2nO3 TSG2nO4 TSG2nO5 TSG2nO6 ...

Page 863: ...5 6 9 10 16 bit counter starts counting 16 bit counter clears and starts on match with TSnCMP0 Set SP PWM mode TSnCTL0 TSnMD1 and TSnMD0 10B Set compare registers TSnCMPm m 0 1 2 5 6 9 10 Set PWM output Set dead time setting registers TSnDTC0 TSnDTC1 Upon match of 16 bit counter with TSnCMP1 TSnCMP5 and TSnCMP9 buffer registers positive phase OFF inverse phase ON Upon match of 16 bit counter with ...

Page 864: ...ead time TSnDCMP0W TSnDCMP2 Reload Anytime rewrite Possible Outputs a diagnostic signal or A D conversion trigger Table 15 63 Output Functions in SP PWM Mode Pin Function TSG2nO1 PWM output with dead time by compare match of TSnCMP1 buffer register clear timing or TSnCMP2 buffer register set timing with 16 bit counter TSG2nO2 Output inverse phase with respect to TSG2nO1 with dead time TSG2nO3 PWM ...

Page 865: ...h Timer Output Condition in SP PWM Mode 1 2 Pin Item Output Period Output Duty Output Condition Setting Condition TSG2nO1 TSG2nO3 TSG2nO5 PWM output TSnCMP0 1 count clock Output an inactive level throughout one period duty 0 TSnCMPm TSnCMP m 1 or TSnCMP m 1 TSnCMP0 m 1 5 9 Output an active level of one count clock in one period TSnCMPm TSnCMP m 1 1 TSnCMP m 1 TSnCMPm 1 m 1 5 9 Output an inactive l...

Page 866: ...ghout one period duty 0 TSnCMPm TSnCMP m 1 or TSnCMP m 1 TSnCMP0 m 2 6 10 Output an active level of one count clock in one period TSnCMPm TSnCMP m 1 1 TSnCMP m 1 TSnCMPm 1 m 2 6 10 Output an inactive level of one count clock in one period TSnCMPm TSnCMP m 1 1 TSnCMP m 1 TSnCMPm 1 m 2 6 10 Output an active level throughout one period duty 100 TSnCMPm TSnCMP0 m 2 6 10 TSG2nO7 Diagnostic signal outpu...

Page 867: ...gital conversion trigger output The analog to digital conversion trigger 0 TSnADTRG0 signal is set with TSnCTL5 TSnAT09 to TSnAT00 TSnAT09 to TSnAT00 is used to enable or disable the A D conversion trigger output on timing match of TSnDCMP2 to TSnDCMP0 with the 16 bit counter up count TSnCTL6 TSnAT19 to TSnAT10 is used to set the analog to digital conversion trigger 1 TSnADTRG1 signal To set the m...

Page 868: ...llowing expression TSnCMP0 carrier period count clock cycle 1 Caution PWM output with 100 duty cannot be produced when TSnCMP0 FFFFH Setting duty PWM width The duty of U phase V phase and W phase is set with TSnCMPm TSnUPW TSnVPW and TSnWPW m 1 2 5 6 9 10 respectively The set timings of the U phase V phase and W phase are set with TSnCMP2 TSnCMP6 and TSnCMP10 and the clear timings are set with TSn...

Page 869: ... for setting a dead time from a change of the inverse phase to the inactive state to a change of the positive phase to the active state TSnDTC1 is used for setting a dead time from a change of the positive phase to the inactive state to a change of the inverse phase to the active state Figure 15 67 shows an example of the output waveform Figure 15 58 Example of Output Waveform in SP PWM Mode Note ...

Page 870: ...eed After that when TSnSOC is set to 0 output control is retained When the reload timing is generated output control is switched to SP PWM mode output control For details refer to Section 15 11 5 Software Output Control Function Figure 15 59 Example of Output Control Switching from SP PWM Mode Control to Software Control 1 0 0 0 0 1 16 bit counter TSG2nO1 pin TSG2nO2 pin TSG2nO3 pin TSG2nO4 pin TS...

Page 871: ...rol mode 3 Change the output pattern setting for TSnSPC2 TSnSPC0 to change the timer output During software control mode the following registers can be modified TSnTRG0 TSnTS TSnCTL3 TSnCTL6 TSnOPT0 TSnOPT1 TSnCMP0 TSnCMP12 TSnDTC0 and TSnDTC1 4 Ensure that the reload request flag TSnSTR0 TSnRSF is 0 If TSnRSF is 1 do not shift to the following procedure until it goes 0 5 By clearing TSnSOC to 0 s...

Page 872: ...ove to the following procedure if no setting is required In addition change the registers with the reload function if necessary 7 Write TSnUPW TSnCMP1 to start reloading 8 Reload is executed and software output control is released Caution Be sure to execute reload after execution of steps 4 5 6 and 7 Unless reload can be executed software output control cannot be released ...

Page 873: ...1 to INTTSG2nI12 interrupts are generated by a compare match of the 16 bit counter and TSnCMP1 to TSnCMP12 buffer registers respectively Note 120 DC mode is valid when TSnCTL0 TSnMD1 to TSnMD0 are set to 11B Figure 15 61 Block Diagram in 120 DC Mode Match selector INTTSG2nI01 INTTSG2nI02 INTTSG2nI05 INTTSG2nI06 INTTSG2nI09 and INTTSG2nI10 interrupts INTTSG2nI03 INTTSG2nI04 INTTSG2nI07 INTTSG2nI08 ...

Page 874: ...nd TSnPAT1W Setting of dead time setting registers TSnDTC0 and TSnDTC1 Setting of rotation direction TSnOPT0 TSnIDC bit Initial setting Timer operation enabled TSnTRG0 TSnTS bit 1 The values of the TSnCMP0 to TSnCMP12 TSnDTC0 and TSnDTC1 are transferred to the TSnCMP0 to TSnCMP12 TSnDTC0 and TSnDTC1 buffer registers 16 bit counter starts counting 16 bit counter matches with TSnCMP1 to TSnCMP12 buf...

Page 875: ... dead time by compare match of the TSnCMPm buffer register m 1 2 5 6 9 10 with the 16 bit counter and by selecting output pattern through TSnPAT0W setting TSG2nO2 pin PWM output with dead time by compare match of the TSnCMPm buffer register m 3 4 7 8 11 12 and the 16 bit counter and by selecting output pattern through TSnPAT1W setting TSG2nO3 pin PWM output with dead time by compare match of the T...

Page 876: ...pare Match Timing in 120 DC Mode Compare Match Timing TSnCMP0 When 16 bit counter changes from TSnCMP0 to 0000H TSnCMPm m 1 to 12 After detecting the match of 16 bit counter and TSnCMPm m 1 to 12 Table 15 73 Example of Setting Each Timer Output Condition in 120 DC Mode Pin Item Output Period Output Duty Output Condition Setting Condition TSG2nOm m 1 to 6 PWM output TSnCMP0 1 count clock See Sectio...

Page 877: ... output To set A D conversion trigger 0 TSnADTRG0 signal use TSnCTL5 TSnAT09 to TSnAT00 With TSnAT09 to TSnAT00 A D conversion trigger output is enabled or disabled at the match of the 16 bit counter and TSnDCMP2 to TSnDCMP0 during up count To set A D conversion trigger 1 TSnADTRG1 signal use TSnCTL6 TSnAT19 to TSnAT10 To set the match timing of the 16 bit counter and TSnDCMP2 to TSnDCMP0 set the ...

Page 878: ...ion TSnCMP0 carrier period count clock cycle 1 Duty PWM width setting The duty of PWM output is set with TSnCMP1 to TSnCMP12 The setting range of the compare registers is as follows 0000H TSnCMPm TSnCMP0 1 Caution Do not set TSnCMPm to TSnCMP0 1 m 1 to 12 only when TSnCMP0 1 TSnCMPm and TSnCMP0 FFFFH Output PWM setting In 120 DC mode the output pins TSG2nO1 TSG2nO3 and TSG2nO5 are controlled by TS...

Page 879: ...ter is cleared by match of the 16 bit counter and TSnCMP0 or by a write access to TSnOPT1 TSnSPC2 to TSnSPC0 In this method the pattern is output which is decoded using information on the output pattern TSnSPC2 to TSnSPC0 the electric current direction control bit TSnOPT0 TSnIDC and TSG2nPTSI2 to TSG2nPTSI0 pattern order detection flag TSnSTR1 TSnTSF Figure 15 83 shows the timer output when the ou...

Page 880: ...atch of the 16 bit counter and TSnCMP0 or by a change of the input pattern TSG2nPTSI2 to TSG2nPTSI0 pins In this method the pattern which is decoded by using information on input pattern TSG2nPTSI2 to TSG2nPTSI0 the electric current direction control bit TSnOPT0 TSnIDC and TSG2nPTSI2 to TSG2nPTSI0 pattern order detection flag TSnSTR1 TSnTSF is output Figure 15 65 to Figure 15 68 show the timer out...

Page 881: ...ation of trigger switch method With the trigger input switch method the rising edges of the TSnOPCI0 and TSnOPCI1 signals are detected and the output switch timing is generated The initial timer output pattern is set with TSnOPT1 TSnSPC2 to TSnSPC0 The subsequent output patterns are determined with TSnSPC2 to TSnSPC0 TSnOPT0 TSnIDC and TSnPSC The 16 bit counter counts based on the carrier period s...

Page 882: ...d TSG2nO2 TSG2nO4 and TSG2nO6 pins m 0 1 2 3 4 5 Figure 15 63 TSG2nO1 TSG2nO3 TSG2nO5 Pin Output of Each Output Pattern Table 15 74 TSnPAT0W Set Value and Output Control PATmT Value Output Control 000 Fixed to low 001 PWM output set with TSnCMP1 010 PWM output set with TSnCMP2 011 PWM output set with TSnCMP5 100 PWM output set with TSnCMP6 101 PWM output set with TSnCMP9 110 PWM output set with TS...

Page 883: ...t with TSnCMP4 011 PWM output set with TSnCMP7 100 PWM output set with TSnCMP8 101 PWM output set with TSnCMP11 110 PWM output set with TSnCMP12 111 Fixed to high 1 PATmB 000B 2 PATmB 001B 3 PATmB 010B 4 PATmB 011B 5 PATmB 100B 6 PATmB 101B 7 PATmB 110B 8 PATmB 111B TSG2nO2 TSG2nO4 TSG2nO6 TSG2nO2 TSG2nO4 TSG2nO6 TSG2nO2 TSG2nO4 TSG2nO6 TSG2nO2 TSG2nO4 TSG2nO6 TSG2nO2 TSG2nO4 TSG2nO6 TSG2nO2 TSG2n...

Page 884: ...PWM operation set by TSnCMP1 to TSnCMP12 respectively Figure 15 65 Example of Operation in 120 DC Mode Normal Rotation TSnSTR1 TSnTSF 0 and TSnOPT0 TSnIDC 0 Note 1 For pattern switch method TSnOPT0 TSnPOT 0 Note 2 For trigger switch method TSnOPT0 TSnPOT 1 and TSnPSS 1 Note TSnOPT0 TSnSOC 0 16 bit counter 1 Time Input pattern 1 Input pattern 2 Input pattern 3 Input pattern 4 Input pattern 5 Input ...

Page 885: ...put pattern 2 Input pattern 3 Input pattern 4 Input pattern 5 Input pattern 6 Input pattern 1 2 Pattern switch trigger TSG2nPTSI2 pin TSG2nPTSI1 pin TSG2nPTSI0 pin TSnTSF flag L TSG2nO1 pin TSG2nO2 pin TSG2nO3 pin TSG2nO4 pin TSG2nO5 pin TSG2nO6 pin TSnOPF2 to TSnOPF0 flags PAT3T PAT4T PAT5T PAT0T PAT1T PAT2T PAT3T PAT3B PAT2B PAT1B PAT0B PAT1T PAT0T PAT5T PAT4T PAT4B PAT5B PAT0B PAT1B PAT5T PAT4T...

Page 886: ...nput pattern 2 Input pattern 3 Input pattern 4 Input pattern 5 Input pattern 6 Input pattern 1 2 Pattern switch trigger TSG2nO1 pin TSG2nO2 pin TSG2nO3 pin TSG2nO4 pin TSG2nO5 pin TSG2nO6 pin TSnOPF2 to TSnOPF0 flags 1 0 1 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 1 0 1 PAT5B PAT4B PAT3B PAT2B PAT1B PAT0B PAT5B PAT5T PAT0T PAT1T PAT2T PAT3T PAT4T PAT5T PAT3B PAT4B PAT5B PAT0B PAT1B PAT2B PAT3B PAT3T PAT4T PAT...

Page 887: ...nput pattern 2 Input pattern 3 Input pattern 4 Input pattern 5 Input pattern 6 Input pattern 1 2 Pattern switch trigger TSG2nPTSI2 pin TSG2nPTSI1 pin TSG2nPTSI0 pin TSnTSF flag H TSG2nO1 pin TSG2nO2 pin TSG2nO3 pin TSG2nO4 pin TSG2nO5 pin TSG2nO6 pin TSnOPF2 to TSnOPF0 flags PAT4T PAT5T PAT0T PAT1T PAT2T PAT3T PAT4T PAT4B PAT5B PAT0B PAT1B PAT2B PAT3B PAT4B PAT0T PAT1T PAT2T PAT3T PAT4T PAT5T PAT0...

Page 888: ...to PAT5B PWM output set by TSnCMP3W TSnCMP7W and TSnCMP11W TSnOPT0 Rotation Direction TSnPOT TSnPSS 0 TSnTSF 1 1 TSnPSC The order of pattern switching Output Pin TSnOPT1 TSnSPC2 to TSnSPC0 TSnSTR1 TSnOPF2 to TSnOPF0 101 100 110 010 011 001 000 111 TSG2nO1 PAT0T PAT1T PAT2T PAT3T PAT4T PAT5T Low Low TSG2nO2 PAT0B PAT1B PAT2B PAT3B PAT4B PAT5B Low Low TSG2nO3 PAT4T PAT5T PAT0T PAT1T PAT2T PAT3T Low ...

Page 889: ...nd TSnCMP11W The order of pattern switching Output Pin TSnOPT1 TSnSPC2 to TSnSPC0 TSnSTR1 TSnOPF2 to TSnOPF0 101 100 110 010 011 001 000 111 TSG2nO1 PAT1T PAT0T PAT5T PAT4T PAT3T PAT2T Low Low TSG2nO2 PAT1B PAT0B PAT5B PAT4B PAT3B PAT2B Low Low TSG2nO3 PAT3T PAT2T PAT1T PAT0T PAT5T PAT4T Low Low TSG2nO4 PAT3B PAT2B PAT1B PAT0B PAT5B PAT4B Low Low TSG2nO5 PAT5T PAT4T PAT3T PAT2T PAT1T PAT0T Low Low...

Page 890: ...ion TSnSTR1 TSnTSF cannot be determined Therefore set the rotation direction in TSnPSC when TSnTE is 0 The TSnPSC set value is loaded to TSnTSF and the value can be used for the initial pattern setting TSnOPT0 TSnSOC 0 TSnPSC 0 TSnPOT 0 TSnIDC 0 Figure 15 69 Control when Timer Output Starts in Normal Rotation when Normal Pattern is Input Direction control by TSnTSF PAT0B Direction control by TSnPS...

Page 891: ...TSnOPT0 TSnPSS 1 Direction control by TSnTSF TSG2nPTSI2 pin TSG2nPTSI1 pin TSG2nPTSI0 pin TSnSTR0 TSnTE TSG2nO1 pin TSG2nO2 pin TSG2nO3 pin TSG2nO4 pin TSG2nO5 pin TSG2nO6 pin L L L L PAT0T PAT0B PAT4T PAT4B PAT2T PAT2B PAT1T PAT1B PAT5T PAT5B PAT3T PAT3B H L L L Direction control by TSnPSC bit TSnOPT0 TS nPSS 1 Direction control by TSnTSF Time Low level is output because of input pattern error 11...

Page 892: ...se Rotation when Error Pattern is Input Time TSG2nPTSI2 pin TSG2nPTSI1 pin TSG2nPTSI0 pin TSnSTR0 TSnTE TSG2nO1 pin TSG2nO2 pin TSG2nO3 pin TSG2nO4 pin TSG2nO5 pin TSG2nO6 pin Low level is output because of input pattern error 111 Direction control by TSnTSF Direction control by TSnPSC bit TSnOPT0 TS nPSS 1 PAT0T PAT0B PAT4T PAT4B PAT2T PAT2B PAT1T PAT1B PAT5T PAT5B PAT3T PAT3B L L L H ...

Page 893: ...TSnOPCI0 and TSnOPCI1 signal trigger is input for several times within one period the output pattern is switched by clearing the 16 bit counter each time the trigger is accepted In the trigger switch method if a rewrite to TSnOPT1 TSnSPC2 to TSnSPC0 and TSnOPCI0 and TSnOPCI1 trigger occur within one period TSnSPC2 to TSnSPC0 are rewritten If TSnSPC2 to TSnSPC0 are rewritten more than once within o...

Page 894: ...red and output control is switched TSnOPT0 TSnPOT 1 Figure 15 75 Output Switch Example Switched by TSnOPT0 TSnPSC Note When the pattern is switched here output control is switched from the next period 16 bit counter PAT PAT PAT PAT TSG2nO2 pin TSG2nO1 pin TSnIDC bit 0000H TSnCMP1 TSnCMP2 TSnCMP0 TSnCMP1 TSnCMP1 TSnCMP1 TSnCMP1 TSnCMP1 TSnCMP2 TSnCMP2 TSnCMP3 TSnCMP3 TSnCMP0 TSnCMP0 TSnCMP0 TSnCMP0...

Page 895: ...TSnSPC2 to TSnSPC0 Note Write access 16 bit counter L 0000H TSG2nO1 pin TSG2nO2 pin TSnSPC2 to TSnSPC0 bits TSnCMP2 TSnCMP4 TSnCMP0 TSnCMP0 TSnCMP0 TSnCMP1 TSnCMP3 1 0 1 1 0 0 1 1 0 0 1 0 PAT PAT PAT PAT PAT PAT PAT PAT TSnCMP3 TSnCMP1 TSnCMP3 TSnCMP1 TSnCMP3 TSnCMP1 TSnCMP3 TSnCMP1 TSnCMP3 TSnCMP1 TSnCMP2 TSnCMP4 TSnCMP2 TSnCMP4 TSnCMP2 TSnCMP4 TSnCMP2 TSnCMP4 TSnCMP0 ...

Page 896: ... changed data is not valid until the next reload timing therefore the specified output waveform can be obtained However do not write to TSnCMP1 again while the reload is suspended period from when TSnCMP1 is changed to when simultaneous rewrite is executed Be sure to read the reload request flag TSnRSF to confirm that the flag is 0 and write data to TSnCMP1 Figure 15 77 Output Example when TSnCMP1...

Page 897: ... in the pattern switch method When TSnOPT1 TSnSPC2 to TSnSPC0 are changed and the output pattern is forcibly changed in the trigger switch method When switch method is changed When the current direction control bit TSnOPT0 TSnIDC is changed When the software output control function is used 11 Output Switch in 120 DC Mode In 120 DC mode the output pattern can be controlled by writing values to TSnO...

Page 898: ...n the TSG2nPTSI2 to TSG2nPTSI0 pins during operation with the pattern switch method used Figure 15 79 Example of Noise Filter Circuit Connection Figure 15 80 Example of Noise Generation at Level Change in TSG2nPTSI2 to TSG2nPTSI0 Pins Pattern Switch Method Port and noise filter Brushless DC motor Hall sensor TSG2 TSG2nPTSI2 signal TSG2PTSI1 signal TSG2nPTSI0 signal Device Noise Noise Noise 0 is wr...

Page 899: ...y the rotation direction by TSnPSC TSnPSS 1 in TSnOPT0 in TSnOPT0 when TSnPSC 0 TSG2nPTSI2 to TSG2nPTSI0 Pins after Change 000 111 101 100 110 010 011 001 Current TSG2nPTSI2 to TSG2nPTSI0 pins 000 111 101 Toggle 100 Toggle 110 Toggle 010 Toggle 011 Toggle 001 Toggle when TSnPSC 1 TSG2nPTSI2 to TSG2nPTSI0 Pins after Change 000 111 101 100 110 010 011 001 Current TSG2nPTSI2 to TSG2nPTSI0 pins 000 11...

Page 900: ...at the rising edge of the TSnOPCI0 and TSnOPCI1 signals The output also changes when data is written to TSnSPC2 to TSnSPC0 in TSnOPT0 Note When the input pattern changes to 000 or 111 the TSG2nO1 to TSG2nO6 pins are driven low d Change Timing of TSnTSF Flag The TSnTSF flag toggles when the input pattern TSG2nPTSI2 to TSG2nPTSI0 pins changes TSG2nPTSI2 to TSG2nPTSI0 Pins after Change 000 111 101 10...

Page 901: ...R bit The TSnNDF flag is valid when 1 is set to the TSnNDC bit f Set Timing of TSnPRF Flag The TSnPRF flag is set when the TSnTSF flag changes and cleared when 1 is written to the TSnPRR bit The TSnPRF flag is valid when 1 is set to the TSnPRC bit g Set Timing of TSnPEF Flag The TSnPRF flag is set when 000 or 111 is input to the TSG2nPTSI2 to TSG2nPTSI0 pins and cleared when 1 is written to the TS...

Page 902: ...l because offset width with respect to the hall sensor and the predicted value with respect to the hall sensor should be considered When TSnOPT0 TSnPOT 1 and TSnPSS 1 the rotation direction of the motor can be set with TSnPSC in TSnOPT0 Set TSnPSC to 0 to set normal rotation and 1 to set reverse rotation TSnIDC in TSnOPT0 sets the direction of control acceleration or deceleration If the same value...

Page 903: ... is switched to deceleration control by rewriting only TSnIDC in TSnOPT0 When the rotation count can be reduced to low speed rotation the rotation can be placed in the stopped state by decreasing the PWM duty State transition is shown in Figure 15 81 and Figure 15 82 Figure 15 81 State Transition Diagram Figure 15 82 Relationship between State Transition and Rotation Speed of Motor Note V1 and V4 ...

Page 904: ...rol to 120 DC control set TSnSOC to 0 At this timing output control is retained When the reload timing is generated output control is switched to 120 DC mode For details on software output control function see Section 15 11 5 Software Output Control Function Figure 15 83 Example of Switching from 120 DC Mode to Software Output Control Function Note Write access 16 bit counter 120 DC mode output co...

Page 905: ...h from occurring before step 2 2 Set the output pattern to TSnSPC2 to TSnSPC0 To enable software output control set TSnSOC to 1 simultaneously 3 Change the output pattern setting of TSnSPC2 to TSnSPC0 to change the timer output The registers that can be changed during software control are TSnTRG1 TSnTT TSnCTL4 to TSnCTL6 TSnOPT0 TSnOPT1 TSnCMP0 to TSnCMP12 TSnDTC0 and TSnDTC1 4 Confirm that the re...

Page 906: ... the software output control set the necessary compare registers Proceed to the following step when the register setting is not required Here change the registers with the reload function 7 Write to TSnCMP1 to start reloading 8 Reload is executed and software output is released Caution Execute reload after executing steps 4 to 7 When reload cannot be executed the software output cannot be released...

Page 907: ...d timing Note ACT Active level is output INACT Inactive level is output Table 15 77 Register Description on Software Output Control Function Register Setting TSnOPT0 TSnSOC TSnSOC 1 TSnOPT0 TSnSTE TSnSTE 0 TSnOPT1 TSnSPC2 to TSnSPC0 Set output patterns listed in Table 15 78 and Table 15 79 TSnOPT0 TSnIDC Set output pattern rotation direction Table 15 78 Output Pattern of Software Output Control TS...

Page 908: ... TSnOPT0 TSnIDC 1 TSnOPT0 TSnSOC 1 TSnSTE 0 TSnIDC 1 Output Pin TSnSTR1 TSnOPF2 TSnOPF0 101 100 110 010 011 001 000 111 TSG2nO1 INACT INACT INACT ACT ACT ACT ACT INACT TSG2nO2 ACT ACT ACT INACT INACT INACT INACT ACT TSG2nO3 ACT ACT INACT INACT INACT ACT ACT INACT TSG2nO4 INACT INACT ACT ACT ACT INACT INACT ACT TSG2nO5 INACT ACT ACT ACT INACT INACT ACT INACT TSG2nO6 ACT INACT INACT INACT ACT ACT IN...

Page 909: ...ts from the individual base addresses TPBAn_base0 or TPBAn_base1 Table 16 2 shows the base address of TPBAn Clock supply TPBAn is connected to PCLK and is supplied with the PCLK clock signal input as listed below I O signals The I O signals of the TPBA are listed in Table 16 4 Table 16 1 Instances of TPBA TPBA Instances 1 Name TPBA0 Table 16 2 TPBAn Register Base Addresses TPBAn TPBAn_base0 Addres...

Page 910: ...atched detection interrupt Number of patterns matched detection interrupt Number of duty patterns 64 patterns 16 bits or 128 patterns 8 bits Automatic duty generation according to the number of patterns Output control by software The count clock can be selected from PCLK PCLK 2 PCLK 4 and PCLK 8 according to the prescaler set value Synchronous start with another timer Table 16 5 List of TPBA Inter...

Page 911: ...T PCLK Prescaler Controller TPBAnTS TPBAnTT TPBAnTE TPBAnRSF0 TPBAnCMP0 TPBAnCB0 Reload TPBAnRDM Selector Compare register INTTPBAnIPRD INTTPBAnIDTY TPBnO TPBAnTO TPBAnTOE TPBAnTOL Enable TPBAnCNT1 Clear Reload TPBAnBUF 63 00 Buffer TPBAnCB2 Compare register TPBAnCNT0 Clear TPBAnDPS TPBAnRSF1 TPBAnCMP1 Reload TPBAnCB1 Compare register TPBAnPRS1 0 INTTPBAnIPAT TO controller ...

Page 912: ...An_base1 110H TPBAn reload data trigger register TPBAnRDT TPBAn_base1 114H TPBAn timer output enable register TPBAnTOE TPBAn_base1 120H TPBAn timer output register TPBAnTO TPBAn_base1 11CH TPBAn timer output level register TPBAnTOL TPBAn_base1 124H TPBAn period setting register TPBAnCMP0 TPBAn_base1 100H TPBAn duty setting register TPBAnBUFm TPBAn_base1 000H to 0FCH TPBAn pattern number setting re...

Page 913: ... This register should be set when the timer is stopped TPBAnTE 0 If this register is erroneously rewritten set the register again after stopping the timer 7 6 5 4 3 2 1 0 TPBAn PRS1 TPBAn PRS0 TPBAn DPS R R R W R W R R R R W Table 16 7 TPBAnCTL0 Register Contents Bit Position Bit Name Function 4 5 TPBAnPRS 1 0 Selects the count clock TPBAn PRS1 TPBAn PRS0 Description 0 0 PCLK is selected 0 1 PCLK ...

Page 914: ...er can be rewritten during operation the rewritten value is reflected at any time Accordingly during operation this register should be rewritten when the reload request flag TPBAnRSF is 0 7 6 5 4 3 2 1 0 TPBAn RDM0 R R R R R R R R W Table 16 8 TPBAnRDM Register Contents Bit Position Bit Name Function 0 TPBAnRDM0 Controls the reload timing of the TPBAn period setting register TPBAnCMP0 and TPBAn ti...

Page 915: ...Position Bit Name Function 1 TPBAnRSF1 Indicates whether or not a reload request from TPBAnCMP1 has been generated 0 No reload request generated or reload completed 1 Reload request has been generated This bit is set to 1 when 1 is written to the TPBAnRDT1 bit in the TPBAnRDT register This bit is cleared at the timing when reload is performed 0 TPBAnRSF0 Indicates whether or not a reload request f...

Page 916: ...set from any source 7 6 5 4 3 2 1 0 TPBAn RDT1 TPBAn RDT0 R R R R R R W W Table 16 10 TPBAnRDT Register Contents Bit Position Bit Name Function 1 TPBAnRDT1 Enables reload of the TPBAnCMP1 values 0 Write access is ignored 1 Reload is enabled TPBAnRSF1 is set to 1 The values are updated simultaneously at the next reload timing reload 0 TPBAnRDT0 Enables reload of the TPBAnCMP0 and TPBAnTOL values 0 ...

Page 917: ... 3 2 1 0 TPBAn TOE0 R R R R R R R R W Table 16 11 TPBAnTOE Register Contents Bit Position Bit Name Function 0 TPBAnTOE0 Enables or disables the timer output TPBnO 0 Disables the timer output based on counter operation 1 Enables the timer output based on counter operation When the timer output is disabled the level specified in TPBAnTO is output from the TPBnO pin and can be controlled by software ...

Page 918: ...t from any source 7 6 5 4 3 2 1 0 TPBAn TO0 R R R R R R R R W Table 16 12 TPBAnTO Register Contents Bit Position Bit Name Function 0 TPBAnTO0 Reads the setting of the TPBnO pin output and the output level When the timer output is disabled TPBAnTOE TPBAnTOE0 0 0 Outputs low level 1 Outputs high level When the timer output is enabled TPBAnTOE TPBAnTOE0 1 0 Low level is being output by the timer outp...

Page 919: ...o be reloaded Rewrite during timer operation is reflected at the next reload timing For details on reload see Section 16 5 2 Compare Register Rewrite Operation 7 6 5 4 3 2 1 0 TPBAn TOL0 R R R R R R R R W Table 16 13 TPBAnTOL Register Contents Bit Position Bit Name Function 0 TPBAnTOL0 Specifies the active level of the timer output 0 High 1 Low Setting of this bit is enabled when the timer output ...

Page 920: ... 1 count clock periods Accordingly for PWM output with 100 duty cycle the maximum settable value is FFFEH FEH Caution This register is a register to be reloaded Rewrite during timer operation is reflected at the next reload timing For details on reload see Section 16 5 2 Compare Register Rewrite Operation 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TPBAnCMP0 R W R W R W R W R W R W R W R W R W R W R W R...

Page 921: ... period matched detection interrupt INTTPBAnIPRD Rewrite during timer operation is reflected at any time For details see Section 16 5 3 Duty Rewrite Operation 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TPBAnBUFm R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Table 16 15 TPBAnBUFm Register Contents Bit Position Bit Name Function 15 to 0 TPBAnBUFm15 to TPBAnBUFm0 Sets the duty value This...

Page 922: ... Section 16 5 2 Compare Register Rewrite Operation Caution If 64 or a greater number is set as the number of patterns when the duty setting pattern is in 16 bits 64 patterns mode TPBAnDPS 0 the address pointer changes from 63 to 00 and the duty value is transferred from 00 again A number of patterns matched detection interrupt signal INTTPBAnIPAT is output by the match of the specified number of p...

Page 923: ...nter register through which the 16 bit counter value can be read 12 TPBAn Address Counter Register TPBAnCNT1 This register is a counter register that indicates the address pointer to the duty setting register Access This register can only be read in 8 bit units Address TPBAn_base1 10CH Initial value 00H This register is initialized by a reset from any source 7 bit counter This register indicates T...

Page 924: ...e 00H This register is initialized by a reset from any source 7 6 5 4 3 2 1 0 TPBAn TE0 R R R R R R R R Table 16 17 TPBAnTE Register Contents Bit Position Bit Name Function 0 TPBAnTE0 Indicates whether the timer counter is operating or stopped 0 The timer counter is stopped 1 The timer counter is operating The TPBAnTE0 bit is set to 1 when 1 is written to the TPBAnTS bit or when a synchronous star...

Page 925: ...controls the timer counter stop trigger Access This register can only be written in 8 bit units It is always read as 0 Address TPBAn_base1 130H Initial value 00H This register is initialized by a reset from any source 7 6 5 4 3 2 1 0 TPBAn TS0 R R R R R R R W Table 16 18 TPBAnTS Register Contents Bit Position Bit Name Function 0 TPBAnTS0 This bit is a trigger bit that enables the timer counter 0 W...

Page 926: ...he 16 bit counter value during counting can be read through TPBAnCNT0 2 Basic Operation of 7 Bit Counter TPBAnCNT1 Counting start The 7 bit counter TPBAnCNT1 is initialized to 00H and starts counting Subsequently the counter value is incremented synchronously with a period matched detection interrupt INTTPBAnIPRD Counter clear The 7 bit counter is cleared by the match of the counter value and the ...

Page 927: ...orresponding to the set bits sets the reload request flag TPBAnRSF TPBAnRSFk and the values of all the pertinent registers are updated simultaneously at the next reload timing reload The reload timing of TPBAnCMP0 and TPBAnTOL is set by TPBAnRDM The reload timing of TPBAnCMP1 is the match timing INTTPBAnIPAT of the 7 bit counter TPBAnCNT1 and the buffer register TPBAnCB1 of TPBAnCMP1 The registers...

Page 928: ...rs to be reloaded have been rewritten NO NO START Initial setting Make various settings including settings of the count clock and duty setting patterns to activate the TPBA Timer enabled TPBAnTS TPBAnTS0 1 Transfer the set values of the compare register and the timer output level register to the buffer register at the timing when counting begins TPBAnRSF flag 0 YES Rewrite TPBAnCMPk Rewrite TPBAnT...

Page 929: ...igure 16 3 Simultaneous Rewrite Timing TPBAnDPS 0 TPBAnRDM 0 and TPBAnTOL 0 16 bit counter TPBAnCMP0 TPBAnCB0 TPBAnRDT0 TPBAnRSF0 INTTPBAnIPRD D00 D01 D01 D00 Reload timing Updated simultaneously at reload timing Reload request flag is set Reload request flag is cleared after reloading ...

Page 930: ...ing Flow Figure 16 4 Basic Rewrite Flow of TPBAnBUFm Note Since TPBAnBUFm can be written at any time it is recommended that this register is rewritten during last duty cycle output TPBAnCNT1 00H of the pattern period the number of patterns specified by TPBAnCMP1 START YES NO END Read TPBAnCNT1 Read TPBAnCMP1 Determine whether TPBAnBUFm can be rewritten based on the values of both registers Rewrita...

Page 931: ...e In 16 bits 64 patterns mode TPBAnDPS 0 This register is accessed by the CPU in units of one 16 bit pattern In 8 bits 128 patterns mode TPBAnDPS 1 This register is accessed by the CPU in units of two 8 bit patterns 15 0 Pattern 64 00FCH Pattern 63 00F8H Pattern 3 0008H Pattern 2 0004H Pattern 1 0000H 15 0 Pattern 128 Pattern 127 00FCH Pattern 126 Pattern 125 00F8H Pattern 6 Pattern 5 0008H Patter...

Page 932: ...CMP1 value Example When TPBAnCMP1 08H TPBAnBUF08 3 When TPBAnDPS 1 and the TPBAnCNT1 an odd number The applicable register is found by the formula TPBAnCNT1 2 Example When TPBAnCNT1 07H 07H 02H 03H TPBAnBUF03 lower 8 bits 4 When TPBAnDPS 1 and the TPBAnCNT1 an even number The applicable register is found by the formula TPBAnCNT1 2 01H Example When TPBAnCNT1 08H 08H 02H 01H 03H TPBAnBUF03 upper 8 b...

Page 933: ...level at the same time the counting begins TPBAnCNT1 is incremented and points to the address of the buffer in which the subsequent duty value is stored The output is set to the inactive level by the match of the 16 bit counter and the TPBAnBUFm buffer register TPBAnCB2 The duty value is then transferred from TPBAnBUFm to the buffer register TPBAnCB2 by the match of the 16 bit counter and the TPBA...

Page 934: ...to TPBAnTT Table 16 22 Functions of Compare Registers Register Rewrite Method Rewrite during Operation Function TPBAnCMP0 Reload Possible Setting period TPBAnCMP1 Reload Possible Setting number of patterns TPBAnBUFm Rewrite at any time Possible Setting duty TPBAnTOL Reload Possible Setting output level Table 16 23 Timer Output Function Pin Function TPBnO When output is enabled TPBAnTOE 01H PWM out...

Page 935: ...h the buffer register TPBAnCB2 Table 16 26 Example of Setting Each Timer Output Condition Pin Item Output Period Output Duty Output Condition Setting Condition TPBnO PWM output TPBAnCMP0 1 count clock Outputs an inactive level throughout one period duty cycle 0 TPBAnBUFm 0000H Outputs an active level of one count clock in one period TPBAnBUFm 0001H Outputs an inactive level of one count clock in o...

Page 936: ...nt clock period Note 2 Writing 1 to TPBAnRDT 2 4 3 3 0 2 3 0 1 2 0 1 2 3 3 2 4 A pattern B pattern C pattern B pattern duty setting period C pattern duty setting period FFFFH 16 bit counter 0000H TPBAnTE TPBAnCMP0 TPBAnCB0 TPBAnCNT1 TPBAnCMP1 TPBAnCB1 TPBAnBUFm TPBAnCB2 TPBAnRSF TPBnO pin INTTPBAnIPRDI interrupt INTTPBAnIDTY interrupt INTTPBAnIPAT interrupt D10 D00 D11 D12 D13 D20 D21 D01 D22 D30 ...

Page 937: ... Writing 1 to TPBAnRDT0 Note 3 Writing 1 to TPBAnRDT1 2 4 3 3 0 1 2 3 0 1 2 0 1 2 16 bit counter D12 D32 3 4 B pattern C pattern B pattern duty setting period C pattern duty setting period INTTPBAnIPAT interrupt INTTPBAnIDTY interrupt INTTPBAnIPRD interrupt TPBnO pin TPBAnRSF1 flag TPBAnRSF0 flag TPBAnCB2 TPBAnBUFm A pattern TPBAnCB1 TPBAnCMP1 TPBAnCNT1 TPBAnCB0 TPBAnCMP0 TPBAnTE 0000H FFFFH D10 D...

Page 938: ...the individual base addresses OSTMn_base0 or OSTMn_base1 The OSTMn_base addresses of each OSTMn are listed in the following table Clock supply All OS timers provide one clock input Interrupts The OS timers can generate the following interrupt requests Table 17 1 Instances of OS timer OS Timer Instances 2 Name OSTMn Table 17 2 Register Base Addresses OSTMn OSTMn_base0 Address OSTMn_base1 Address OS...

Page 939: ...on 17 3 1 Clock Signal to Drive Counting Note 2 If you wish to use the synchronous counting start trigger OSTMnTSST refer to Section 24 4 1 Simultaneous Start Trigger Function Table 17 5 OSTMn I O Signals OSTNn Signals Function Connected to OSTM0TTOUT OS timer output OSTM0O OSTM1TTOUT OSTM1O Table 17 6 OSTMn Signal Processing OSTNn Signals Function Connected to OSTMnTCKE Enabling the counter clock...

Page 940: ... starting of the timers is possible The following block diagram shows the main components of the OS timer Figure 17 1 Block Diagram of the OS Timer OSTMnCNT OSTMnTE OSTMnTS OSTMnCTL OSTMnTOE OSTMnTO OSTMnTINT OSTMnTTOUT OSTMnTSST PIC function OSTMnCMP OSTMnTCKE IC0CKSELn register OSTMnTT Counter clock control Counter clock 32 bit counter Enabling counting Match INT generator Start trigger control ...

Page 941: ...f IC0KSELn IC0TMEN0 is set to 1 counting of cycles of the selected clock signal from TAUB or TAUJ is selected This is illustrated in the following figures Figure 17 2 Counter Operation with the High Level on OSTMnTCKE IC0KSELn IC0TMEN0 0 Figure 17 3 Counter Operation with OSTMnTCKE Set to the High Level in Every 3rd Cycle of PCLK IC0KSELn IC0TMEN0 1 Each OSTM is capable of intermittent operation w...

Page 942: ...ELn IC0TMENn bit to 1 Caution 3 If TAUBn or TAUJn is selected as the source of a counter clock enable signal for OSTMn the IC0CKSELn IC0TMENn bit is 1 do not change the operation of TAUBn or TAUJn while the OSTMn is operating the OSTMnTE OSTMnTE bit is 1 Setting procedure 1 Confirm that the OSTMnTE OSTMnTE bit is 0 OSTMn operation is stopped 2 Set the IC0CKSELn IC0CKSELn 13 0 bits to select a coun...

Page 943: ... is generated Both output modes are illustrated in the following figure Figure 17 4 Timing Diagram of Output Modes The above timing diagram shows the following operations In software control mode the level of the OSTMnTTOUT output changes in accord with the value set in the OSTMnTO OSTMnTO bit In timer output toggling mode the value of the OSTMnTO OSTMnTO bit and level of the OSTMnTTOUT output are...

Page 944: ...counter This is controlled by the OSTMnCTL OSTMnMD0 bit Since OSTMnTINT triggers toggling of the OSTMnTTOUT output in timer output toggling mode OSTMnTOE OSTMnTOE is 1 the setting of the OSTMnCTL OSTMnMD0 bit also affects the output OSTMnTTOUT This is illustrated in the following figure Figure 17 5 Generating an Interrupt When Counting Starts OSTMnTS or OSTMnTSST OSTMnTE OSTMnTINT OSTMnTTOUT OSTMn...

Page 945: ...he counter is stopped values in the OSTMnTO and OSTMnCNT registers and the level of the OSTMnTTOUT output are retained until further counting operations start Synchronous start The OSTMnTSST signal output from the PIC module can be used to start multiple timers at the same time Refer to Section 24 Peripheral Interconnection PIC Initialization To initialize interval timer mode and free running comp...

Page 946: ... is rewritten during count operation the counter loads the new OSTMnCMP value when the next 0000 0000H is reached Then the counter continues with the new value Periods of OSTMnTINT and OSTMnTTOUT output The periods of OSTMnTINT and OSTMnTTOUT output are as follows OSTMnTINT generation period counter clock period OSTMnCMP 1 OSTMnTTOUT output period OSTMnTINT generation period 2 The following figure...

Page 947: ... toggled The OSTMnCNT register contains the current value as the counter 2 When the counter reaches 0000 0000H an OSTMnTINT interrupt request is generated and the OSTMnTTOUT output is toggled The counter loads the new initial value from OSTMnCMP and continues counting down 3 When the counter is stopped OSTMnTT OSTMnTT 1 the OSTMnTE OSTMnTE bit is cleared to indicate disabling of the counter The co...

Page 948: ... Diagram for a Forced Restart in Interval Timer Mode Operations shown in the above timing diagram are as follows 1 The counter is started and stopped as shown in and described under Figure 17 6 Timing Diagram of OS Timer in Interval Timer Mode 2 Writing OSTMnTS OSTMnTS 1 or placing the high level on OSTMnTSST if the synchronous start trigger is in use forcibly restarts the counter while counting i...

Page 949: ...s are enabled OSTMnCTL OSTMnMD0 1 and output on OSTMnTTOUT is in timer output toggling mode OSTMnTOE OSTMnTOE 1 Figure 17 8 Timing Diagram for Operations When OSTMnCMP 0000 0000H in Interval Timer Mode PCLK Is Selected as the Counter Clock i e OSTMnTCKE Is High The timing diagram above shows the following 1 The counter is reloaded with the value in OSTMnCMP as soon as it starts counting so the val...

Page 950: ...unning Comparison Mode The timing diagram above shows the following 1 The counter starts counting when OSTMnTS OSTMnTS 1 or when OSTMnTSST is high if the synchronous start trigger is in use The OSTMnTE OSTMnTE bit is set to indicate enabling of the counter The counter counts up from 0000 0000H to FFFF FFFFH The OSTMnCNT register is the counter so it contains the current value 2 When the current co...

Page 951: ... Free Running Comparison Mode Forced restart Forced restarting does not proceed during counting even if the OSTMnTS OSTMnTS bit is set or if OSTMnTSST is high when the synchronous start trigger is in use The counter ignores the attempted setting and continues counting Table 17 7 OSTMnTINT Generation Timing OldValue for Compari son New Value for Compari son Counter Value at the Time of Rewriting Pe...

Page 952: ...ce the counter starts it counts up from 0000 0000H to FFFF FFFFH 2 An OSTMnTINT interrupt request is generated when counting starts and the OSTMnTTOUT output is toggled 3 The OSTMnTTOUT output is toggled A comparison interrupt is only generated if the current value of the counter matches that in the OSTMnCMP register Note When PCLK is selected as the counter clock OSTMnTCKE is high and the value f...

Page 953: ...STM compare register OSTMnCMP OSTMn_base1 OSTM counter register OSTMnCNT OSTMn_base1 4H OSTM output register OSTMnTO OSTMn_base1 8H OSTM output enable register OSTMnTOE OSTMn_base1 CH OSTM count enable status register OSTMnTE OSTMn_base1 10H OSTM count start trigger register OSTMnTS OSTMn_base1 14H OSTM count stop trigger register OSTMnTT OSTMn_base1 18H OSTM control register OSTMnCTL OSTMn_base0 ...

Page 954: ...2 bit units Address OSTMn_base1 Initial value 0000 0000H This register is initialized by a reset from any source 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 OSTMnCMP 31 16 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OSTMnCMP 15 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Table 17 9 OSTMnCMP Register Contents Bit Po...

Page 955: ...espondence between operating mode counting direction and initial value The initial value is the value read from the counter after a change to the operating mode Note Value after reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 OSTMnCNT 31 16 R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OSTMnCNT 15 0 R R R R R R R R R R R R R R R R Table 17 10 OSTMnCNT Register Content...

Page 956: ...r is readable writable in 8 bit units Address OSTMn_base1 CH Initial value 00H This register is initialized by a reset from any source 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 OSTMnTO R R R R R R R R W Table 17 12 OSTMnTO Register Contents Bit Position Bit Name Function 0 OSTMnTO For specifying or reading the level of the OSTMnTTOUT output signal 0 Low level 1 High level 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 OSTMn T...

Page 957: ...arted it restarts counting down from the value in the OSTMnCMP register if it is in interval timer mode or restarts counting up from the counter value 0000 0000H if it is in free running comparison mode 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 OSTMnTE R R R R R R R R Table 17 14 OSTMnTE Register Contents Bit Position Bit Name Function 0 OSTMnTE This bit indicates whether the counter is enabled or disabled 0 ...

Page 958: ...his register is initialized by a reset from any source 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 OSTMnTS R R R R R R R W Table 17 15 OSTMnTS Register Contents Bit Position Bit Name Function 0 OSTMnTS This bit starts the counter 0 No function 1 Starts the counter and sets OSTMnTE OSTMnTE 1 In interval timer mode a forced restart is executed if this bit is set while OSTMnTE OSTMnTE 1 In free running comparison ...

Page 959: ...he counter is disabled OSTMnTE OSTMnTE 0 Address OSTMn_base0 20H Initial value 00H This register is initialized by a reset from any source 7 6 5 4 3 2 1 0 0 0 0 0 0 0 OSTMn MD1 OSTMn MD0 R R R R R R R W R W Table 17 17 OSTMnCTL Register Contents Bit Position Bit Name Function 1 OSTMnMD1 Specifies the operating mode for the counter 0 Interval timer mode 1 Free running comparison mode 0 OSTMnMD0 Con...

Page 960: ...s the counter clock enable signal for the OSTM0 PCLK is selected as the counter clock 1 Input the counter clock enable signal selected by IC0TMSEL00 and IC0TMSEL01 to OSTM0 13 12 IC0TMSEL00 IC0TMSEL01 According to the setting these bits select the timer signal indicated below as the counter clock enable signal from among the counter clock enable signals selected by bits 11 to 0 IC0TMSEL01 IC0TMSEL...

Page 961: ...ELn IC0TMENn bit to 1 Caution 3 If TAUBn or TAUJn is selected as the source of a counter clock enable signal for OSTMn the IC0CKSELn IC0TMENn bit is 1 do not change the operation of TAUBn or TAUJn while the OSTMn is operating the OSTMnTE OSTMnTE bit is 1 Setting procedure 1 Confirm that the OSTMnTE OSTMnTE bit is 0 OSTMn operation is stopped 2 Set the IC0CKSELn IC0CKSELn 13 0 bits to select a coun...

Page 962: ... the high level as the counter clock enable signal for the OSTM1 1 Input the counter clock enable signal selected by IC0TMSEL10 and IC0TMSEL11 to OSTM1 13 12 IC0TMSEL10 IC0TMSEL11 According to the setting these bits select the timer signal indicated below as the counter clock enable signal from among the counter clock enable signals selected by bits 11 to 0 IC0TMSEL11 IC0TMSEL10 Description 0 0 TA...

Page 963: ...ELn IC0TMENn bit to 1 Caution 3 If TAUBn or TAUJn is selected as the source of a counter clock enable signal for OSTMn the IC0CKSELn IC0TMENn bit is 1 do not change the operation of TAUBn or TAUJn while the OSTMn is operating the OSTMnTE OSTMnTE bit is 1 Setting procedure 1 Confirm that the OSTMnTE OSTMnTE bit is 0 OSTMn operation is stopped 2 Set the IC0CKSELn IC0CKSELn 13 0 bits to select a coun...

Page 964: ... edges refers to both rising and falling edges Register addresses All ENCAn register addresses are given as address offsets to the individual base address ENCAn_base The base address ENCAn_base of each ENCAn is listed in the following table Clock supply The following clock input is provided to each ENCAn That is each ENCAn is connected to the PCLK Table 18 1 Instances of ENCA Encoder Timer Instanc...

Page 965: ...rrupt controller DMA INTENCAnI0 Compare match 0 or capture 0 interrupt Interrupt controller DMA INTENCAnI1 Compare match 1 or capture 1 interrupt Interrupt controller DMA INTENCAnIEC Interrupt to indicate clearing due to clearing input from the encoder Interrupt controller DMA Table 18 5 List of ENCAn Input Signals ENCAn Signals Function Connected to ENCAnI0 ENCAn capture trigger input 0 ENCAnI1 E...

Page 966: ...can be set separately for capture operation and for compare operation Interrupt masking function for masking the output of interrupt signals as a result of a match in judgment by comparison Function for loading the value of the capture compare register to the counter when the latter underflows An input signal from an encoder can be applied as the clearing condition for the timer counter Edge or le...

Page 967: ...1 ENCAnl1 encoder capture trigger input 1 ENCAnI0 encoder capture trigger input 0 ENCAnEC encoder clearing input signal ENCAnE0 encoder input 0 ENCAnE1 encoder input 1 Capture 1 Capture 0 ENCAnCCR0 capture compare ENCAnCCR0 capture compare ENCAnLDE ENCAnECM0 ENCAnCRM1 ENCAnCTS ENCAnTS ENCAnTT ENCAnACL ENCAnCLOV ENCAnOVF ENCAnUFD ENCAnCSF ENCAnCLUD ENCAnCNT ENCAnBCL ENCAnZCL ENCAnSCE ENCAnTE ENCAnT...

Page 968: ... register 0 ENCAnCCR0 ENCAn_base1 ENCAn capture compare register 1 ENCAnCCR1 ENCAn_base1 04H ENCAn counter register ENCAnCNT ENCAn_base1 08H ENCAn status flag register ENCAnFLG ENCAn_base1 0CH ENCAn status flag clear register ENCAnFGC ENCAn_base1 10H ENCAn timer enable status register ENCAnTE ENCAn_base1 14H ENCAn timer start trigger register ENCAnTS ENCAn_base1 18H ENCAn timer stop trigger regist...

Page 969: ...M1 0 Caution 2 While the ENCAnCME bit is set to 1 setting ENCAnECM1 to 1 is prohibited 14 ENCAnMCS This bit is used to select the trigger for canceling masking of compare 1 match interrupt detection when the compare function by ENCAnCCR1 register is used 0 Masking of compare match interrupt detection is canceled when the ENCAnCCR1 register is written 1 Masking of compare match interrupt detection ...

Page 970: ...he ENCAnCCR0 register is not loaded to the counter when the counter underflows regardless of the value of the ENCAnLDE bit 3 ENCAnECM1 This bit is used to select or deselect counter clearing upon matches between the values in the counter and in register ENCAnCCR1 0 The counter is not cleared to 0000H 1 The counter is cleared to 0000H if the next step in counting is counting down Caution The settin...

Page 971: ...ill be down if ENCAnE1 is high and up if ENCAnE1 is low 0 1 Detection of a valid edge in the ENCAnE0 encoder input causes counting up Detection of a valid edge in the ENCAnE1 encoder input causes counting down 1 0 A rising edge of the ENCAnE0 encoder input causes counting down A falling edge of the ENCAnE0 encoder input causes counting up However counting in either direction only proceeds when ENC...

Page 972: ...er Contents Bit Position Bit Name Function 3 2 ENCAnTIS3 ENCAnTIS2 Selects the valid edge of capture trigger 1 ENCAnl1 ENCAn TIS3 ENCAn TIS2 Operation 0 0 Neither edge is detected 0 1 Rising edges are detected 1 0 Falling edges are detected 1 1 Both edges are detected Caution Settings in these bits are only valid when ENCAnCTL ENCAnCRM1 1 and ENCAnCTS 0 The settings are invalid with any other sett...

Page 973: ...ring condition causes clearing When ENCAnSCE 0 settings of the ENCAnZCL ENCAnACL and ENCAnBCL bits become ineffective and settings of the ENCAnECS1 and ENCAnECS0 bits become effective The counter is cleared to 0000H when ENCAnSCE 1 and the clearing conditions set in the ENCAnZCL ENCAnACL and ENCAnBCL bits are all matched settings of the ENCAnECS1 and ENCAnECS0 bits become ineffective Caution When ...

Page 974: ...ed Caution These bits are valid when ENCAnSCE bit 0 1 0 ENCAnEIS1 ENCAnEIS0 These bits set the valid edge for input signals from the encoder signals on the ENCAnE0 and ENCAnE1 pins ENCAn EIS1 ENCAn EIS0 Operation 0 0 Neither edge is detected 0 1 Rising edges are detected 1 0 Falling edges are detected 1 1 Both edges are detected Caution These bits are valid when the ENCAnUDS1 and ENCAnUDS0 bits ar...

Page 975: ...rated if the ENCAnUDF flag is set to 1 Setting condition An underflow during encoder timer counter operations causes setting of this flag to 1 Clearing condition Writing 1 to the ENCAnCLUD bit of the ENCAnFGC register setting the ENCAnTS bit to 1 while the ENCAnTE bit 0 or input of the synchronous start trigger signal ENCAnTSST signal at the high level causes clearing of this flag to 0 Caution Thi...

Page 976: ...egister always returns 00H when read Address ENCAn_base1 10H Initial value 00H A reset from any source will initialize the bits 7 6 5 4 3 2 1 0 0 0 0 0 0 0 ENCAn CLUD ENCAn CLOV R R R R R R W W Table 18 11 ENCAnFGC Register Contents Bit Position Bit Name Function 1 ENCAnCLUD This bit clears the underflow flag 0 Invalid 1 Clears ENCAnUDF of the ENCAnFLG register clears underflow detection 0 ENCAnCL...

Page 977: ...Address ENCAn_base1 00H Initial value 0000H A reset from any source will initialize the bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENCAnCCR0 15 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Table 18 12 ENCAnCCR0 Register Contents Bit Position Bit Name Function 15 to 0 ENCAn CCR0 15 0 If ENCAnCTL ENCAnCRM0 0 ENCAnCCR0 is comparison register Set the value to be compared with the ...

Page 978: ...s invalid Address ENCAn_base1 04H Initial value 0000H A reset from any source will initialize the bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENCAnCCR1 15 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Table 18 13 ENCAnCCR1 Register Contents Bit Position Bit Name Function 15 to 0 ENCAn CCR1 15 0 If ENCAnCTL ENCAnCRM1 0 ENCAnCCR1 is comparison register Set the value to be compared...

Page 979: ...urce will initialize the bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENCAnCNT 15 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Table 18 14 ENCAnCNT Register Contents Bit Position Bit Name Function 15 to 0 ENCAnCNT 15 0 Operation of counter register ENCAnTE Counter Status Operation 0 Stopped initial setting Set a given value to timer counter register 0 1 Starting operation Start ...

Page 980: ...nitialize the bits 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 ENCAn TE R R R R R R R R Table 18 15 ENCAnTE Register Contents Bit Position Bit Name Function 0 ENCAnTE This is a status bit that indicates the operation enabled stopped status of the encoder timer 0 Operation stopped status 1 Operation enabled status Clearing condition This bit is cleared to 0 when 1 is written to ENCAnTT ENCAnTT Setting condition ...

Page 981: ...ys returns 00H when read Writing to this register is only valid when ENCAnTE ENCAnTE 0 Address ENCAn_base1 18H Initial value 00H A reset from any source will initialize the bits 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 ENCAn TS R R R R R R R W Table 18 16 ENCAnTS Register Contents Bit Position Bit Name Function 0 ENCAnTS This is the trigger bit for placing the encoder timer in the operation enabled state 0 I...

Page 982: ... be read written in 8 bit units This register always returns 00H when read Address ENCAn_base1 1CH Initial value 00H A reset from any source will initialize the bits 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 ENCAn TT R R R R R R R W Table 18 17 ENCAnTT Register Contents Bit Position Bit Name Function 0 ENCAnTT This is the trigger bit for stopping ENCAn operations 0 Invalid 1 Operation is stopped ENCAnTE ENCAn...

Page 983: ...re registers 18 4 1 Timer Counter Operation Operations of the encoder timer are described below The figure below shows the basic operations For detailed descriptions of the individual types of operation refer to the corresponding passages Figure 18 2 Timer Counter Initial Value Setting Start Stop ENCAnTS bit ENCAnTE bit ENCAnTT bit 16 bit counter ENCAnCNT INTENCAnIOV interrupt INTENCAnIUD interrup...

Page 984: ...up Writing 1 to the timer start trigger bit ENCAnTS ENCAnTS causes setting of the timer status enable bit ENCAnTE ENCAnTE to 1 enables counting and counting proceeds upon detection of a valid edge in the input signal from the encoder Condition for Use ENCAnCCR0 Register ENCAnCCR1 Register Only comparison is in use encoder comparison mode Comparison function Comparison function Comparison and captu...

Page 985: ...lue increases from FFFEH to FFFFH 2 From label 2 the counter overflows when its value changes from FFFFH to 0000H At the same time an overflow interrupt is output and the overflow flag is set to 1 3 Label 3 indicates the method for clearing of the overflow flag i e the overflow flag is cleared to 0 by setting ENCAnFGC ENCAnCLOV to 1 Alternatively the overflow flag may be cleared by setting ENCAnTS...

Page 986: ...e time an underflow interrupt is output setting the underflow flag to 1 3 Label 3 indicates the method for clearing of the underflow flag i e the underflow flag is cleared to 0 by setting ENCAnFGC ENCAnCLUD to 1 Alternatively the underflow flag may be cleared by setting ENCAnTS ENCAnTS to 1 while ENCAnTE ENCAnTE 0 or by placing the signal input as ENCAnTSST synchronous start trigger at the high le...

Page 987: ...eeds when the valid edges of the signals on ENCAnE0 and ENCAnE1 match The timing chart below shows counting operation when ENCAnCTL ENCAnUDS 1 0 00B Figure 18 5 Counting Operation when ENCAnCTL ENCAnUDS 1 0 00B ENCAnUDS1 ENCAnUDS0 Operation Description Signal on the ENCAnE0 Pin Signal on the ENCAnE1 Pin Counting Operation 0 0 Rising edge High level Counting down Falling edge Both edges Rising edge...

Page 988: ...TL ENCAnUDS 1 0 01B Figure 18 6 Counting Operation of ENCAnCTL ENCAnUDS 1 0 01B ENCAnUDS1 ENCAnUDS0 Description of Operation Signal on the ENCAnE0 Pin Signal on the ENCAnE1 Pin Counting Operation 0 1 Low level Rising edge Counting down Falling edge Both edges High level Rising edge Falling edge Both edges Rising edge Low level Counting up Falling edge Both edges Rising edge High level Falling edge...

Page 989: ...al on the ENCAnE0 Pin Signal on the ENCAnE1 Pin Counting Operation 1 0 Rising edge Low level Counting down Rising edge Falling edge Falling edge Low level Counting up Falling edge Falling edge Low level Rising edge Retaining Rising edge Rising edge High level Rising edge Falling edge Rising edge Low level Falling edge Rising edge High level High level Falling edge Falling edge High level ENCAnUDS ...

Page 990: ...B ENCAnUDS1 ENCAnUDS0 Description of Operation Signal on the ENCAnE0 Pin Signal on the ENCAnE1 Pin Counting Operation 1 1 Low level Falling edge Counting down Rising edge Low level High level Rising edge Falling edge High level Rising edge High level Counting up High level Falling edge Falling edge Low level Low level Rising edge Simultaneous input Retaining ENCAnUDS 1 0 11B ENCAnE0 pin ENCAnE1 pi...

Page 991: ...al when ENCAnIOC1 ENCAnSCE 0 Upon detection of the valid edge of ENCAnEC the timer counter is cleared to 0000H in synchronization with the operation clock The valid edge of ENCAnEC is specified by the setting of the ENCAnECS1 and ENCAnECS0 bits in the ENCAnIOC1 register The settings of the ENCAnZCL ENCAnBCL and ENCAnACL bits in the ENCAnIOC1 register are ineffective A clear interrupt signal INTENC...

Page 992: ...apture proceeds on the rising edge of the trigger signal input on the ENCAnEC pin 2 Clearing of the counter s value to 0000H in response to the input on the ENCAnEC pin proceeds 3 The pre clearing value from the counter 0002H is captured in the ENCAnCCR1 register on the rising edge of the input signal on the ENCAnEC pin 4 The cleared interrupt INTENCAnIEC and capture interrupt INTENCAnI1 in respon...

Page 993: ...are detected and the timer counter is cleared to 0000H in synchronization with the operating clock The setting of the ENCAnIOC1 ENCAnECS 1 0 bits is ineffective The encoder cleared interrupt signal INTENCAnIEC is output simultaneously with the timer counter clearing Conditions for clearing of the timer counter in accord with the setting of the ENCAnZCL ENCAnBCL and ENCAnACL bits in the ENCAnIOC1 r...

Page 994: ...IOC1 ENCAnZCL 1 and ENCAnCTL ENCAnUDS 1 0 11B Figure 18 11 Timing of Clearing when Input on the ENCAnEC Pin Follows Input on the ENCAnE1 Pin during Counting up ENCAnCNT register INTENCAnI0 interrupt ENCAnE0 pin ENCAnE1 pin ENCAnEC pin ENCAnCCR0 register INTENCAnI1 interrupt ENCAnCCR1 register PCLK register Counter clock Clearing signal H L 0 m m 1 0 m 1 H Setting of ENCAnCCR0 m 1 Setting of ENCAnC...

Page 995: ... and ENCAnE1 Pins Coincides during Counting up c When Input on the ENCAnEC Pin Precedes Input on the ENCAnE1 Pin during Counting up When ENCAnIOC1 ENCAnACL 1 ENCAnIOC1 ENCAnBCL 0 ENCAnIOC1 ENCAnZCL 1 and ENCAnCTL ENCAnUDS 1 0 11B Figure 18 13 Timing of Clearing when Input on the ENCAnEC Pin Precedes Input on the ENCAnE1 Pin during Counting up ENCAnCNT register ENCAnE0 pin ENCAnE1 pin ENCAnEC pin P...

Page 996: ...ENCAnIOC1 ENCAnZCL 1 and ENCAnCTL ENCAnUDS 1 0 11B Figure 18 14 Timing of Clearing when Input on the ENCAnEC Pin Follows Input on the ENCAnE1 Pin during Counting down ENCAnCNT register ENCAnE0 pin ENCAnCCR0 register INTENCAnI0 interrupt ENCAnCCR1 register INTENCAnI1 interrupt ENCAnE1 pin ENCAnEC pin PCLK Counter clock Clearing signal H L 0 m H m 1 m 1 0 Setting of ENCAnCCR0 m 1 Setting of ENCAnCCR...

Page 997: ... in synchronization with the operating clock PCLK upon a compare match if further counting is to be counting up When ENCAnCTL ENCAnLDE 1 Upon occurrence of an underflow the setting value of the ENCAnCCR0 register is loaded to the timer counter An underflow interrupt INTENCAnIUD is output ENCAnCCR0 Function Compare Match Clear Control Next Counting Operation Timer Counter Clearing Upon Compare Matc...

Page 998: ...1 ENCAnTIS1 and ENCAnTIS0 01B 2 Counting down proceeds at label 2 3 At label 3 a rising edge of the input signal on the ENCAnI0 pin is detected and the value reached by the counter is captured in the ENCAnCCR0 register 4 At label 4 the interrupt signal INTENCAnI0 that corresponds to capture to the ENCAnCCR0 register is output PCLK ENCAnCNT register INTENCAnI0 interrupt INTENCAnI1 interrupt ENCAnCC...

Page 999: ...en masked for the second and subsequent compare matches When ENCAnCTL ENCAnMCS 0 writing to the ENCAnCCR1 register disables masking of compare 1 match interrupt detection When ENCAnCTL ENCAnMCS 1 clearing of the timer counter due to input on the ENCAnEC pin or a match between the value in the ENCAnCCR0 register and the timer counter disables masking of compare 1 match interrupt detection When ENCA...

Page 1000: ...ENCAnCME ENCAnMCS Underflow Occurrence upon ENCAnLDE 0 0 Compare 0 Masking disabled Setting invalid Outputs compare 1 match interrupt upon each compare match 1 Masking enabled 0 Writing to ENCAnCCR1 Occurred Loading of ENCAnCCR0 to timer counter Outputs compare 1 match interrupt once upon the first compare match Interrupts are masked for the second and subsequent matches until the cancel trigger o...

Page 1001: ...pin is detected and the value reached by the counter is captured in the ENCAnCCR1 register 4 At label 4 the interrupt signal INTENCAnI1 that corresponds to capture to the ENCAnCCR1 register is output PCLK ENCAnCNT register INTENCAnI0 interrupt INTENCAnI1 interrupt ENCAnCCR1 register ENCAnTIS 3 2 ENCAnCRM1 bit ENCAnI1 pin Input on the ENCAnI1 pin rising ENCAnCSF flag Counter clock H counting up H c...

Page 1002: ...er continues counting operation Counting down Does not clear timer counter continues counting operation Does not clear timer counter continues counting operation 01 Counting up Does not clear timer counter continues counting operation Clears timer counter to 0000H Counting down Does not clear timer counter continues counting operation Does not clear timer counter continues counting operation 10 Co...

Page 1003: ...ng the Timer in a Single Encoder Timer Configuration Operation can be started by setting ENCAnTE ENCAnTS 1 2 Stopping an Encoder Timer The timer is stopped by setting ENCAnTT ENCAnTT 1 and ENCAnTE ENCAnTE 0 In a single encoder timer configuration setting the ENCAnTT ENCAnTT bit to 1 changes the value of the ENCAnTE bit to 0 and thus stops the timer ...

Page 1004: ...his register the ENCAnTS bit is set to 1 the counter operation starts from the set count value The set value is set as the initial value of the counter register Operation start Perform the counter operation start setting Set the ENCAnTS bit to 1 Counting is started in this state The value of the ENCAnTE bit indicating the state of operation is 1 and the counter clock is supplied to the internal ci...

Page 1005: ...s can be set to 00B 01B 10B or 11B While ENCAnSCE 1 setting the ENCAnUDS 1 0 bits to 00B or 01B is prohibited but setting the ENCAnUDS 1 0 bits to 10B or 11B is possible Set the level of the clearing input signal from the encoder on the ENCAnEC pin Set the level of the clearing input signal from the encoder on the ENCAnE0 pin Set the level of the clearing input signal from the encoder on the ENCAn...

Page 1006: ...alue of the ENCAnCCR1 register and the value of the counter Enable or disable masking of compare match interrupts Disable masking of compare match interrupt detection Set the trigger for capture to the ENCAnCCR1 register 0 capture trigger 1 1 ENCAnEC input Set the valid edge of capture trigger 1 ENCAnT1 input Refer to the ENCAnIOC1 register settings in section 18 5 1 2 Initial Setting Procedure fo...

Page 1007: ... Mode 1 A compare match interrupt INTENCAnI0 is generated when the values of the counter and register ENCAnCCR0 D0 match If further counting is upwards the counter is cleared to 0000H because ENCAnECM0 1 A compare match interrupt INTENCAnI1 is generated when the values of the counter and register ENCAnCCR1 D1 match Counter clearing due to a match with ENCAnCCR1 does not proceed because ENCAnECM1 0...

Page 1008: ...on Mode 2 A compare match interrupt INTENCAnI0 is generated when the values of the counter and register ENCAnCCR0 D0 match Counter clearing due to matching with ENCAnCCR0 does not proceed because ENCAnECM0 0 A compare match interrupt INTENCAnI1 is generated when the values of the counter and register ENCAnCCR1 D1 and D2 match Counter clearing due to matching with ENCAnCCR1 does not proceed because...

Page 1009: ... counter is cleared ENCAnCTL ENCAnLDE 0 The counter is not loaded with the value from the ENCAnCCR0 register Figure 18 19 Timing of Basic Encoder Operation 3 Encoder Comparison Mode 3 A compare match interrupt INTENCAnI0 is generated when the values of the counter and register ENCAnCCR0 D0 match If further counting is upwards the counter is cleared to 0000H because ENCAnECM0 1 A compare match inte...

Page 1010: ...0 ENCAnTIS 1 0 01B Selects detection of rising edges of the signal on the ENCAnI0 pin Figure 18 20 Timing of Basic Encoder Operation 4 Encoder Capture Mode The detection of a rising edge on the ENCAnI0 pin leads to storage of the counter value in the capture register ENCAnCCR0 and the generation of a capture interrupt INTENCAnI0 The detection of a rising edge on the ENCAnI1 pin leads to storage of...

Page 1011: ... is cleared when its value matches that of the ENCAnCCR0 register ENCAnCTL ENCAnLDE 1 When the counter underflows it is loaded with the value from the ENCAnCCR0 register ENCAnIOC1 ENCAnSCE 0 ENCAnECS 1 0 00B ENCAnIOC0 ENCAnTIS 3 2 11B Selects detection of both edges of the signal on the ENCAnI1 pin Figure 18 21 Timing of Basic Encoder Operation 5 Encoder Capture and Comparison Mode ENCAnCCR0 regis...

Page 1012: ...because ENCAnECM0 1 The detection of both edges on the ENCAnI1 pin leads to storage of the counter value in the capture register ENCAnCCR1 and the generation of a capture interrupt INTENCAnI1 An underflow interrupt INTENCAnIUD is generated when the counter underflows ENCAnLDE 1 so the counter is loaded with the value from the ENCAnCCR0 register D0 when the counter underflows ENCAnLDE 1 and ENCAnEC...

Page 1013: ...x n n 0 2 For example TAPAnFLG indicates the TAPAn flag registers Register addresses All TAPAn register addresses are given as address offsets from the given base address TAPAn_base0 or TAPAn_base1 Each of the TAPAn base addresses is listed in the following table Clock supply The following clock signal is input to the timer option Table 19 1 Instances of Timer Option Modules Timer Option Instances...

Page 1014: ... TAPAn Signals Function Connected to TAPA0 TAPA0TIPEK0 TAPA0 peak interrupt INTTAPA0IPEK0 signal for the interrupt controller TAPA0TIPEK1 TAPA0 peak interrupt TAPA0TIVLY0 TAPA0 valley interrupt INTTAPA0IVLY0 signal for the interrupt controller TAPA0TIVLY1 TAPA0 valley interrupt TAPA2 TAPA2TIPEK0 TAPA2 peak interrupt TAPA2TIPEK1 TAPA2 peak interrupt TAPA2TIVLY0 TAPA2 valley interrupt TAPA2TIVLY1 TA...

Page 1015: ...nal PIC TAPA0TCDENM0 TAUB master channel 0 cycle detection input signal TAPA0TCDENM1 TAUB master channel 1 cycle detection input signal TAPA0TOEM0 TAUB master channel 0 timer enabled input signal TAPA0TOEM1 TAUB master channel 1 timer enabled input signal TAPA0TADOUT0 A D converter trigger output signal 0 ADCA0 TAPA0TADOUT1 A D converter trigger output signal 1 ADCA0 TAPA2 TAPA2THASIN Asynchronous...

Page 1016: ... TAPA TAPA2TOEM0 TAUB master channel 0 timer enabled input signal TAPA2TOEM1 TAUB master channel 1 timer enabled input signal TAPA2TADOUT0 A D converter trigger output signal 0 TAPA2TADOUT1 A D converter trigger output signal 1 Table 19 5 TAPAn Internal Signal 2 2 TAPAn Signals Function Connected to ...

Page 1017: ...Z Control Signal for TAPA0 TAPA0THASIN b Hi Z Control Signal for TAPA2 TAPA2THASIN Figure 19 1 Hi Z Control Signals for TAPA0 and TAPA2 TAPAnTHASIN 0 0 1 0 1 0 0 0 0 0 1 PIC0HIZCENn n 0 1 ESOn ERROROUT INTADCA0ERR TAPA0THASIN 0 0 1 0 1 0 0 1 0 0 0 1 PIC0HIZCEN2 ESO2 INTTSG20IER ERROROUT TAPA2THASIN INTADCA0ERR ...

Page 1018: ...TADCA0TERR interrupt signal and ERROROUT signal is selected select the rising edge TAPA0CTL0 TAPA0DCN TAPA0DCP 01 as the valid edge Note Set undefined bits in PIC0HIZCEN0 to 0 7 6 5 4 3 2 1 0 0 PIC0HIZ CEN06 PIC0HIZ CEN05 0 0 0 0 PIC0HIZ CEN00 R R W R W R R R R R W Table 19 6 Contents of the PIC0HIZCEN0 Register Bit Position Bit Name Function 6 PIC0HIZCEN06 Enables and disables Hi Z output control...

Page 1019: ...selected select the rising edge TAPA2CTL0 TAPA2DCN TAPA2DCP 01 as the valid edge Note Set the undefined bits in PIC0HIZCEN2 to 0 7 6 5 4 3 2 1 0 0 PIC0HIZ CEN26 PIC0HIZ CEN25 0 PIC0HIZ CEN23 0 0 PIC0HIZ CEN20 R R W R W R R W R R R W Table 19 7 Contents of the PIC0HIZCEN2 Register Bit Position Bit Name Function 6 PIC0HIZCEN26 Enables and disables Hi Z output control by the INTADCA0TERR interrupt si...

Page 1020: ...nction Connected to TAPA0 TAPA0THZOUT0 Hi Z control signal 0 phase U Hi Z control of phase U output signal from TAUB0 TOUT10 TOUT11 TAPA0THZOUT1 Hi Z control signal 1 phase V Hi Z control of phase V output signal from TAUB0 TOUT12 TOUT13 TAPA0THZOUT2 Hi Z control signal 2 phase W Hi Z control of phase W output signal from TAUB0 TOUT14 TOUT15 TAPA2 TAPA2THZOUT0 Hi Z control signal 0 Hi Z control of...

Page 1021: ...gnal output by the TAUB provides the basis for the output of two conversion trigger signals for the A D converter 19 2 1 Block Diagram Edge detection circuit TAPAnTHASIN Asynchronous Hi Z control TAPAnDCN TAPAnDCP TAPAnDCM TAPAnHOF2 TAPAnACE TAPAnHOF1 TAPAnHOF0 ashzout TAPAnACTS TAPAnACWE TAPAnTCDENM0 TAPAnTUDCM0 TAPAnTTOEM0 TAPAnTCDENM1 TAPAnTUDCM1 TAPAnTTOEM1 TAPAnOPHS1 TAPAnOPHT0 TAPAnACTT Hi Z...

Page 1022: ... as the valley period and an interrupt generated to indicate this period is defined as a valley interrupt INT VLY The period from a TAUB up status counting up status to generation of an interrupt from the master channel is defined as the peak period and an interrupt generated to indicate this period is defined as a peak interrupt INT PEK Master channel CNT M INT M TOUT INT VLY Valley Valley Valley...

Page 1023: ...ntrol register 0 TAPAnCTL0 TAPAn_base0 20H TAPAn control register 1 n 0 TAPAnCTL1 n 0 TAPAn_base0 24H n 0 TAPAn flag register TAPAnFLG TAPAn_base1 00H TAPAn asynchronous control write enable register TAPAnACWE TAPAn_base1 04H TAPAn asynchronous control start trigger register TAPAnACTS TAPAn_base1 08H TAPAn asynchronous control stop trigger register TAPAnACTT TAPAn_base1 0CH TAPAn Hi Z start trigge...

Page 1024: ... W R W R W R R Table 19 10 Contents of the TAPAnCTL0 Register Bit Position Bit Name Function 4 TAPAnDCM Clearing condition specification bit This control bit specifies the condition for clearing of the Hi Z control outputs 0 Manipulation of TAPAnOPHT0 is enabled regardless of the TAPAnTHASIN signal input level 1 Manipulation of TAPAnOPHT0 is disabled when the TAPAnTHASIN signal input is at the act...

Page 1025: ...t 1 TAPAnTADOUT1 TAPAn ATS3 TAPAn ATS2 Description 0 0 Outputs INT while the master channel is in the down state 0 1 Outputs INT while the master channel is in the up state 1 0 Outputs INT while the master channel is in the down up state 1 1 Outputs INT and a valley interrupt of the master channel TAPAnTIVLYn0 while the master channel is in the down up state 1 0 TAPAn ATS 1 0 A D converter trigger...

Page 1026: ... R R R R R Table 19 12 Contents of the TAPAnFLG Register Bit Position Bit Name Function 10 to 8 TAPAn HOFm TAPAnTHZOUTm output monitor bit m 0 to 2 This bit monitors the TAPAnTHZOUTm output 0 The TAPAnTHZOUTm output is at the low level 1 The TAPAnTHZOUTm output is at the high level 0 TAPAn ACE Asynchronous Hi Z control enable bit This bit indicates the state of asynchronous Hi Z control TAPAnTHASI...

Page 1027: ...ource 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 TAPAn ACWE R R R R R R R R W Table 19 13 Contents of the TAPAnACWE Register Bit Position Bit Name Function 0 TAPAn ACWE Asynchronous control write enable bit This is a write enable bit for asynchronous Hi Z control After 1 has been written to this bit it is automatically cleared to 0 by writing 1 to TAPAnACTS and TAPAnACTT 0 Disables writing to TAPAnACTS and TAP...

Page 1028: ... Initial value 00H This register is initialized by a reset from any source 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 TAPAn ACTT R R R R R R R W Table 19 15 Contents of the TAPAnACTT Bit Position Bit Name Function 0 TAPAn ACTT Asynchronous control stop trigger bit This bit enables the stop trigger for asynchronous Hi Z control The setting of this bit is only valid when TAPAnACWE 1 0 Writing 0 to this bit is ig...

Page 1029: ... always read as 00H Address TAPAn_base1 18H Initial value 00H This register is initialized by a reset from any source 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 TAPAn OPHT0 R R R R R R R W Table 19 17 Contents of the TAPAnOPHT Register Bit Position Bit Name Function 0 TAPAn OPHT0 Hi Z control signal stop trigger 0 bit This bit sets the stop trigger for a Hi Z control signal 0 The read value is 0 and writing 0 ...

Page 1030: ...ntrol by the CPU 2 Overview of Hi Z Control Function The following method is available for controlling Hi Z states Asynchronous input Hi Z control for pin inputs Controls the Hi Z control output signals TAPAnTHZOUT0 phase U TAPAnTHZOUT1 phase V and TAPAnTHZOUT2 phase W asynchronously 3 Hi Z Control and Its Operation Function Operation Asynchronous Hi Z control corresponding to pin input This funct...

Page 1031: ...This module assumes that microcontroller operation may hang when an error occurs To handle such situations external error detection signals are continuously processed so that the motor driving signal can be set to the Hi Z state even if no clock signal is being supplied This module only detects an error as an edge of the error detection signal A fixed output level is not detected as an error the s...

Page 1032: ...rt control for Hi Z output as long as the TAPAnTHZOUT0 output is at the low level TAPAnTHZOUT0 goes to the low level in response to detection of a rising edge of the asynchronous input TAPAnTHASIN TAPAnTHZOUT0 goes to the high level in response to writing 1 to Hi Z stop trigger 0 TAPAnOPHT0 regardless of the level of TAPAnTHASIN Carrier cycle one cycle TAPAnOPHT0 write 1 O Counter Positive phase o...

Page 1033: ... a rising edge of the asynchronous input signal TAPAnTHASIN Writing of 1 to Hi Z stop trigger 0 TAPAnOPHT0 is ignored as long as the asynchronous input signal TAPAnTHASIN is at the active level high because TAPAnDCP 1 After the asynchronous input signal TAPAnTHASIN is switched to the inactive level low because TAPAnDCP 1 TAPAnTHZOUT0 goes to the high level when 1 is written to Hi Z stop trigger 0 ...

Page 1034: ...e Hi Z Stop Trigger TAPAnOPHT during Hi Z Control in Response to Asynchronous Input The Hi Z stop trigger operates as follows TAPAn DCM Operation 0 1 Writing 1 to the TAPAnOPHS0 bit places the TAPAnTHZOUT0 TAPAnTHZOUT1 and TAPAnTHZOUT2 signals at the low level TAPAn DCM Operation 0 Writing 1 to the TAPAnOPHT0 bit places the TAPAnTHZOUT0 TAPAnTHZOUT1 and TAPAnTHZOUT2 signals at the high level 1 If ...

Page 1035: ...ing to TAPAnOPHT0 is ignored as long as TAPAnTHASIN is at the active level high when TAPAnDCN 0 and TAPAnDCP 1 After a falling edge of TAPAnTHASIN is detected TAPAnTHZOUT0 goes to the high level when 1 is written to TAPAnOPHT0 while TAPAnTHASIN is at the inactive level low when DCN 0 and DCP 1 Hi Z control output TAPAnTHZOUT0 Carrier cycle one cycle TAPAnOPHT0 write 1 TAPAnOPHT0 write 1 X TAPAnOPH...

Page 1036: ... Hi Z control of an output from the timer Control is by the TAPAnOPHS0 bit of TAPA Control is by the Hi Z input signal TAPAnTHASIN for TAPA To stop Hi Z control of output from the timer Control is by the TAPAnOPHT0 bit of TAPA if TAPAnDCM 0 TAPAnOPHT0 is used if the Hi Z input signal for TAPA TAPAnTHASIN is at the inactive level if TAPAnDCM 1 The state of TAPA operations can be read from the TAPAn...

Page 1037: ...ut of the TAPAnTIPEK0 signal An TAPAnTSIM0 signal from the master that arrives while the TAPAnTUDCM0 signal from the master channel of the TAUB is at the low level is regarded as a valley interrupt and leads to output of the TAPAnTIVLY0 signal The PIC0REG2n0 register is used to select channel 0 2 or 8 for the TAPAnTSIM0 and TAPAnTUDCM0 signals Timer I O control register 200 PIC0REG200 Access This ...

Page 1038: ... 0 by the PIC function see section 24 Peripheral Interconnection PIC In that case apply the bit definition of the corresponding function Bit Position Bit Name Function 25 24 PIC0REG 20025 PIC0REG 20024 Selects the TAUB channel to be used by TAPAnTSIM0 and TAPAnTUDCM0 0 0 None 0 1 TAUBn channel 0 1 0 TAUBn channel 2 1 1 TAUBn channel 8 ...

Page 1039: ...interrupt and outputs the TAPAnTIPEK0 signal in response The TAPA module handles TAPAnTSIM0 arriving while TAPAnTUDCM0 is low as a valley interrupt and outputs the TAPAnTIVLY0 signal in response Caution Combined circuits handle output of the TAPAnTIPEK0 TAPAnTIVLY0 signals and operate regardless of the operating mode When the TAPAnTIPEK0 TAPAnTIVLY0 signals are not in use they must be controlled b...

Page 1040: ...settings TAUB and TAPA are stopped Initialize the TAUB module Determine the timer operating mode Starting operation Start the TAUB module TAUB starts counting During operation TAUB runs in accord with the settings for the various functions The INT signal output selector outputs a peak interrupt TAPAnTIPEK0 or a valley interrupt TAPAnTIVLY0 for control cycle 0 This is based on interrupt input TAPAn...

Page 1041: ...g the TAPATADOUT Signals Output Signal Up Down Input Slave Match Detection Signal Valley Interrupt Signal TAPAnTADOUT0 TAPAnTUDCM0 TAPAnTCDENS0 TAPAnTIVLY0 TAPAnTADOUT1 TAPAnTUDCM0 TAPAnTCDENS1 TAPAnTIVLY0 Table 19 19 Operation of TAPAnCTL1 TAPAnATS 1 0 and TAPAnTADOUT0 TAPAn ATS1 TAPAn ATS0 Description 0 0 The INT signal from slave 0 is output as TAPAnTADOUT0 while master 0 of the TAUB module is ...

Page 1042: ...PAnATS 0 0 INT Output while Master Channel is in the Down State An INT signal from the slave while the master is in the down state is output as a trigger to start conversion by the A D converter An INT signal from the slave while the master is in the up state is not output Carrier cycle TAPAnTADOUT0 TAPAnTUDCM0 up down Positive phase output timer Negative phase output timer TAPAnTIVLY0 TAPAnTCDENS...

Page 1043: ... to start conversion by the A D converter An INT signal from the slave while the master is in the down state is not output Figure 19 6 TAPAnATS 1 0 INT Output while Master Channel is in either the Down or Up State Carrier cycle TAPAnTADOUT0 TAPAnTUDCM0 up down Positive phase output timer Negative phase output timer TAPAnTIVLY0 TAPAnTCDENS0 Carrier cycle TAPAnTADOUT0 TAPAnTUDCM0 up down Positive ph...

Page 1044: ...on by the A D converter Figure 19 7 TAPAnATS 1 1 Output of INT and Valley Interrupt while Master Channel is in either the Down or Up State An INT signal or valley interrupt signal from the slave is output as a trigger to start conversion by the A D converter Carrier cycle TAPAnTADOUT0 TAPAnTUDCM0 up down Positive phase output timer Negative phase output timer TAPAnTIVLY0 TAPATnCDENS0 ...

Page 1045: ...CTL1 register Set TAPAnATS 1 0 bits for TAPAnTADOUT0 Set TAPAnATS 3 2 for TAPAnTADOUT1 Start operation Start the TAUB module TAUB starts counting During operation TAUB runs in accord with the settings for the various functions The A D converter conversion trigger selector outputs TAPAnTADOUT0 in accord with the settings of TAPAnATS 1 0 or TAPAnTADOUT1 in accord with the settings of TAPAnATS 3 2 ba...

Page 1046: ...AN controller is identified by the index n n 0 1 for example FCN0GMCLCTL for the FCN0 control register Message buffers index m Throughout this section the FCN message buffer registers are identified by m m 000 to 031 for example FCNnMmDAT4B for FCN instance n message data byte 4 of message buffer register m Register address All CAN controller register addresses are given as address offsets to the ...

Page 1047: ...Function Connected to INT0ERR FCN0 error detection INTFCN0ERR INT0REC FCN0 reception completion INTFCN0REC INT0TRX FCN0 transmission completion INTFCN0TRX INT1ERR FCN1 error detection INTFCN1ERR INT1REC FCN1 reception completion INTFCN1REC INT1TRX FCN1 transmission completion INTFCN1TRX INT0WUP FCN0 sleep wake up transmission abortion INTFCN0WUP INT1WUP FCN1 sleep wake up transmission abortion INT...

Page 1048: ...y FCN module bit rate prescaler register FCNnCMBRPRS and bit rate register FCNnCMBTCTL As an example the following sample point configurations can be configured 66 7 70 0 75 0 80 0 81 3 85 0 87 5 Baud rates in the range of 10 kbps up to 1 Mbps can be configured Enhanced features Each message buffer can be configured to operate as a transmit or a receive message buffer A transmission request can be...

Page 1049: ...essage transmission Unique ID can be set to each message buffer Transmit completion interrupt can be enabled or disabled for each message buffer Transmission abort interrupt and transmission completion flag only one transmission of any buffer can be aborted at a time Message buffer number 0 to 7 specified as the transmit message buffer can be set for automatic block transfer Message transmission i...

Page 1050: ...r and to the CAN RAM within the FCN module CAN protocol layer This functional block is involved in the operation of the CAN protocol and its related settings CAN RAM This is the CAN memory functional block which is used to store message IDs message data etc Figure 20 1 Block Diagram of the CAN Controller CANTXDn CANRXDn FCN module CAN RAM PBUS MCM Message control module PBUS interface CPU Interrup...

Page 1051: ... mask 4 registers FCNnCMMKCTL07H FCNnCMMKCTL08H FCNnCMMKCTL07W FCNn module mask 5 registers FCNnCMMKCTL09H FCNnCMMKCTL10H FCNnCMMKCTL09W FCNn module mask 6 registers FCNnCMMKCTL11H FCNnCMMKCTL12H FCNnCMMKCTL11W FCNn module mask 7 registers FCNnCMMKCTL13H FCNnCMMKCTL14H FCNnCMMKCTL13W FCNn module mask 8 registers FCNnCMMKCTL15H FCNnCMMKCTL16H FCNnCMMKCTL15W FCNn module control register FCNnCMCLCTL ...

Page 1052: ...9 FCNn Global and Module Registers 1 2 Address Offset Register Name Symbol R W Access Bit After Reset 0 0008H FCNn global clock selection register FCNnGMCSPRE R W 8 0FH 0 0020H FCNn global automatic block transmission delay register FCNnGMADCTL R W 8 00H 0 8000H FCNn global control register FCNnGMCLCTL R W 16 00X0H 1 0 8018H FCNn global automatic block transmission register FCNnGMABCTL R W 16 0000...

Page 1053: ... 8 00H 0 024CH FCNn module information register FCNnCMINSTR R 8 00H 0 0268H FCNn module bit rate prescaler register FCNnCMBRPRS R W 8 FFH 0 0278H FCNn module last in pointer register FCNnCMLISTR R 8 Undefined 0 0288H FCNn module last out pointer register FCNnCMLOSTR R 8 Undefined 0 8240H FCNn module control register FCNnCMCLCTL R W 16 0000H 0 8250H FCNn module error counter register FCNnCMERCNT R ...

Page 1054: ...GMABCTL R 0 0 0 0 0 0 FCNnGM ABCLRF FCNnGMA BABTT 0 0 0 0 0 0 0 0 0 0020H FCNnGMADCTL 0 0 0 0 FCNnGMADSSAD 3 0 1 00C0H FCNnDNBMRX0 R FCNnDNBMSSDN 7 0 FCNnDNBMSSDN 15 8 FCNnDNBMSSDN 23 16 FCNnDNBMSSDN 31 24 Table 20 11 FCN Module Mask Control 16 Bit Registers Bit Configuration 1 2 Address Offset Symbol Bit 15 Bit 14 Bit 13 Bits 12 to 0 0 8300H FCNnCMM KCTL01H FCNnCMMKSSID 15 0 0 8308H FCNnCMM KCTL0...

Page 1055: ...ffset Symbol Bit 31 Bit 30 Bit 29 Bits 28 to 0 1 0300H FCNnCMM KCTL01W 0 0 0 FCNnCMMKSSID 28 0 1 0310H FCNnCMM KCTL03W 0 0 0 FCNnCMMKSSID 28 0 1 0320H FCNnCMM KCTL05W 0 0 0 FCNnCMMKSSID 28 0 1 0330H FCNnCMM KCTL07W 0 0 0 FCNnCMMKSSID 28 0 1 0340H FCNnCMM KCTL09W 0 0 0 FCNnCMMKSSID 28 0 1 0350H FCNnCMM KCTL11W 0 0 0 FCNnCMMKSSID 28 0 1 0360H FCNnCMM KCTL13W 0 0 0 FCNnCMMKSSID 28 0 1 0370H FCNnCMM K...

Page 1056: ...M INSTR 0 0 0 FCNnCMI NBOFF FCNnCMINSSTE 1 0 FCNnCMINSSRE 1 0 0 8250H FCNnCM ERCNT FCNnCMERTECF 7 0 FCNnCM ERRPSF FCNnCMERRECF 6 0 0 8258H FCNnCM IECTL W 0 FCNnCMIECLIE 6 0 0 FCNnCMIESEIE 6 0 FCNnCM IECTL R 0 FCNnCMIEINTF 6 0 0 0 0 0 0 0 0 0 0 8260H FCNnCM ISCTL W 0 FCNnCMISCLTS 6 0 0 0 0 0 0 0 0 0 FCNnCM ISCTL R 0 FCNnCMISITSF 6 0 0 0 0 0 0 0 0 0 0 0268H FCNnCM BRPRS FCNnCMBRPRS 7 0 0 8270H FCNnC...

Page 1057: ... 40H FCNnMm DAT0B FCNnMmSSD0 7 00 0 1004H m 40H FCNnMm DAT1B FCNnMmSSD1 7 00 0 9008H m 40H FCNnMm DAT2H FCNnMmSSD2 7 00 FCNnMmSSD3 7 00 0 1008H m 40H FCNnMm DAT2B FCNnMmSSD2 7 00 0 100CH m 40H FCNnMm DAT3B FCNnMmSSD3 7 00 1 1010H m 40H FCNnMm DAT4W FCNnMmSSD4 7 00 FCNnMmSSD5 7 00 FCNnMmSSD6 7 00 FCNnMmSSD7 7 00 0 9010H m 40H FCNnMm DAT4H FCNnMmSSD4 7 00 FCNnMmSSD5 7 00 0 1010H m 40H FCNnMm DAT4B F...

Page 1058: ...Mm SSIE 0 0 FCNnMmSSID 28 24 0 9038H m 40H FCNnMmCTL W 0 FCNnMm CLNH 0 FCNnMm CLMW FCNnMm CLIE FCNnMm CLDN FCNnMm CLTR FCNnMm CLRY 0 FCNnMm SENH 0 0 FCNnMm SEIE 0 FCNnMm CSETR FCNnMm SERY FCNnMmCTL R 0 FCNnMm NHMF 0 FCNnMm MOWF FCNnMm IENF FCNnMm DTNF FCNnMm TRQF FCNnMm RDYF 0 0 FCNnMm MUCF 0 0 0 FCNnMm TCPF 0 Table 20 14 FCN Message Buffer Register Bit Configuration 2 2 Address Offset Symbol Bit ...

Page 1059: ...ing any of the lower 8 bits the following mechanism is implemented When writing 16 bit data to the register address Bit clear Each of the lower 8 data bits CLx in the register layout below indicates whether the corresponding register bit RWx should be cleared i e set to 0 if CLx 1 the corresponding RWx is cleared to 0 remain unchanged if CLx 0 the corresponding RWx does not change Bit set Each of ...

Page 1060: ...d before bit manipulations Register write access Register read after bit manipulations Table 20 15 Bit Set Clear Operation CLx SEx Operation on RWx 0 0 No change of RWx 0 1 RWx set to 1 1 0 RWx cleared to 0 1 1 No change of RWx 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 1 1 May hold any value here 18H RW7 to RW0 83H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 0 0 0 0 0 0...

Page 1061: ...GMCLCTL FCNnGMCLSSMO is read only Even if 1 is written while it is 0 its value does not change and access to the message buffer registers or registers related to transmit history or receive history remains disabled 15 14 13 12 11 10 9 8 FCNnGM CLSSMO 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 FCNnGMC LECCF 1 FCNnGMC LSORF 1 0 0 FCNnGM CLESDE FCNnGM CLPWOM Note 1 Initial values are as follows No error detec...

Page 1062: ...M if FCNnGMCLCTL FCNnGMCLECCF is cleared before setting FCNnGMCLSORF Note 3 When FCNnGMCLCTL FCNnGMCLSORF is set to 1 again while it has been set to 1 the software reset procedure does not restart but continues Note 4 After release of the hardware reset FCNnGMCLCTL FCNnGMCLSORF is automatically set to 1 and initialization of message buffer RAM starts Note 5 It is impossible that clearing FCNnGMCLC...

Page 1063: ... to operate 15 14 13 12 11 10 9 8 0 0 0 FCNnGM CLSESR 0 0 FCNnGM CLSESD FCNnGM CLSEOM 7 6 5 4 3 2 1 0 0 0 FCNnGM CLCLMB 0 0 0 0 FCNnGM CLCLOM FCNnGMCLSESR Software Reset Start 0 No changes 1 Start software reset FCNnGMCLSESD FCNnGMCLSESD Setting 0 FCNnGMCLESDE bit remains unchanged 1 FCNnGMCLESDE bit set to 1 FCNnGMCLSEOM FCNnGMCLCLOM FCNnGMCLPWOM Setting 0 1 FCNnGMCLCTL FCNnGMCLPW OM bit cleared ...

Page 1064: ... bit units Address FCNn_base 0008H Initial value 0FH This register is initialized by various types of reset Note fCAN FCN reference clock 7 6 5 4 3 2 1 0 0 0 0 0 FCNnGMCSPRSC 3 0 FCNnGMCSPRSC 3 0 FCN Module System Clock fCANMOD 0000B fCAN 1 0001B fCAN 2 0010B fCAN 3 0011B fCAN 4 0100B fCAN 5 0101B fCAN 6 0110B fCAN 7 0111B fCAN 8 1000B fCAN 9 1001B fCAN 10 1010B fCAN 11 1011B fCAN 12 1100B fCAN 13...

Page 1065: ...Read Note Start clearing the automatic transmission engine by setting FCNnGMABCTL FCNnGMABSEAC to 1 while FCNnGMABCTL FCNnGMABABTT is 0 The operation is not guaranteed if FCNnGMABCLRF is set to 1 while FCNnGMABABTT 1 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 FCNnGM ABCLRF FCNnGM ABABTT FCNnGMABCLRF Automatic Block Transmission Engine Clear Status 0 Clearing the automatic tr...

Page 1066: ...ntroller has entered normal operating mode with ABT Caution 3 Do not start automatic block transmission while FCNnCMCLCTL FCNnCMCLSSTS is set to 1 transmission in progress Confirm FCNnCMCLSSTS 0 directly in advance before starting automatic block transmission 15 14 13 12 11 10 9 8 0 0 0 0 0 0 FCNnGM ABSEAC FCNnGM ABSEAT 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 FCNnGM ABCLAT FCNnGMABSEAC Automatic Block Trans...

Page 1067: ...1 Unit Data bit time DBT Caution1 Do not change the contents of the FCNnGMADCTL register while FCNnGMABCTL FCNnGMABCLRF 1 clearing of ABT in progress Caution 2 The timing at which the ABT message is actually transmitted onto the CAN bus differs depending on the status of transmission from the other station or how a request to transmit a message other than an ABT message is made 7 6 5 4 3 2 1 0 0 0...

Page 1068: ...d in 32 bit units Address FCNnDNBMRX0 FCNn_base 1 00C0H Initial value 0000 0000H This register can be initialized by various reset operations a FCNnDNBMRX0 31 30 29 28 27 26 25 24 FCNnDNBMSSDN 31 24 23 22 21 20 19 18 17 16 FCNnDNBMSSDN 23 16 15 14 13 12 11 10 9 8 FCNnDNBMSSDN 15 08 7 6 5 4 3 2 1 0 FCNnDNBMSSDN 07 00 FCNnDNBMSSDN 31 0 Message Buffer Data New 0 No remote or data frame has been store...

Page 1069: ...se 0 8308H FCNnCMMKCTL03H FCNn_base 0 8310H FCNnCMMKCTL04H FCNn_base 0 8318H FCNnCMMKCTL05H FCNn_base 0 8320H FCNnCMMKCTL06H FCNn_base 0 8328H FCNnCMMKCTL07H FCNn_base 0 8330H FCNnCMMKCTL08H FCNn_base 0 8338H FCNnCMMKCTL09H FCNn_base 0 8340H FCNnCMMKCTL10H FCNn_base 0 8348H FCNnCMMKCTL11H FCNn_base 0 8350H FCNnCMMKCTL12H FCNn_base 0 8358H FCNnCMMKCTL13H FCNn_base 0 8360H FCNnCMMKCTL14H FCNn_base 0...

Page 1070: ... used for both the standard and extended IDs 15 14 13 12 11 10 9 8 FCNnCMMKSSID 15 8 7 6 5 4 3 2 1 0 FCNnCMMKSSID 7 0 15 14 13 12 11 10 9 8 0 0 0 FCNnCMMKSSID 28 24 7 6 5 4 3 2 1 0 FCNnCMMKSSID 23 16 31 30 29 28 27 26 25 24 0 0 0 FCNnCMMKSSID 28 24 23 22 21 20 19 18 17 16 FCNnCMMKSSID 23 16 15 14 13 12 11 10 9 8 FCNnCMMKSSID 15 8 7 6 5 4 3 2 1 0 FCNnCMMKSSID 7 0 FCNnCMMKSSID i 1 Mask Pattern Setti...

Page 1071: ...he second bit of the inter frame space On transition to initialization mode at the first bit of the inter frame space Note 1 FCNnCMCLSSTS is set to 1 under the following condition timing The SOF bit of a transmit frame is detected Note 2 FCNnCMCLSSTS is cleared to 0 under the following conditions timing During transition to bus off state On occurrence of arbitration loss in transmit frame On detec...

Page 1072: ...s also cleared by normal shutdown or forced shutdown of the CAN controller Note FCNnCMCLALBF is valid only in single shot mode Note 1 Detection of a valid receive message frame is not dependent upon storage in the receive message buffer data frame or transmit message buffer remote frame Note 2 If only two CAN nodes are connected to the CAN bus with one transmitting a message frame in normal mode a...

Page 1073: ...ge from recessive level to dominant level Caution1 Transition to initialization mode or power save mode may take some time Be sure to verify the success of mode change by reading the values before proceeding Caution 2 If initialization mode is set during reception in operating mode the last reception in which the FCNnMmCTL FCNnMmDTNF bit in the message buffer is set may occur A transition back to ...

Page 1074: ... to 0 1 0 FCNnCMCLALBF is set to 1 Other than the above FCNnCMCLALBF is not changed FCNnCMCLCLVL Setting FCNnCMCLVALF 0 FCNnCMCLVALF is not changed 1 FCNnCMCLVALF is cleared to 0 FCNnCMCLSEPS0 FCNnCMCLCLPS0 Setting FCNnCMCLMDPF0 0 1 FCNnCMCLMDPF0 is cleared to 0 1 0 FCNnCMCLMDPF0 is set to 1 Other than the above FCNnCMCLMDPF0 is not changed FCNnCMCLSEPS1 FCNnCMCLCLPS1 Setting FCNnCMCLMDPF1 0 1 FCN...

Page 1075: ...LCLOP1 Setting FCNnCMCLMDOF1 0 1 FCNnCMCLMDOF1 is cleared to 0 1 0 FCNnCMCLMDOF1 is set to 1 Other than above FCNnCMCLMDOF1 is not changed FCNnCMCLSEOP2 FCNnCMCLCLOP2 Setting FCNnCMCLMDOF2 0 1 FCNnCMCLMDOF2 is cleared to 0 1 0 FCNnCMCLMDOF2 is set to 1 Other than above FCNnCMCLMDOF2 is not changed 7 6 5 4 3 2 1 0 0 0 0 0 0 FCNnCMLCSSLC 2 0 FCNnCMLCSSLC 2 0 Last FCN Protocol Error Information 000B ...

Page 1076: ...than 255 The value of the transmit counter is 256 or more FCNnCMINSSTE 1 0 Transmission Error Counter Status 00B The value of the transmission error counter is less than that of the warning level less than 96 01B The value of the transmission error counter is in the range of the warning level 96 to 127 10B Setting prohibited 11B The value of the transmission error counter is in the range of the er...

Page 1077: ...d in the bus off state FCNnCMINSTR FCNnCMINBOFF 1 15 14 13 12 11 10 9 8 FCNnCM ERRPSF FCNnCM ERRECF 6 0 7 6 5 4 3 2 1 0 FCNnCM ERTECF 7 0 FCNnCMERRPSF Reception Error Passive Status 0 The reception error counter is not in the error passive range less than 128 1 The reception error counter is in the error passive range 128 or more FCNnCMERRECF 6 0 Reception Error Counter 0 to 127 Number of receptio...

Page 1078: ...ad b FCNnCMIECTL Write 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 FCNnCMIEINTF 6 0 FCNnCMIEINTF 6 0 FCN Module Interrupt Enable 0 Output of the interrupt corresponding to interrupt status register FCNnCMISCTL is disabled 1 Output of the interrupt corresponding to interrupt status register FCNnCMISCTL is enabled 15 14 13 12 11 10 9 8 0 FCNnCMIESEIE 6 0 7 6 5 4 3 2 1 0 0 FCNnCMIECLIE 6 ...

Page 1079: ...mode has been released by software 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 FCNnCMISITSF 6 0 FCNnCMISITSF 6 0 FCN Interrupt Status 0 No related interrupt source event is pending 1 A related interrupt source event is pending Interrupt Status Bit Related Interrupt Source Event FCNnCMISITSF6 FCN module transmission abort interrupt status bit FCNnCMISITSF5 Wake up interrupt from FCN sle...

Page 1080: ... reference system clock fTQ The communication baud rate is set according to the FCNnCMBTCTL register Access This register can be read written in 8 bit units Address FCNn_base 0 0268H Initial value FFH This register is initialized by various types of reset 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 FCNnCMISCLTS 6 0 FCNnCMISCLTS 6 0 Clearing FCNnCMISITSF 6 0 0 FCNnCMISITSF 6 0 bits are ...

Page 1081: ...N module system clock fTQ CAN protocol layer reference system clock Caution FCNnCMBRPRS can be write accessed only in initialization mode FCNnGMCSPRSC 3 0 Prescaler FCNn module bit rate prescaler register FCNnCMBRPRS Baud rate generator FCNn module bit rate register FCNnCMBTCTL fCAN fCANMOD fTQ 0 0 0 0 FCNnCMBRPRS 7 0 FCNn global clock selection register FCNnGMCSPRE ...

Page 1082: ...is initialized by various types of reset Figure 20 3 Data Bit Time 15 14 13 12 11 10 9 8 0 0 FCNnCM BTJWLG 1 0 0 FCNnCM BTS2LG 2 0 7 6 5 4 3 2 1 0 0 0 0 0 FCNnCMBTS1LG 3 0 FCNnCMBTJWLG 1 0 Length of Synchronization Jump Width SJW 00B 1TQ 01B 2TQ 10B 3TQ 11B 4TQ default value FCNnCMBTS2LG 2 0 Length of Time Segment 2 TSEG2 000B 1TQ 001B 2TQ 010B 3TQ 011B 4TQ 100B 5TQ 101B 6TQ 110B 7TQ 111B 8TQ defa...

Page 1083: ... message buffer Therefore if FCNnCMRGRX FCNnCMRGSSPM is set to 1 after the FCN module has changed from initialization mode to an operating mode the read value of FCNnCMLISTR is undefined FCNnCMBTS1LG 3 0 Length of Time Segment 1 TSEG1 0000B Setting prohibited 0001B 2TQ 1 0010B 3TQ 1 0011B 4TQ 0100B 5TQ 0101B 6TQ 0110B 7TQ 0111B 8TQ 1000B 9TQ 1001B 10TQ 1010B 11TQ 1011B 12TQ 1100B 13TQ 1101B 14TQ 1...

Page 1084: ...GSSPT of the receive history list are read These contents indicate the number of the message buffer in which a data frame or a remote frame has been stored FCNnCMRGSSPM 1 Receive History List Pointer 0 The receive history list has at least one message buffer number that has not been read 1 The receive history list has no message buffer numbers that have not been read FCNnCMRGRVFF 1 Receive History...

Page 1085: ...mitted from the message buffer Therefor when FCNnCMTGTX FCNnCMTGSSPM is set at transition from initial mode to operation mode read value of FCNnCMLOSTR is undefined 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 FCNnCM RGCLRV FCNnCMRGCLRV Clearing FCNnCMRGRVFF 0 FCNnCMRGRVFF bit is not changed 1 FCNnCMRGRVFF bit is cleared to 0 7 6 5 4 3 2 1 0 FCNnCMLOSSLT 7 0 FCNnCMLOSSLT 7 0...

Page 1086: ...GTX is read the contents of the element indexed by the read pointer FCNnCMTGSSPT 7 0 of the transmit history list are read These contents indicate the number of the message buffer to which a data frame or a remote frame was transmitted last FCNnCMTGSSPM 1 Transmit History Pointer 0 The transmit history list has at least one message buffer number that has not been read 1 The transmit history list h...

Page 1087: ... 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 FCNnCM TGCLTV FCNnCMTGCLTV Setting FCNnCMTGTVFF 0 FCNnCMTGTVFF bit is not changed 1 FCNnCMTGTVFF bit is cleared to 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 FCNnCM TSLOKE FCNnCM TSSELE FCNnCM TSTSGE FCNnCMTSLOKE Time Stamp Lock Function Enable 0 Time stamp lock function stopped The TSOUT signal is toggled each time the selected...

Page 1088: ... 0 0 0 FCNnCM TSCLLK FCNnCM TSCLSL FCNnCM TSCLTS FCNnCMTSSELK FCNnCMTSCLLK Setting FCNnCMTSLOKE 0 1 FCNnCMTSLOKE is cleared to 0 1 0 FCNnCMTSLOKE is set to 1 Other than the above FCNnCMTSLOKE is not changed FCNnCMTSSESL FCNnCMTSCLSL Setting FCNnCMTSSELE 0 1 FCNnCMTSSELE is cleared to 0 1 0 FCNnCMTSSELE is set to 1 Other than the above FCNnCMTSSELE is not changed FCNnCMTSSETS FCNnCMTSCLTS Setting F...

Page 1089: ...se 0 1014H m 40H FCNnMmDAT6B FCNn_base 0 1018H m 40H FCNnMmDAT7B FCNn_base 0 101CH m 40H FCNnMmDAT0H FCNn_base 0 9000H m 40H FCNnMmDAT2H FCNn_base 0 9008H m 40H FCNnMmDAT4H FCNn_base 0 9010H m 40H FCNnMmDAT6H FCNn_base 0 9018H m 40H FCNnMmDAT0W FCNn_base 1 1000H m 40H FCNnMmDAT4W FCNn_base 1 1010H m 40H Initial value FCNnMmDATxB 00H FCNnMmDATyH 0000H FCNnMmDATzW 0000 0000H This register can be ini...

Page 1090: ...nMmSSD z 3 6 FCNnMmSSD z 3 7 23 22 21 20 19 18 17 16 FCNnMmSSD z 2 0 FCNnMmSSD z 2 1 FCNnMmSSD z 2 2 FCNnMmSSD z 2 3 FCNnMmSSD z 2 4 FCNnMmSSD z 2 5 FCNnMmSSD z 2 6 FCNnMmSSD z 2 7 15 14 13 12 11 10 9 8 FCNnMmSSD z 1 0 FCNnMmSSD z 1 1 FCNnMmSSD z 1 2 FCNnMmSSD z 1 3 FCNnMmSSD z 1 4 FCNnMmSSD z 1 5 FCNnMmSSD z 1 6 FCNnMmSSD z 1 7 7 6 5 4 3 2 1 0 FCNnMmSSDz0 FCNnMmSSDz1 FCNnMmSSDz2 FCNnMmSSDz3 FCNnM...

Page 1091: ...e FCNnMmDATxB register in which no data is stored is undefined Caution 3 On reception FCNnMmDTLGB is updated according to the received frame 7 6 5 4 3 2 1 0 0 0 0 0 FCNnMmDTLG 3 0 FCNnMmDTLG 3 0 Data Length of Transmit Receive Message 0000B 0 bytes 0001B 1 byte 0010B 2 bytes 0011B 3 bytes 0100B 4 bytes 0101B 5 bytes 0110B 6 bytes 0111B 7 bytes 1000B 8 bytes 1001B Setting prohibited If these bits a...

Page 1092: ...ame that is transmitted or received from to a message buffer Note 1 If the message buffer is defined as a transmit message buffer and a remote frame shall be received into it the FCNnMmSSRT bit must be cleared Note 2 Even if a valid remote frame has been received in a transmit message buffer the FCNnMmSSRT bit of the transmit message buffer that has received the frame remains cleared to 0 Note 3 E...

Page 1093: ...Nn_base 0 9030H m 40H FCNnMmMID0W FCNn_base 1 1028H m 40H Initial value FCNnMmMID0H 0000H FCNnMmMID1H 0000H FCNnMmMID0W 0000 0000H This register can be initialized by various reset operations a FCNnMmMID0H FCNnMmSSMT 3 0 Message Buffer Type Setting 0000B Transmit message buffer 0001B Receive message buffer no mask setting 0010B Receive message buffer mask 1 set 0011B Receive message buffer mask 2 ...

Page 1094: ...SSID 28 18 bit positions 15 14 13 12 11 10 9 8 FCNnMm SSIE 0 0 FCNnMmSSID 28 24 7 6 5 4 3 2 1 0 FCNnMmSSID 23 16 31 30 29 28 27 26 25 24 FCNnMm SSIE 0 0 FCNnMmSSID 28 24 23 22 21 20 19 18 17 16 FCNnMmSSID 23 16 15 14 13 12 11 10 9 8 FCNnMmSSID 15 8 7 6 5 4 3 2 1 0 FCNnMmSSID 7 0 FCNnMmSSIE Format Mode Specification 0 Standard format mode FCNnMmSSID 28 18 11 bits FCNnMmSSID 17 0 are not used 1 Exte...

Page 1095: ...is not set to 1 even if a remote frame is received and stored in the transmit message buffer of FCNnMmDTNF 1 15 14 13 12 11 10 9 8 0 0 FCNnMm MUCF 0 0 0 FCNnMm TCPF 0 7 6 5 4 3 2 1 0 0 FCNnMm NHMF 0 FCNnMm MOWF FCNnMm IENF FCNnMm DTNF FCNnMm TRQF FCNnMm RDYF FCNnMmMUCF Message Buffer Data Being Updated 0 The FCN module is not updating receiving and storing the message buffer 1 The FCN module is up...

Page 1096: ...ffer Valid message reception completion interrupt disabled Transmit message buffer Normal message transmission completion interrupt and abort interrupt disabled 1 Receive message buffer Valid message reception completion interrupt enabled Transmit message buffer Normal message transmission completion interrupt and abort interrupt enabled FCNnMmDTNF Message Buffer Data Update 0 No new data frame or...

Page 1097: ... message buffer participates in the search to store the receiving frame Caution Do not set FCNnMmDTNF to 1 by software Be sure to write 0 to bit 10 15 14 13 12 11 10 9 8 0 FCNnMm SENH 0 0 FCNnMm SEIE 0 FCNnMm SETR FCNnMm SERY 7 6 5 4 3 2 1 0 0 FCNnMm CLNH 0 FCNnMm CLMW FCNnMm CLIE FCNnMm CLDN FCNnMm CLTR FCNnMm CLRY FCNnMmSENH FCNnMmCLNH Setting FCNnMmNHMF 0 1 FCNnMmNHMF is cleared to 0 1 0 FCNnMm...

Page 1098: ...erform the transmission abort processing to clear FCNnMmRDYF Caution 4 Clearing of FCNnMmRDYF may take some time depending on activity of the CAN controller Repeat the clearing access until reading of FCNnMmRDYF confirms that the bit has been cleared Caution 5 Make sure that FCNnMmRDYF is cleared before writing to another message buffer register by checking the status of FCNnMmRDYF FCNnMmSETR FCNn...

Page 1099: ... Buffer in Initialization Mode Place the FCN module in initialization mode once and then change the ID and control information of the message buffer in initialization mode After the ID and control information are changed set the FCN module to an operating mode 2 Redefining Message Buffer during Reception Perform redefinition as shown in Figure 20 17 Message Buffer Redefinition during Reception 3 R...

Page 1100: ...d in the message buffer following redefinition are those stored after the message buffer has been redefined If no ID and IDE are stored after redefinition redefine the message buffer again Caution 2 When a message is transmitted the transmission priority is checked in accordance with the ID IDE and FCNnMmSTRB FCNnMmSSRT set to each transmit message buffer to which a transmission request was set Th...

Page 1101: ... reception or transmission is in progress and the FCN module enters initialization mode at the first bit in the inter frame space the values of FCNnCMCLCTL FCNnCMCLMDOF 2 0 are changed to 000B After issuing a request to change the mode to initialization mode read FCNnCMCLCTL FCNnCMCLMDOF 2 0 until their values become 000B to confirm that the module has entered initialization mode see Figure 20 14 ...

Page 1102: ... linked to mask 1 even if that message buffer has not received a message and a message has already been received in the unmasked receive message buffer In other words when a condition has been set in two or more message buffers with different priorities the message buffer with the highest priority always stores the message the message is not stored in message buffers with a lower priority This als...

Page 1103: ...the CPU Note that the storage process may be disturbed delayed when the CPU accesses the message buffer Caution To securely store a message in the message buffer the FCNnMmCTL FCNnMmDTNF bit of the buffer must be cleared before the message search processing is started before the frame ID is output to the bus This is the 15th of CAN bits after EOF of the previous frame at shortest To securely recei...

Page 1104: ...ory list is recorded The FCNnCMRGRX FCNnCMRGSSPT pointer is used as a read pointer that reads a recorded message buffer number from the RHL This pointer indicates the first RHL element that the CPU has not read yet By reading the FCNnCMRGRX register by software the number of a message buffer that has received and stored a data frame or remote frame can be read Each time a message buffer number is ...

Page 1105: ...fer 6 Event Message buffers 6 9 2 and 7 are read by CPU Newly received messages are stored in message buffers 3 4 and 8 Event Reception in message buffers 13 14 and 15 occurs Overflow situation occurs Event 20 other messages are received Message buffer 6 carries last received message Upon reception in message buffer 6 RHL is full RGRVFF is set Message buffer 8 Message buffer 4 Message buffer 3 Rec...

Page 1106: ...Identifier to be Stored in Message Buffer 2 Identifier to be Configured in Message Buffer 14 Example Using FCN1M014MID0W Register Note 1 ID with the ID27 to ID25 bits cleared to 0 and the ID24 and ID22 bits set to 1 is registered initialized in message buffer 14 Note 2 Message buffer 14 is set as a standard format identifier that is linked to mask 1 FCN1M014STRB FCN1M014SSMT 3 0 0010B 3 FCN Module...

Page 1107: ...message buffers 0 to k 2 is cleared to 0 interrupts disabled and FCNnMmIENF in message buffer k 1 is set to 1 interrupts enabled In that case a reception completion interrupt occurs when a message has been received and stored in message buffer k 1 indicating that MBRB has become full Alternatively by clearing FCNnMmIENF of message buffers 0 to k 3 and setting FCNnMmIENF of message buffer k 2 a war...

Page 1108: ...Ready for reception FCNnMmCTL FCNnMmRDYF 1 Set for remote frame message type FCNnMmSTRB FCNnMmSSRT 1 Buffer is ready to store a message FCNnMmCTL FCNnMmDTNF 0 or FCNnMmSTRB FCNnMmSSOW 1 and FCNnMmCTL FCNnMmDTNF 1 Upon reception of a remote frame the following actions are executed if the ID of the received remote frame matches the ID of a message buffer that satisfies the above conditions The FCNnM...

Page 1109: ...frame is stored in the transmit message buffer with the lowest message buffer number Note 2 If transmit and receive message buffers are found which can receive a remote frame matching with its ID either masked or unmasked the remote frame is stored in the transmit message buffer Note 3 If there are receive message buffers that meet remote frame receiving conditions the reception priority is identi...

Page 1110: ... priority is controlled by the identifier ID Figure 20 8 Example of Message Processing After the transmit message search the transmit message with the highest priority of the transmit message buffers that have a pending transmission request message buffers with the FCNnMmCTL FCNnMmTRQF bit set to 1 in advance is transmitted If a new transmission request is set the transmit message buffer with the ...

Page 1111: ...terrupt enable bit FCNnMmIENF of the corresponding transmit message buffer is set to 1 Note 2 When changing the contents of a transmit buffer the FCNnMmCTL FCNnMmRDYF flag of this buffer must be cleared before updating the buffer contents Since the FCNnMmRDYF flag may be locked temporarily during internal transfer operation the status of the FCNnMmRDYF flag must be checked by software after it is ...

Page 1112: ...read pointer that reads a recorded message buffer number from the THL This pointer indicates the first THL element that the CPU has not yet read By reading the FCNnCMTGTX register by software the number of a message buffer that has completed transmission can be read Each time a message buffer number is read from the FCNnCMTGTX register the FCNnCMTGSSPT 7 0 pointer is automatically incremented If t...

Page 1113: ... Message buffer 3 Message buffer 7 Transmit history list THL Transmit history list THL TGSSPT TGSSPT TGSSPT TGSSPT Transmit history list THL Transmit history list THL Message buffer 5 Message buffer 8 Message buffer 4 Message buffer 3 Message buffer 7 Message buffer 10 Message buffer 6 Message buffer 5 Message buffer 8 Message buffer 4 Message buffer 3 Message buffer 7 Message buffer 14 Message bu...

Page 1114: ...ally set to 1 After transmission of the data of message buffer 0 is completed the FCNnMmTRQF of the next message buffer message buffer 1 is automatically set In this way transmission is performed successively A delay time can be inserted by the program in the interval in which the transmission request FCNnMmCTL FCNnMmTRQF is automatically set while successive transmission is being executed The del...

Page 1115: ...from initialization mode to ABT mode Caution 4 Do not set FCNnMmCTL FCNnMmTRQF of the ABT message buffers to 1 by software in normal operating mode with ABT Otherwise the operation is not guaranteed Caution 5 The FCNnGMADCTL register is used to set the delay time that is inserted in the period from completion of the preceding ABT message to setting of FCNnMmCTL FCNnMmTRQF for the next ABT message ...

Page 1116: ...the transmission is completed successfully or not if an ABT message is currently being transmitted and is cleared to 0 as soon as transmission is completed This aborts ABT If the last transmission before ABT is aborted is successful the internal ABT pointer of the normal operating mode with ABT points to the next message buffer to be transmitted In the case of a failure in transmission the positio...

Page 1117: ...leted even if FCNnGMABCTL FCNnGMABABTT is cleared to 0 If FCNnMmCTL FCNnMmRDYF in the next message buffer in the ABT area is cleared to 0 the internal ABT pointer is retained but the resumption operation is not performed even if FCNnGMABABTT is set to 1 and ABT ends immediately 20 8 5 Remote Frame Transmission Remote frames can be transmitted only from transmit message buffers Set whether a data f...

Page 1118: ...erating modes 2 The CAN bus state is bus idle the fourth bit in the inter frame space is recessive If the CAN bus is fixed to dominant the request for transition to FCN sleep mode is held pending Also the transition from FCN stop mode to FCN sleep mode is independent of the CAN bus state 3 No transmission request is pending 4 Do not use power save mode in combination with the operating mode change...

Page 1119: ...ialization mode and sleep mode are not requested simultaneously i e the first request has not been granted while the second request is made the request for transition to initialization mode has priority over the sleep mode request The sleep mode request is cancelled when the transition to initialization mode is requested While a request for transition to initialization mode is pending a subsequent...

Page 1120: ...If FCN sleep mode is released by a change in the CAN bus state FCNnCMISCTL FCNnCMISITSF5 is set to 1 regardless of FCNnCMIECTL FCNnCMIEINTF 6 0 After the FCN module is released from FCN sleep mode it participates in the CAN bus communication again by automatically detecting 11 consecutive recessive level bits on the CAN bus The user application has to wait until FCNnGMCLCTL FCNnGMCLSSMO 1 before a...

Page 1121: ...tion pin FCNnRX while this process is being performed FCN sleep mode is automatically released In this case the FCN stop mode transition request is not acknowledged 2 FCN Stop Mode Status The FCN module is in the following state after it enters FCN stop mode The internal operating clock stops and the power consumption is minimized To wake up the FCN module from the CPU data can be set to FCNnCMCLC...

Page 1122: ... module is automatically released from FCN sleep mode FCNnCMCLMDPF 1 0 00B and returns to normal operating mode The CPU in response to INTnWUP can release its own power save mode and return to normal operating mode To further reduce the power consumption of the CPU the internal clock including that of the FCN module may be stopped In this case the operating clock supplied to the FCN module stops a...

Page 1123: ...ECTL 1 Interrupt Request Signal Description of Interrupt Source 1 FCNnCMISITSF0 FCNnCMIESEIE0 INTnTRX Message frame successfully transmitted from message buffer m 2 FCNnCMISITSF1 FCNnCMIESEIE1 INTnREC Valid message frame reception in message buffer m 3 FCNnCMISITSF2 FCNnCMIESEIE2 INTnERR FCN module error state interrupt This interrupt is generated when the transmission reception error counter is a...

Page 1124: ...er data frames or transmit message buffer remote frames A valid reception event is indicated and confirmed by setting FCNnCMCLCTL FCNnCMCLVALF to 1 Figure 20 10 FCN Module Pin Connection in Receive only Mode In receive only mode no message frames can be transmitted from the FCN module to the CAN bus Transmit requests issued to message buffers defined as transmit message buffers are held pending In...

Page 1125: ...t be used in combination with normal operating mode with ABT Single shot mode disables the re transmission of an aborted message frame according to the setting of FCNnCMCLCTL FCNnCMCLALBF When FCNnCMCLALBF is cleared to 0 re transmission upon arbitration loss and upon error occurrence is disabled If FCNnCMCLALBF is set to 1 re transmission upon error occurrence is disabled but re transmission upon...

Page 1126: ...d transmission and reception are internally looped back The FCN transmission pin FCNnTX is fixed to the recessive level If the falling edge on the FCN reception pin FCNnRX is detected after the FCN module has entered FCN sleep mode from self test mode however the module is released from the FCN sleep mode in the same manner as the other operating modes To keep the module in FCN sleep mode use the ...

Page 1127: ...ating Mode Operating Mode Transmission ofData Remote Frame Transmission of ACK Transmission of Error Overload Frame Transmission Retry Automatic Block Transmission ABT FCNnCMCLVALF Setting Store Data to Message Buffer Initialization mode Disabled Disabled Disabled Disabled Disabled Disabled Disabled Normal operating mode Enabled Enabled Enabled Enabled Disabled Enabled Enabled Normal operating mod...

Page 1128: ...24 4 9 CAN Time Stamp Function The 8ch and 9ch of TAUB0 capture timer values according to the capturing trigger signal TSOUT that is output when a data frame from the CAN controller is received The CPU can retrieve the time of occurrence of the capture event i e the time stamp of the message received from the CAN bus by reading the captured value The TSOUT signal can be selected from the following...

Page 1129: ... toggle occurrence by the TSOUT signal so that the time stamp value toggled last captured last can be saved as the time stamp value of the time at which the data frame was received in message buffer 0 Caution The time stamp function using the FCNnCMTSLOKE bit stops toggle of the TSOUT signal by receiving a data frame in message buffer 0 Toggle of the TSOUT signal does not stop when a data frame is...

Page 1130: ...TCTL FCNnCMBTS1LG 3 0 1 TSEG2 FCNnCMBTCTL FCNnCMBTS2LG 2 0 1 SJW FCNnCMBTCTL FCNnCMBTJWLG 1 0 1 Table 20 19 Settable Bit Rate Combinations shows combinations of bit rates that meet the above conditions Table 20 19 Settable Bit Rate Combinations 1 3 Valid Bit Rate Setting FCNnCMBTCTL Setting Value Sampling Point Unit DBT Length SYNC SEGMENT PROP SEGMENT PHASE SEGMENT 1 PHASE SEGMENT 2 FCNnCMBTS1LG ...

Page 1131: ...4 4 17 1 2 7 7 1000 110 58 8 17 1 4 6 6 1001 101 64 7 17 1 6 5 5 1010 100 70 6 17 1 8 4 4 1011 011 76 5 17 1 10 3 3 1100 010 82 4 17 1 12 2 2 1101 001 88 2 17 1 14 1 1 1110 000 94 1 16 1 1 7 7 0111 110 56 3 16 1 3 6 6 1000 101 62 5 16 1 5 5 5 1001 100 68 8 16 1 7 4 4 1010 011 75 0 16 1 9 3 3 1011 010 81 3 16 1 11 2 2 1100 001 87 5 16 1 13 1 1 1101 000 93 8 15 1 2 6 6 0111 101 60 0 15 1 4 5 5 1000 ...

Page 1132: ...10 000 92 3 12 1 1 5 5 0101 100 58 3 12 1 3 4 4 0110 011 66 7 12 1 5 3 3 0111 010 75 0 12 1 7 2 2 1000 001 83 3 12 1 9 1 1 1001 000 91 7 11 1 2 4 4 0101 011 63 6 11 1 4 3 3 0110 010 72 7 11 1 6 2 2 0111 001 81 8 11 1 8 1 1 1000 000 90 9 10 1 1 4 4 0100 011 60 0 10 1 3 3 3 0101 010 70 0 10 1 5 2 2 0110 001 80 0 10 1 7 1 1 0111 000 90 0 9 1 2 3 3 0100 010 66 7 9 1 4 2 2 0101 001 77 8 9 1 6 1 1 0110 ...

Page 1133: ...100 001 75 0 500 2 00000001 8 1 5 1 1 0101 000 87 5 250 2 00000001 16 1 1 7 7 0111 110 56 3 250 2 00000001 16 1 3 6 6 1000 101 62 5 250 2 00000001 16 1 5 5 5 1001 100 68 8 250 2 00000001 16 1 7 4 4 1010 011 75 0 250 2 00000001 16 1 9 3 3 1011 010 81 3 250 2 00000001 16 1 11 2 2 1100 001 87 5 250 2 00000001 16 1 13 1 1 1101 000 93 8 250 4 00000011 8 1 3 2 2 0100 001 75 0 250 4 00000011 8 1 5 1 1 01...

Page 1134: ... 1 0101 000 87 5 33 3 10 00001001 24 1 7 8 8 1110 111 66 7 33 3 10 00001001 24 1 9 7 7 1111 110 70 8 33 3 12 00001011 20 1 7 6 6 1100 101 70 0 33 3 12 00001011 20 1 9 5 5 1101 100 75 0 33 3 15 00001110 16 1 7 4 4 1010 011 75 0 33 3 15 00001110 16 1 9 3 3 1011 010 81 3 33 3 16 00001111 15 1 6 4 4 1001 011 73 3 33 3 16 00001111 15 1 8 3 3 1010 010 80 0 33 3 20 00010011 12 1 5 3 3 0111 010 75 0 33 3 ...

Page 1135: ...6 1 5 5 5 1001 100 68 8 500 2 00000001 16 1 7 4 4 1010 011 75 0 500 2 00000001 16 1 9 3 3 1011 010 81 3 500 2 00000001 16 1 11 2 2 1100 001 87 5 500 2 00000001 16 1 13 1 1 1101 000 93 8 500 4 00000011 8 1 3 2 2 0100 001 75 0 500 4 00000011 8 1 5 1 1 0101 000 87 5 250 4 00000011 16 1 3 6 6 1000 101 62 5 250 4 00000011 16 1 5 5 5 1001 100 68 8 250 4 00000011 16 1 7 4 4 1010 011 75 0 250 4 00000011 1...

Page 1136: ... 00011101 24 1 9 7 7 1111 110 70 8 33 3 24 00010111 20 1 9 5 5 1101 100 75 0 33 3 24 00010111 20 1 11 4 4 1110 011 80 0 33 3 30 00011101 16 1 7 4 4 1010 011 75 0 33 3 30 00011101 16 1 9 3 3 1011 010 81 3 33 3 32 00011111 15 1 8 3 3 1010 010 80 0 33 3 32 00011111 15 1 10 2 2 1011 001 86 7 33 3 37 00100100 13 1 6 3 3 1000 010 76 9 33 3 37 00100100 13 1 8 2 2 1001 001 84 6 33 3 40 00100111 12 1 5 3 3...

Page 1137: ...TART After hardware RESET Set FCNnCGMCSPRE register Set FCNnGMCLCTL FCNnGMCLPWOM Set FCNnCMIECTL register Set FCNnCMMKCTLx register END Initialize message buffers Set FCNnCMBRPRS register and FCNnCMBTCTL register Set FCNnCMCLCTL FCNnCMCLMDOF 2 0 No No The period of software reset FCNnGMCLCTL FCNnGMCLSESR 1 is about 550 CLK Yes Yes FCNnGMCLCTL FCNnGMCLECCF 0 FCNnGMCLCTL FCNnGMCLSORF 0 Execute softw...

Page 1138: ...ode after all transmit requests have been cleared according to the transmission abort processing in Figure 20 24 in operating mode In normal operating mode with ABT clear all transmit requests according to the transmission abort processing in Figure 20 25 No Yes START END Initialization mode Initialize message buffers Clear FCNnCMCLCTL FCNnCMCLMDOF 2 0 Set FCNnCMBRPRS register and FCNnCMBTCTL regi...

Page 1139: ...Execute software reset FCNnGMCLCTL FCNnGMCLSESR 1 FCNnGMCLCTL FCNnGMCLECCF 0 FCNnGMCLCTL FCNnGMCLSORF 0 FCNnGMCLCTL FCNnGMCLPWOM 0 Initialize message buffers Set FCNnGMCSPRE register Set FCNnGMCLCTL FCNnGMCLPWOM Set FCNnCMIECTL register Set FCNnCMMKCTLx register Set FCNnCMBRPRS register and FCNnCMBTCTL register Set FCNnCMCLCTL FCNnCMCLMDOF 2 0 Operating mode Normal operating mode normal operating ...

Page 1140: ...ake the following settings for message buffers not used by the application Clear the FCNnMmRDYF FCNnMmTRQF and FCNnMmDTNF bits of the FCNnMmCTL register to 0 Clear FCNnMmSTRB FCNnMmSSAM to 0 END No Yes No No Yes Yes START Set FCNnMmSTRB register Transmit message buffer Set FCNnMmMID0W register Set FCNnMmDTLGB register Set FCNnMmCTL register Set FCNnMmRDYF register Clear FCNnMmCTL FCNnMmRDYF FCNnMm...

Page 1141: ... Set message buffers END No Yes No Yes Yes No Note 1 Confirm that a message is being received because FCNnMmCTL FCNnMmRDFY must be set after a message is completely received Note 2 Avoid message buffer redefinition during store operation of message reception by waiting additional 4 CAN data bits Clear FCNnMmCTL FCNnMmRDYF Clear FCNnCMCLCTL FCNnCMCLVALF FCNnCMCLCTL FCNnCMCLSSRS 0 or FCNnCMCLCTL FCN...

Page 1142: ... 0 0000B Figure 20 18 Message Buffer Redefinition during Transmission Remote frame Yes No START No Yes Data frame or remote frame Set FCNnMmDATx register Set FCNnMmDTLGB register Clear FCNnMmSTRB FCNnMmSSRT Set FCNnMmMID0W register Set FCNnMmDTLGB register Set FCNnMmSTRB FCNnMmSSRT Set FCNnMmMID0W register Data frame Transmit Set FCNnMmCTL FCNnMmRDYF Set FCNnMmCTL FCNnMmTRQF Transmit abort process...

Page 1143: ...nMmRDYF must be set before setting FCNnMmCTL FCNnMmTRQF Caution 2 Do not set FCNnMmCTL FCNnMmRDYF and FCNnMmCTL FCNnMmTRQF at the same time No Yes Yes No Remote frame Data frame START END Data frame or remote frame Set FCNnMmDATx register Set FCNnMmDTLGB register Clear FCNnMmSTRB FCNnMmSSRT Set FCNnMmMID0W register Set FCNnMmDTLGB register Set FCNnMmSTRB FCNnMmSSRT Set FCNnMmMID0W register Set FCN...

Page 1144: ...s other than ABT message buffers see Figure 20 19 Message Transmit Processing Caution FCNnCMCLCTL FCNnCMCLSSTS must be cleared to 0 before setting FCNnGMABCTL FCNnGMABABTT to 1 FCNnCMCLCTL FCNnCMCLSSTS must be checked first and then FCNnGMABCTL FCNnGMABABTT must be set to 1 Yes START END No Yes Yes No Set all ABT transmit messages Yes No No Set FCNnMmDATx register Set FCNnMmDTLGB register Clear FC...

Page 1145: ...ne in order to check the access to the message buffers as well as transmit history list registers of the FCN module in case a pending sleep mode had been executed If FCNnGMCLSSMO is detected to be cleared at No Remote frame Date frame Transmit completion interrupt processing START END Data frame or remote frame Yes Read FCNnCMLOSTR register Set FCNnMmDATx register Set FCNnMmDTLGB register Clear FC...

Page 1146: ...nterrupt Using FCNnCMTGTX Register Yes Remote frame Data frame No Yes No Yes START END Data frame or remote frame No Transmit completion interrupt processing Set FCNnMmDATx register Set FCNnMmDTLGB register Clear FCNnMmSTRB FCNnMmSSRT Set FCNnMmMID0W register Set FCNnMmDTLGB register Set FCNnMmSTRB FCNnMmSSRT Set FCNnMmMID0W register Set FCNnMmCTL FCNnMmRDYF Set FCNnMmCTL FCNnMmTRQF Read FCNnCMTGT...

Page 1147: ...eck the access to the message buffers as well as transmit history list registers of the FCN module in case a pending sleep mode had been executed If FCNnGMCLSSMO is detected to be cleared at any check re set FCNnGMCLSSMO discard actions and results of the processing and then perform processing again It is recommended that all sleep mode requests be cancelled before processing transmission interrup...

Page 1148: ...e frame Data frame No No Yes No Yes START END Data frame or remote frame Yes FCNnCMISCTL FCNnCMISITSF0 1 Set FCNnMmDATx register Set FCNnMmDTLGB register Clear FCNnMmSTRB FCNnMmSSRT Set FCNnMmMID0W register Set FCNnMmDTLGB register Set FCNnMmSTRB FCNnMmSSRT Set FCNnMmMID0W register Set FCNnMmCTL FCNnMmRDYF Set FCNnMmCTL FCNnMmTRQF FCNnMmCTL FCNnMmRDYF 0 FCNnCMTGTX FCNnCMTGTVFF 1 FCNnCMTGTX FCNnCMT...

Page 1149: ...transmission interrupts Note 2 Once FCNnCMTGTX FCNnCMTGTVFF is set the transmit history list is inconsistent Consider to examine all configured transmit buffers to check completed transmissions Figure 20 24 Transmission Abort Processing Except Normal Operating Mode with ABT Note A transmission request to the protocol layer may have been acknowledged during a period of 11 bits 3 bit next inter fram...

Page 1150: ...an be checked after the transmit completion interrupt Caution 4 Do not execute any new transmission request including transmission in other message buffers while transmission abort processing is in progress Figure 20 25 Transmission Abort Processing other than the ABT transmission Normal Operating Mode with ABT No Yes No Yes START END Wait for 11 CAN data bits Read FCNnCMLOSTR register Clear FCNnM...

Page 1151: ...e transmission abort processing is in progress Note Since the transmission request to the protocol layer has already been acknowledged transmission may be started during a period of 11 bits 3 bit next inter frame space plus 8 bit transmission abort processing even if theFCNnMmCTL FCNnMmTRQF bit is cleared Figure 20 26 ABT Transmission Request Abort Processing Normal Operating Mode with ABT 1 shows...

Page 1152: ...FCNnGMABABTT is cleared after ABT mode is aborted following the procedure shown in Figure 20 26 ABT Transmission Request Abort Processing Normal Operating Mode with ABT 1 or Figure 20 27 ABT Transmission Request Abort Processing Normal Operating Mode with ABT 2 with Transmission Abort Interrupt Flag When clearing a transmission request in an area other than the ABT area follow the procedure shown ...

Page 1153: ...p mode FCN stop mode transition request after FCNnGMABCTL FCNnGMABABTT is cleared after ABT mode is aborted following the procedure shown in Figure 20 26 ABT Transmission Request Abort Processing Normal Operating Mode with ABT 1 or Figure 20 27 ABT Transmission Request Abort Processing Normal Operating Mode with ABT 2 When clearing a transmission request in an area other than the ABT area follow t...

Page 1154: ... step Transmission abort success indicates that the transmission was successfully aborted which was checked by using the FCNnMmTCPF flag in the ABT message buffer Figure 20 28 ABT Transmission Request Abort Processing with Transmission Completion Flag Normal Operating Mode with ABT No No Yes Yes START END FCNnGMABCTL FCNnGMABABTT 0 Clear FCNnGMABCTL FCNnGMABABATT Transmission start pointer clear T...

Page 1155: ...ure shown in Figure 20 26 ABT Transmission Request Abort Processing Normal Operating Mode with ABT 1 or Figure 20 27 ABT Transmission Request Abort Processing Normal Operating Mode with ABT 2 When clearing a transmission request in an area other than the ABT area follow the procedure shown in Figure 20 24 Transmission Abort Processing Except Normal Operating Mode with ABT Note There is the case th...

Page 1156: ...ft using this flowchart Caution 3 Avoid the target message from being updated setting FCNnMmRDYF and FCNnMmTRQF while transmission abort processing is in progress due to the transmission completion processing Caution 4 Do not clear FCNnMmTRQF of other message buffers while transmission abort processing is in progress Caution 5 When setting an ID with lower priority than the previous ID after trans...

Page 1157: ... Before making a sleep mode transition request confirm that there is no transmission request left using this flowchart Caution 3 Avoid the target message from being updated setting FCNnMmRDYF and FCNnMmTRQF while transmission abort processing is in progress due to the transmission completion processing Caution 4 When setting an ID with lower priority than the previous ID after transmission abort p...

Page 1158: ... the message buffers as well as receive history list registers of the FCN module in case a pending sleep mode had been executed If FCNnGMCLSSMO is detected to be cleared at any check re set FCNnGMCLSSMO discard actions and results of the processing and then perform processing again It is recommended that all sleep mode requests be cancelled before processing reception interrupts Yes No START END R...

Page 1159: ...Yes Yes No No or 2 START Clear FCNnCMRGRX FCNnCMRGRVFF FCNnCMRGRX FCNnCMRGRVFF 1 Read FCNnCMRGRX register Generation of receive completion interrupt END Yes Correct data is read Illegal data is read B A A B FCNnCMRGRX FCNnCMRGSSPM 1 Read FCNnMmDATx FCNnMmDTLGB and FCNnMmMID0W registers Clear FCNnMmCTL FCNnMmDTNF FCNnMmCTL FCNnMmDTNF 0 and FCNnMmCTL FCNnMmMUCF 0 1 ...

Page 1160: ...CNnGMCLSSMO flag at the beginning and at the end of the interrupt routine in order to check the access to the message buffers as well as receive history list registers of the FCN module in case a pending sleep mode had been executed If FCNnGMCLSSMO is detected to be cleared at any check re set FCNnGMCLSSMO discard actions and results of the processing and then perform processing again It is recomm...

Page 1161: ... It is recommended that all sleep mode requests be cancelled before processing reception interrupts Note 2 Once FCNnCMRGRX FCNnCMRGRVFF is set the receive history list is inconsistent Consider to examine all configured receive buffers to check reception Note 3 This flow will not provide most recently received data for the application However interrupt load is reduced because of less processing amo...

Page 1162: ... FCNnGMCLSSMO is detected to be cleared at any check re set FCNnGMCLSSMO discard actions and results of the processing and then perform processing again Note 3 Once FCNnCMRGRX FCNnCMRGRVFF is set the receive history list is inconsistent Consider to examine all configured receive buffers to check reception No No Yes Yes Yes No START Yes Read FCNnCMRGRX register END Correct data is read Illegal data...

Page 1163: ...p mode perform transmission abort processing according to previously given flowcharts Set FCNnCMCLCTL FCNnCMCLMDPF0 CAN sleep mode END Yes No CAN stop mode Request CAN sleep mode again Clear FCNnCMISCTL FCNnCMISITSF5 Yes No Yes No Initialization mode Yes No Clear FCNnCMCLCTL FCNnCMCLMDOF 2 0 Set FCNnCMCLCTL FCNnCMCLMDOF 2 0 Set FCNnCMCLCTL FCNnCMCLMDPF1 FCNnCMCLCTL FCNnCMCLMDPF1 1 FCNnCMCLCTL FCNn...

Page 1164: ...asing FCN Sleep Mode and Stop Mode START END CAN sleep mode CAN stop mode Releasing CAN sleep mode by user Releasing CAN sleep mode by CAN bus active Bus activity 0 FCNnCMCLCTL FCNnCMCLMDPF0 0 FCNnCMISCTL FCNnCMISITSF5 1 Clear FCNnCMCLCTL FCNnCMCLMDPF0 Clear FCNnCMCLCTL FCNnCMCLMDPF1 Clear FCNnCMISCTL FCNnCMISITSF5 ...

Page 1165: ... the reception error counter is cleared Therefore it is necessary to detect 11 consecutive recessive level bits 128 times again on the bus Note Operating mode Normal operating mode normal operating mode with ABT receive only mode single shot mode self test mode START Forced recovery from bus off END Yes No Wait for recovery from bus off Yes No Set FCNnCMCLCTL FCNnCMCLMDOF 2 0 Set FCNnCMCLCTL FCNnC...

Page 1166: ...time period from the setting of the FCNnGMCLESDE bit until clearing of the FCNnGMCLPWOM bit Clear FCNnGMCLCTL FCNnGMCLPWOM FCNnGMCLCTL FCNnGMCLPWOM 0 Yes No Initialization mode END Shutdown successful FCNnGMCLCTL FCNnGMCLPWOM 0 FCNnGMCLCTL FCNnGMCLESDE 0 START START Yes No Must be a subsequent write END FCNnGMCLCTL FCNnGMCLPWOM 0 Shutdown successful FCNnGMCLCTL FCNnGMCLPWOM 0 FCNnGMCLCTL FCNnGMCLE...

Page 1167: ...ing START FCNnCMISCTL FCNnISITSF2 1 END Yes No Yes No Error interrupt Clear FCNnCMISCTL FCNnISITSF3 Clear FCNnCMISCTL FCNnISITSF2 No Yes Check CAN module state read FCNnCMINSTR register Check CAN protocol error state read FCNnCMLCSTR register FCNnCMISCTL FCNnISITSF3 1 FCNnCMISCTL FCNnISITSF4 1 Clear FCNnCMISCTL FCNnISITSF4 ...

Page 1168: ... by wake up from the CAN bus until the CPU is set to CPU standby mode Note 2 A wake up condition may occur on the CAN bus during a time period from checking of FCNnGMCLSSMO 0 until CPU standby mode is set In that case the CAN module releases sleep mode the FCNnCMISITSF5 bit is set and a wake up interrupt is generated if it is enabled START FCNnCMCLCTL FCNnCMCLMDPF0 1 FCNnGMCLCTL FCNnGMCLSSMO 0 END...

Page 1169: ...be released only by setting FCNnCMCLCTL FCNnCMCLMDPF 1 0 to 01B and is not released by a change in the FCN bus state START END Yes Yes Set CPU standby mode No Yes CAN sleep mode Clear FCNnCMISCTL FCNnCMISITSF5 No No CAN stop mode FCNnCMCLCTL FCNnCMCLMDPF0 1 Set FCNnCMCLCTL FCNnCMCLMDPF0 FCNnCMCLCTL FCNnCMCLMDPF1 1 FCNnCMCLCTL FCNnCMCLMDPF 1 0 11B Set FCNnCMCLCTL FCNnCMCLMDPF1 ...

Page 1170: ...ter 0 Register addresses All CSIGn register addresses are given as address offsets to the individual base addresses CSIGn_base0 and CSIGn_base1 The base address CSIGn_base of each CSIGn is listed in the following table Clock supply The following clock is input on CSIGn Interrupt The clocked serial interface G can generate the following interrupt requests Table 21 1 Instances of CSIG Clocked Serial...

Page 1171: ...rrupt Interrupt controller INTCSIGnIR DMA CSIGnTIRE Reception error interrupt Interrupt controller INTCSIGnIRE Table 21 5 CSIGn I O Signals CSIGn Signals Function Connected to CSIGnTSCK Serial clock signal Port CSIGnSC CSIGnTSI Serial data input signal Port CSIGnSI CSIGnTSO Serial data output signal Port CSIGnSO CSIGnTRYI Handshake input signal Port CSIGnRYI CSIGnTRYO Handshake output signal Port ...

Page 1172: ...electable Data transfer with MSB or LSB first selectable Transfer data length selectable from 7 to 16 bits in 1 bit units EDL extended data length function for transferring data with more than16 bits Three selectable transfer modes Transmit only mode Receive only mode Transmit receive mode Built in handshake function Separate transmit and receive buffers two 16 bit registers Error detection data c...

Page 1173: ...the internal baud rate generator BRG In slave mode the module supplies the serial communications clock through CSIGnTSCK Peripheral bus CSIGnRX0 Main control unit CSIGnTIC CSIGnTX0 16 16 32 BRG PCLK CSIGnCFG0 Interrupt generator Shift register Loop back circuit CSIGnCTL0 1 CSIGnCTL2 Peripheral bus CSIGnTIR CSIGnTIRE CSIGnTSCK CSIGnTSO CSIGnTSI CSIGnTRYI CSIGnTRYO Master mode transmission clock Buf...

Page 1174: ...lue other than 111B in CSIGnCTL2 CSIGnPRS 2 0 and a value other than 0 in CSIGnCTL2 CSIGnBRG 11 0 makes the settings for the BRG effective The default level of CSIGnTSCK depends on the clock phase selection bit it is high when CSIGnCTL1 CSIGnCKR 0 and is low when CSIGnCTL1 CSIGnCKR 1 The example below shows the communication in master mode for 8 data bits CSIGnCTL1 CSIGnCKR 0 CSIGnCFG0 CSIGnDAP 0 ...

Page 1175: ...nCTL2 CSIGnPRS 2 0 to 111B Note When using slave mode disable the baud rate generator BRG by clearing bits CSIGnCTL2 CSIGnBRS 11 0 The example below shows the communication in slave mode for 8 data bits CSIGnCTL1 CSIGnCKR 0 CSIGnCFG0 CSIGnDAP 0 and MSB first Figure 21 3 Transmit Receive in Slave Mode 21 3 2 Master Slave Connections Figure 21 4 Simple Master Slave Connection DO7 DO6 DO5 DO4 DO3 DO2...

Page 1176: ...aud rate is calculated as follows CSIGnTSCK PCLK 2m k 2 Where m CSIGnCTL2 CSIGnPRS 2 0 0 to 6 k CSIGnCTL2 CSIGnBRS 11 0 1 to 4095 Baud rate upper lower limits When setting the baud rate note the following points The baud rate must be no greater than 8 0 Mbps in master mode The baud rate must be no greater than 6 6 Mbps in slave mode and no greater than PCLK 6 Mbps For operation with an external ma...

Page 1177: ...ansfer to start As long as CSIGnBCTL0 CSIGnSCE 1 reading from the receive data register CSIGnRX0 triggers further reception In slave mode reception starts when the communication clock CSIGTSCK from the master is received Note In receive only mode avoid overwriting of data by reading previously received data from the reception register CSIGnRX0 before new data arrive Moreover the communication star...

Page 1178: ...ws The data has to be broken into 16 bit blocks plus remainder For example a string of 42 bits would be broken into two 16 bit blocks plus 10 bits The remainder defines the data length that has to be specified in the CSIGnCFG0 CSIGnDLS 3 0 bits If a 16 bit block is to be transmitted CSIGnTX0W CSIGnEDL must be set to 1 In this case data written to CSIGnTX0W are transmitted as 16 bit data regardless...

Page 1179: ... is enabled the parity bit is added after the last bit Note 3 When sending data in LSB first mode MSB first mode write to the CSIGnTX0W register according to the relevant sequence below when transmission data is 123456H CSIGnCFG0 CSIGnDIR 1 LSB first CSIGnTX0W 2000 3456H CSIGnEDL 1 CSIGnTX0W 0000 0012H CSIGnEDL 0 CSIGnCFG0 CSIGnDIR 0 MSB first CSIGnTX0W 2000 1234H CSIGnEDL 1 CSIGnTX0W 0000 0056H C...

Page 1180: ... DO3 DO2 DO1 DI5 DI4 DI3 DI2 DI1 DO0 DI7 DI6 DI0 Read operation from CSIGnRX0 Underfined Data Underfined Data Underfined Data Shift register Data 00H Data Data CSIGnRX0 Shift register 15 8 7 0 15 8 7 0 15 8 7 0 15 8 7 0 CSIGnTSCK CSIGnTSI CSIGnTSO Write value CSIGnTX0W CSIGnTSO Write operation from CSIGnTX0W to shift register CSIGnTSI CSIGnTSO Read value CSIGnTSI DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 CS...

Page 1181: ...s set to transmit receive mode CSIGnCTL0 CSIGnPWR 1 CSIGnCTL0 CSIGnTXE 1 and CSIGnCTL0 CSIGnRXE 1 communication start is enabled 4 The transfer status flag CSIGnSTR0 CSIGnTSF is automatically set when data for transfer are written to the transmission register CSIGnTX0W or CSIGnTX0H 5 When an external clock signal is detected as the CSIGnTSCK signal the slave immediately starts transferring data th...

Page 1182: ...AP 0 normal clock and data phase CSIGnCFG0 CSIGnDLS 3 0 1000B 8 bit data length and CSIGnCTL1 CSIGnSLIT 0 normal interrupt timing Figure 21 11 Generation of CSIGnTIC after Communication CSIGnCTL1 CSIGnSLIT 0 However CSIGnTIC can also be set up to occur when the CSIGnTX0 or CSIGnTX0H register is free for the next data This is specified by setting CSIGnCTL1 CSIGnSLIT 1 This mode allows more efficien...

Page 1183: ... register CSIGnSTR0 For details on the various error types refer to Section 21 3 11 Error Detection 4 All Interrupts Delay In master mode delaying all interrupts from the master by half a cycle of the transmission clock CSIGnTSCK is possible This function is not available in slave mode Set the CSIGnCTL1 CSIGnSIT bit to 1 to specify this delay The following settings are assumed in the figure below ...

Page 1184: ...ul 17 2014 V850E2 PG4 L Section 21 Clocked Serial Interface G CSIG Figure 21 14 Interrupt Delay Function CSIGnCTL1 CSIGnSIT 1 DO0 DI7 DO7 DI6 DO6 DO5 DO4 DO3 DO2 DO1 DI5 DI4 DI3 DI2 DI1 DI0 CSIGnTSCK CSIGnTSI CSIGnTSO CSIGnTIC Delay DO7 DI7 Delay ...

Page 1185: ...ft register to CSIGnRX0 CSIGnRX0 full condition The following examples assume 8 bit data length Figure 21 15 Ready Busy Signal from Slave CSIGnCFG0 CSIGnDAP 0 As long as the slave is busy the master has to wait i e suspend the transmission clock The slave sets CSIGnTRYO to high ready as soon as the reception register CSIGnRX0 has been read Figure 21 16 Ready Busy Signal from Slave CSIGnCFG0 CSIGnD...

Page 1186: ...ss causes the master to suspend generation of the serial clock after the current transfer is complete The master resumes the transfer as soon as the level on the CSIGnTRYI is high indicating that the slave is ready Figure 21 18 Master s Response to CSIGnTRYO Signal from Slave CSIGnCFG0 CSIGnDAP 1 Caution CSIGnTRYI must be pulled down by the slave before the next transfer starts Even if the signal ...

Page 1187: ...SCK CSIGnTSO and CSIGnTSI signals are disconnected from the port pins In addition the CSIGnTSO output is fixed to the low level and CSIGnTSCK is set to the inactive state The rest of CSIG works as in normal operation In order to test the CSIG set the CSIGnCTL1 CSIGnLBM bit to 1 carry out normal transfer operations and then check that the received data is the same as the transmitted data Figure 21 ...

Page 1188: ...Detection CSIG can detect three error types Data consistency error transmission data Parity error received data Overrun error Error checking can be individually enabled disabled for each type If one of these errors is detected the CSIGnTIRE interrupt signal is generated and the flag corresponding to the detected error is set ...

Page 1189: ...al levels on CSIGnTSO are written into their own shift register After completion of the transmission the transmitted data is compared with the original transmission data A mismatch is considered a data consistency error in which case the following steps proceed The CSIGnTIRE interrupt signal is generated The data consistency error flag CSIGnSTR0 CSIGnDCE is set Caution For data consistency checkin...

Page 1190: ...pt CSIGnTIRE is generated The parity error flag CSIGnSTR0 CSIGnPE is set The following figure shows an example Data length is 8 bits The data transmitted is 05H and 35H Parity type is odd Figure 21 22 Parity Check Example The parity bit for the first of the data to be received is 1 There is no parity error because the total number of ones including the parity bit is odd The parity bit for the subs...

Page 1191: ...ample where Rx data 3 was not read Rx data 4 was received but cannot be stored Thus an overrun error occurs Figure 21 24 Overrun Error Detection Example Note Overrun errors from trying to overwrite received data in slave mode can be avoided through handshaking When handshake is used in slave mode the receiver slave signals to the transmitter master that it is busy The transmitter then waits until ...

Page 1192: ...ster Overview Register name Symbol Address Control register 0 CSIGnCTL0 CSIGn_base1 00H Control register 1 CSIGnCTL1 CSIGn_base0 10H Control register 2 CSIGnCTL2 CSIGn_base0 14H Status register 0 CSIGnSTR0 CSIGn_base1 04H Status clear register 0 CSIGnSTCR0 CSIGn_base1 08H Receive only mode control register 0 CSIGnBCTL0 CSIGn_base1 80H Configuration register 0 CSIGnCFG0 CSIGn_base0 1010H Transmissi...

Page 1193: ...a transmission is pending or ongoing i e if CSIGnSTR0 CSIGnTSF 1 7 6 5 4 3 2 1 0 CSIGn PWR CSIGn TXE CSIGn RXE 0 0 0 0 CSIGn MBS R W R W R W R R R R R W Table 21 9 CSIGnCTL0 Register Contents Bit Position Bit Name Function 7 CSIGnPWR Controls operation clock 0 Stop operation clock 1 Provide operation clock Clearing CSIGnPWR to 0 resets the internal circuits stops operation and sets the CSIG to sta...

Page 1194: ... SIT CSIGn HSE 0 R R R R R R R R R W R R W R R W R W R W R Table 21 10 CSIGnCTL1 Register Contents 1 2 Bit Position Bit Name Function 17 CSIGnCKR Selects the phase of the CSIGnTSCK clock signal 0 Default level of CSIGnTSCK is high 1 Default level of CSIGnTSCK is low For the setting example refer to the CSIGnDAP bit in Table 21 15 CSIGnCFG0 Register Contents 16 CSIGnSLIT Selects the timing of inter...

Page 1195: ...he bit to 0 in slave mode 2 CSIGnSIT Selects interrupt delay mode 0 No delay 1 Half clock delay for all interrupts This bit is only valid in master mode In slave mode no delay is generated For details refer to Section 21 3 8 CSIG Interrupts 1 CSIGnHSE Enables disables handshake mode 0 Handshake function disabled 1 Handshake function enabled For details refer to Section 21 3 9 Handshake Function Ta...

Page 1196: ...1 0 R W R W R W R R W R W R W R W R W R W R W R W R W R W R W R W Table 21 11 CSIGnCTL2 Register Contents Bit Position Bit Name Function 15 to 13 CSIGnPRS 2 0 Selects the value of the prescaler CSIGn PRS2 CSIG nPRS 1 CSIG nPRS 0 Prescaler Output PRSOUT 0 0 0 PCLK master mode 0 0 1 PCLK 2 master mode 0 1 0 PCLK 4 master mode 0 1 1 PCLK 8 master mode 1 0 0 PCLK 16 master mode 1 0 1 PCLK 32 master mo...

Page 1197: ...5 4 3 2 1 0 0 0 0 0 0 0 0 0 CSIGn TSF 0 0 1 CSIGn DCE 0 CSIGn PE CSIGn OVE R R R R R R R R R R R R R R R R Table 21 12 CSIGnSTR0 Register Contents 1 2 Bit Position Bit Name Function 7 CSIGnTSF Transfer status flag 0 Idle state 1 Transmission is in progress or being prepared Conditions for setting and clearing the bit are as follows Master Mode Set by Cleared by Transmit only mode Writing to the CS...

Page 1198: ...leared by writing 1 to CSIGnSTCR0 CSIGnPEC This bit is writable when CSIGnCTL0 CSIGnPWR is 0 This bit is initialized when CSIGnCTL0 CSIGnPWR changes from 0 to 1 or from 1 to 0 When setting to 1 due to parity error detection and clearing to 0 by writing to CSIGnSTCR0 CSIGnPEC occur simultaneously setting to 1 due to parity error detection takes precedence over clearing 0 CSIGnOVE Overrun error flag...

Page 1199: ...0 CSIGn DCEC 0 CSIGn PEC CSIGn OVEC R R R R R R R R R R R R W R W W Table 21 13 CSIGnSTCR0 Register Contents Bit Position Bit Name Function 3 CSIGnDCEC Controls the operation of clearing the data consistency check error flag CSIGnSTR0 CSIGnDCE 0 No operation Read value is always 0 1 Clear data consistency error flag CSIGnSTR0 CSIGnDCE 1 CSIGnPEC Controls the operation of clearing the parity error ...

Page 1200: ...t reception the CSIGnSCE bit has to be controlled as follows If CSIGnSLIT is 0 clear the bit before the last data reception reading from the CSIGnRX0 register If CSIGnSLIT is 1 clear the bit immediately after reception of all but the last of the data reading from the CSIGnRX0 register and at least one clock cycle of CSIGnTSCK before generation of the CSIGnTIR interrupt for completion of the last r...

Page 1201: ...an be read written in 32 bit units Address CSIGn_base0 1010H Initial value 0000 0000H This register is initialized by a reset from any source Caution Changing the contents of this register is only permitted when CSIGnCTL0 CSIGnPWR 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 CSIGn PS 1 0 CSIGn DLS 3 0 0 0 0 0 0 CSIGn DIR 0 CSIGn DAP R R R W R W R W R W R W R W R R R R R R W R R W 15 14 13...

Page 1202: ...rity Odd parity judged 1 1 Add even parity Even parity judged 27 to 24 CSIGnDLS 3 0 Specifies data length 0 Data length is 16 bits 1 Data length is 1 bit 2 Data length is 2 bits 15 Data length is 15 bits Caution The extended data length EDL function has to be used to set data lengths from 1 to 6 bits refer to Section 21 3 5 2 Data Length Greater than 16 Bits Transmitting twice consecutively with a...

Page 1203: ...is as follows CSIGnCTL1 CSIGnCKR 0 CSIGn DAP Clock and Data Phase Selection 0 1 CSIGnCTL1 CSIGnCKR 1 CSIGn DAP Clock and Data Phase Selection 0 1 Table 21 15 CSIGnCFG0 Register Contents 2 2 Bit Position Bit Name Function CSIGnTSI capture CSIGnTSCK CSIGnTSO D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 CSIGnTSI capture CSIGnTSCK CSIGnTSO D7 D6 D5 D4 D3 D2 D1 D0 CSIGnTSI capture CSIGnTSCK CSIGnTSO...

Page 1204: ...ster is forbidden when CSIGnCTL0 CSIGnTXE 0 and CSIGnCTL0 CSIGnRXE 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 CSIGn EDL 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R W R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CSIGnTX 15 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Table 21 16 CSIGnTX0W Register Contents Bit Position Bit Name Function 29 CSIGnEDL Specifies t...

Page 1205: ...SIGnEDLE 0 Access This register can be read written in 16 bit units Address CSIGn_base1 88H Initial value 0000H This register is initialized by a reset from any source Caution Writing to this register is forbidden when CSIGnCTL0 CSIGnTXE 0 and CSIGnCTL0 CSIGnRXE 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CSIGnTX 15 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Table 21 17 CSIGnTX0...

Page 1206: ...es from 0 to 1 or from 1 to 0 Caution 2 Reading from this register is forbidden when CSIGnCTL0 CSIGnTXE 0 and CSIGnCTL0 CSIGnRXE 0 Values read from the register while settings are as follows are undefined CSIGnPWR 0 CSIGnTXE 1 CSIGnRXE 1 CSIGnPWR 1 CSIGnTXE 0 CSIGnRXE 0 Caution 3 Reading from this register is possible when CSIGnCTL0 CSIGnPWR 1 Caution 4 Writing to this register is possible when CS...

Page 1207: ... CSIGnDLS 3 0 1000B MSB is transmitted first CSIGnCFG0 CSIGnDIR 0 CSIGnTIC interrupt is generated at the end of the transfer CSIGnCTL1 CSIGnSLIT 0 Normal clock and data phase CSIGnCTL1 CSIGnCKR 0 CSIGnCFG0 CSIGnDAP 0 The number of data packets is 10 0 to 9 Figure 21 25 Communication in Master Mode CSIGnTXE CSIGnRXE CSIGnTSCK CSIGnTSO CSIGnTSI CSIGnSTR0 CSIGnTSF CSIGnTIC CSIGnTIR Write to CPU 1 2 3...

Page 1208: ...w enabled 3 Write the first packet of data to be sent to the transmission register CSIGnTX0W or CSIGnTX0H Transmission starts automatically 4 After every packet that has been transmitted the interrupts CSIGnTIC and CSIGnTIR are generated CSIGnTIC indicates that the next packet can be written to CSIGnTX0W or CSIGnTX0H CSIGnTIR indicates that the reception register CSIGnRX0 must be read In this exam...

Page 1209: ...addresses of each UARTHn are listed in the following table Clock supply A single clock signal is input to each UARTHn as follows I O signals The I O signals of the UARTHn are listed in the table below Table 22 1 Instances of UARTHn Synchronous Asynchronous Serial Interface H Instances 2 Name UARTHn Table 22 2 UARTHn Register Base Addresses URTHn_base0 and URTHn_base1 UARTHn URTHn_base0 Address URT...

Page 1210: ...als Function Connected to URTHnTIT Transmission interrupt Interrupt controller INTURTHnIT DMA URTHnTIR Reception interrupt Interrupt controller INTURTHnIR DMA URTHnTIS Status interrupt Interrupt controller INTURTHnIS DMA Table 22 6 Port Groups for UARTHn UARTHn Channel Pin Name Group 1 2 3 UARTH0 URTH0SC P0_2 P1_9 P5_2 URTH0TXD P0_1 P1_8 P5_1 URTH0RXD P0_0 P1_7 P5_0 URTH0CTS P0_3 P5_3 URTH0RTS UAR...

Page 1211: ...Parity function odd even 0 or none Transmission stop bit s 1 or 2 MSB LSB first transfer selectable Inversion of data for transmission and received data is available 13 to 20 bits selectable for the BF break field in the LIN local interconnect network communication format Recognition of 11 bits or more possible for BF reception in LIN communication format BF reception flag provided BF reception ca...

Page 1212: ...unit Reception shift register Filter Selector Reception controller Send and receive data comparison Baud rate generator Transmission unit Transmission controller Baud rate generator Filter Selector Synchronizing clock control circuit Transmission shift register Filter Clock selector URTHnTIT URTHnTIS URTHnTIR URTHnRX URTHnCTL2 URTHnCTL0 URTHnSTR0 URTHnSTR1 URTHnOPT0 to URTHnOPT2 URTHnCTL1 URTHnTRG...

Page 1213: ...THn_base1 0CH Status register 0 URTHnSTR0 URTHn_base1 10H Status register 1 URTHnSTR1 URTHn_base1 14H Status clear register URTHnSTC URTHn_base1 18H Option register 0 URTHnOPT0 URTHn_base0 48H Option register 1 URTHnOPT1 URTHn_base1 04H Option register 2 URTHnOPT2 URTHn_base1 08H Receive data register URTHnRX URTHn_base1 1CH Receive data register HL URTHnRXHL URTHn_base1 20H Extension bit receive ...

Page 1214: ...PRSCLK clock and then set URTHnTXE to 1 again 5 URTHnRXE Reception operation enable 0 Disable reception operation 1 Enable reception operation To enable reception set URTHnPW to 1 and then set URTHnRXE to 1 To disable reception clear URTHnRXE to 0 or clear URTHnPW and URTHnRXE simultaneously To initialize the reception unit clear URTHnRXE to 0 wait for 2 cycles of the PRSCLK clock and then set URT...

Page 1215: ...HnRXE URTHnTXE 1 data consistency checking is enabled URTHnSLDC 1 and transmission is ongoing or completed Reception shall be disabled while enabling of transmission is maintained in this case follow the procedure below Check that transmission has not been executed URTHnSTR0 URTHnSSBT URTHnSTR0 URTHnSST 0 Disable reception by setting URTHnCTL0 URTHnRXE 0 The reason for this procedure is that the d...

Page 1216: ...nction 15 URTHnSLBM BF reception mode selection 0 BF reception during data reception disabled 1 BF reception during data reception enabled Changing this bit is only allowed while reception is disabled URTHnCTL0 URTHnPW 0 or URTHnCTL0 URTHnRXE 0 14 to 12 URTHnBLG 2 0 BF bit length during transmission URTHnBLG2 URTHnBLG1 URTHnBLG0 BF Length 1 0 1 13 bits 1 1 0 14 bits 1 1 1 15 bits 0 0 0 16 bits 0 0...

Page 1217: ...the URTHnTXD output level immediately regardless of the values of URTHnCTL0 URTHnPW and URTHnCTL0 URTHnTXE Therefore if URTHnTDL is set to 1 while operations are disabled the URTHnTXD outputs low level Changing this bit is only allowed while transmission is disabled URTHnCTL0 URTHnPW 0 or URTHnCTL0 URTHnTXE 0 4 URTHnRDL Received data level control 0 No inverted input of received data 1 Inverted in...

Page 1218: ... direction selection 0 MSB first transfer 1 LSB first transfer When the transmission reception is performed in the LIN format set URTHnSLD to 1 Changing this bit is only allowed while transmission and reception are disabled URTHnCTL0 URTHnPW 0 or URTHnCTL0 URTHnRXE URTHnCTL0 URTHnTXE 0 0 URTHnSLIT Transmission interrupt request URTHnTIT timing selection 0 URTHnTIT is generated when transmission st...

Page 1219: ... Table 22 3 UARTHn Clock Supply 15 14 13 12 11 10 9 8 URTHnPRS 2 0 0 URTHnBRS 11 8 R W R W R W R R W R W R W R W 7 6 5 4 3 2 1 0 URTHnBRS 7 0 R W R W R W R W R W R W R W R W Table 22 10 URTHnCTL2 Register Contents Bit Position Bit Name Function 15 to 13 URTHnPRS 2 0 Prescaler clock PRSCLK division value 0 PRSCLK PCLK 20 1 PRSCLK PCLK 21 2 PRSCLK PCLK 22 3 PRSCLK PCLK 23 4 PRSCLK PCLK 24 5 PRSCLK P...

Page 1220: ...tten to this bit during reception processing the current reception processing is terminated Consequently the received value is not stored the framing parity and overflow error bits are not updated on the basis of the received data and no interrupts are generated Meanwhile the value of the BF counter stays in continuous use After BF reception the reception status is set according to the URTHnCTL1 U...

Page 1221: ...fore BF transmission is completed the BF will only be transmitted once When transmission is enabled URTHnCTL0 URTHnPW URTHnCTL0 URTHnTXE 1 writing 1 to this bit clears all previously set data transmission requests for which the data have not been transmitted leaving only any BF transmission request If a new value is written to the URTHnTX URTHnTX 7 0 bits after 1 is written to this bit the data ar...

Page 1222: ...R R R R Note 1 These bits are also initialized if reception is disabled by URTHnCTL0 URTHnRXE 0 Note 2 These bits are also initialized if transmission is disabled by URTHnCTL0 URTHnTXE 0 Table 22 12 URTHnSTR0 Register Contents Bit Position Bit Name Function 6 URTHnSSBR BF reception enable disable status indication 0 BF reception disabled 1 BF reception has been enabled by setting URTHnTRG URTHnBRT...

Page 1223: ...it is set to 1 if ID value matched when ID comparison is enabled URTHnOPT1 URTHnIDCN 1 by transfer of extension bit 9th bit and the extension bit detection interrupt is enabled URTHnOPT0 URTHnEGE 1 For details on ID match detection refer to Section 22 6 5 Extension bit Detection ID Compare Match Detection 5 URTHnEBD Extension bit detection flag 0 Extension bit of received data is not detected 1 Ex...

Page 1224: ...lue to URTHnTX Further transmission can now proceed 2 URTHnPE Parity error flag 0 Parity error is not detected in received data 1 Parity error is detected in received data The operation of URTHnSTR URTHnPE is controlled by the settings of the URTHnCTL1 URTHnSLP 1 0 Note In consecutive two frame reception mode this reflects the state of reception of 2 frames being completed 1 URTHnFE Framing error ...

Page 1225: ...EB Controls clearing of the extension bit detection flag URTHnSTR1 URTHnEBD bit 0 Writing 0 is ignored 1 Writing 1 clears URTHnSTR1 URTHnEBD 4 URTHnCLBS Controls clearing of the BF reception successful flag URTHnSTR1 URTHnBSF bit 0 Writing 0 is ignored 1 Writing 1 clears URTHnSTR1 URTHnBSF 3 URTHnCLDC Controls clearing of the data consistency error flag URTHnSTR1 URTHnDCE bit 0 Writing 0 is ignore...

Page 1226: ...and disables operation with the extension bit 0 Disables extension bit operation The bit length set for transmission and reception URTHnCTL1 URTHnCLG is used in transmitting and receiving data 1 Enables extension bit operation The character length used in transmitting and receiving data is 9 bits an extension bit is appended to each 8 bit character for transmission and reception The setting of thi...

Page 1227: ...RTHnCTL1 URTHnRDL While ID comparison is enabled URTHnOPT1 URTHnIDCN 1 a match in ID comparison after detection of the extension bit produces an extension bit detection interrupt Changing this bit is only allowed while the UARTHn operation is disabled URTHnCTL0 URTHnPW 0 For details on extension bit detection refer to Section 22 6 5 Extension bit Detection ID Compare Match Detection 12 URTHnSCFR E...

Page 1228: ...ster The master outputs the synchronizing clock for use in transmission and reception 1 Slave The synchronizing clock supplied by the master is used in transmission and reception Changes to this bit only become effective when clock synchronous mode is selected URTHnSAS 1 Changing this bit is only allowed while UARTHn operation is disabled URTHnCTL0 URTHnPW 0 3 URTHnSAS Selects the operating mode f...

Page 1229: ...5 4 3 2 1 0 URTHn IDCN 0 0 0 0 0 0 0 R W R R R R R R R Table 22 16 URTHnOPT1 Register Contents Bit Position Bit Name Function 7 URTHnIDCN Enables and disables ID match detection 0 ID match detection at the time of transfer of an extension bit 9th bit is disabled 1 ID match detection at the time of transfer of an extension bit 9th bit is enabled The setting of this bit is not effective when the uni...

Page 1230: ...1 0 URTHnMID 7 0 R W R W R W R W R W R W R W R W Table 22 17 URTHnOPT2 Register Contents Bit Position Bit Name Function 15 to 8 URTHnIDCD 7 0 Sets the ID value for comparison at the time the extension bit 9th bit is transferred For details on extension bit detection refer to Section 22 6 5 Extension bit Detection ID Compare Match Detection 7 to 0 URTHnMID 7 0 Specifies which bits of the ID values ...

Page 1231: ...n data formats refer to Section 22 6 1 Data Formats Overrun error When an overrun error URTHnSTR1 URTHnOVE 1 occurs data received at the time are not transferred to URTHnRX but are discarded When processing for reception ends and data reception is confirmed without any overrun errors the received data are stored in the URTHnRX register in the specified storage format This register is writable if U...

Page 1232: ...e with 9 bits of data This register corresponds to bits 15 to 0 in the URTHnERXW register Access This register can be read in 16 bit units Address URTHn_base1 20H Initial value FFFFH A reset from any source or when UARTHn operation is enabled setting URTHnCTL0 URTHnPW 1 will initialize the bits 15 14 13 12 11 10 9 8 URTHnRX 15 8 R R R R R R R R 7 6 5 4 3 2 1 0 URTHnRX 7 0 R R R R R R R R Table 22 ...

Page 1233: ...bits 23 to 16 in the URTHnERXW register Access This register can be read in 8 bit units Address URTHn_base1 24H Initial value 11H A reset from any source or when UARTHn operation is enabled setting URTHnCTL0 URTHnPW 1 will initialize the bits 7 6 5 4 3 2 1 0 0 0 0 URTHn ERXH8 0 0 0 URTHn ERXL8 R R R R R R R R Table 22 20 URTHnERX Register Contents Bit Position Bit Name Function 4 URTHn ERXH8 Exten...

Page 1234: ...ress URTHn_base1 28H Initial value 0011FFFFH A reset from any source or when UARTHn operation is enabled setting URTHnCTL0 URTHnPW 1 will initialize the bits 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 R R R R R R R R 23 22 21 20 19 18 17 16 0 0 0 URTHn ERXH8 0 0 0 URTHn ERXL8 R R R R R R R R 15 14 13 12 11 10 9 8 URTHnRX 15 8 R R R R R R R R 7 6 5 4 3 2 1 0 URTHnRX 7 0 R R R R R R R R Table 22 21 URT...

Page 1235: ... data transfer URTHnRX 7 0 1 frame 7 bit data transfer MSB first URTHnRX 7 1 1 frame 7 bit data transfer LSB first URTHnRX 6 0 1 frame extension bit transfer URTHnRX 7 0 URTHnRX8 or URTHnERXL8 2 frame 8 bit data transfer 1st frame URTHnRX 15 8 2nd frame URTHnRX 7 0 2 frame 7 bit data transfer MSB first 1st frame URTHnRX 15 9 2nd frame URTHnRX 7 1 2 frame 7 bit data transfer LSB first 1st frame URT...

Page 1236: ...THnTX 7 1 is transferred to the shift register For details on data formats refer to Section 22 6 1 Data Formats Access This register can be read written in 8 bit units Address URTHn_base1 2CH Initial value FFH This register is initialized by a reset from any source When transmission and reception are enabled URTHnCTL0 URTHnPW URTHnTXE 1 writing to this register triggers the start of transmission N...

Page 1237: ...ion This register corresponds to bits 15 to 0 in the URTHnETXW register Access This register can be read written in 16 bit units Address URTHn_base1 30H Initial value FFFFH A reset from any source or when UARTHn operation is enabled setting URTHnCTL0 URTHnPW 1 will initialize the bits 15 14 13 12 11 10 9 8 URTHnTX 15 8 R W R W R W R W R W R W R W R W 7 6 5 4 3 2 1 0 URTHnTX 7 0 R W R W R W R W R W...

Page 1238: ...responds to the bits 23 to 16 in the URTHnETXW register Access This register can be read written in 8 bit units Address URTHn_base1 34H Initial value 11H A reset from any source or when UARTHn operation is enabled setting URTHnCTL0 URTHnPW 1 will initialize the bits 7 6 5 4 3 2 1 0 0 0 0 URTHn ETXH8 0 0 0 URTHn ETXL8 R R R R W R R R R W Table 22 25 URTHnETX Register Contents Bit Position Bit Name ...

Page 1239: ...it units Address URTHn_base1 38H Initial value 0011FFFFH A reset from any source or when UARTHn operation is enabled setting URTHnCTL0 URTHnPW 1 will initialize the bits 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 R R R R R R R R 23 22 21 20 19 18 17 16 0 0 0 URTHn ETXH8 0 0 0 URTHn ETXL8 R R R R W R R R R W 15 14 13 12 11 10 9 8 URTHnTX 15 8 R W R W R W R W R W R W R W R W 7 6 5 4 3 2 1 0 URTHnTX 7 0...

Page 1240: ...ata transfer URTHnTX 7 0 1 frame 7 bit data transfer MSB first URTHnTX 7 1 1 frame 7 bit data transfer LSB first URTHnTX 6 0 1 frame extension bit transfer URTHnTX 7 0 URTHnTX8 or URTHnETXL8 2 frame 8 bit data transfer First frame URTHnTX 15 8 Second frame URTHnTX 7 0 2 frame 7 bit data transfer MSB first 1st frame URTHnTX 15 9 2nd frame URTHnTX 7 1 2 frame 7 bit data transfer LSB first 1st frame ...

Page 1241: ...EG0 0131 IC0REG0 0130 IC0REG0 0121 IC0REG0 0120 R W R W R W R W R W R W R W R W 23 22 21 20 19 18 17 16 IC0REG0 0111 IC0REG0 0110 IC0REG0 0101 IC0REG0 0100 IC0REG0 0091 IC0REG0 0090 IC0REG0 0081 IC0REG0 0080 R W R W R W R W R W R W R W R W 15 14 13 12 11 10 9 8 IC0REG0 0071 IC0REG0 0070 IC0REG0 0061 IC0REG0 0060 IC0REG0 0051 IC0REG0 0050 IC0REG0 0041 IC0REG0 0040 R W R W R W R W R W R W R W R W 7 ...

Page 1242: ...he first bit starts the start bit in data transmission or the first bit of the BF in BF transmission During data transmission a transmission interrupt request is issued when data for transmission in the URTHnTX register are transferred to the transmission shift register At the end of transmission processing URTHnCTL1 URTHnSLIT 1 A transmission interrupt request is issued on completion of transmiss...

Page 1243: ...5 3 Status Interrupt Request URTHnTIS A status interrupt request URTHnTIS is generated in accord with the settings of status register 1 URTHnSTR1 if an error condition is satisfied during reception or transmission When the BF reception mode selection bit is set in LIN communications mode URTHnCTL1 URTHnSLBM 1 the status interrupt request signal is generated when 11 or more consecutive bits at the ...

Page 1244: ...ngth extension bit LSB first even parity 1 stop bit data for transfer 155H b 9 bit data length extension bit MSB first even parity 1 stop bit data for transfer 155H Table 22 29 Data Format Specification Item Options Control Bits Start bit 1 bit Fixed Character bits 7 bits 8 bits 9 bits URTHnCTL1 URTHnCLG Parity Even parity odd parity 0 parity no parity URTHnCTL1 URTHnSLP 1 0 Number of stop bits 1 ...

Page 1245: ...a for transfer 55H e 8 bit data length MSB first even parity 1 stop bit data for transfer 55H URTHnTTXD inverted f 7 bit data length LSB first odd parity 2 stop bits data for transfer 36H D0 D1 D2 D3 D4 D5 D6 D7 1 data frame Start bit Parity bit Stop bit D7 D6 D5 D4 D3 D2 D1 D0 1 data frame Start bit Parity bit Stop bit D7 D6 D5 D4 D3 D2 D1 D0 1 data frame Start bit Parity bit Stop bit 1 data fram...

Page 1246: ...e 1246 of 1538 Jul 17 2014 V850E2 PG4 L Section 22 Synchronous Asynchronous Serial Interface H UARTH g 8 bit data length LSB first no parity 1 stop bit data for transfer 87H 1 data frame D0 D1 D2 D3 D4 D5 D6 D7 Start bit Stop bit ...

Page 1247: ...are sampled on falling edges of the synchronizing clock a Examples of operation in delayed sampling mode master reception D3 D4 D5 D6 D7 Parity Stop D1 D2 D0 Start URTHnSC pin output URTHnTXD pin output D0 D1 D2 D3 D4 D5 D7 Parity D1 D2 D3 D4 D5 D6 D7 Parity D0 D1 D2 D3 D4 D5 D6 D7 Parity D6 Stop D0 Stop Stop Start Start Start Internal sampling data URTHnSC pin output URTHnTXD pin output URTHnRXD ...

Page 1248: ...ess 1 frame of data will still be transmitted a Example of handshake signals to wait for permission from URTHnCTS in transmission b Example of handshake signals to wait for writing of data in transmission State of operation URTHNnTXD pin URTHnCTS pin input URTHnTIT interrupt State of the transmit data register URTHnTXE bit 1 Waiting for CTS Initialization Data transmission Waiting for CTS Data tra...

Page 1249: ...ignal must be placed at the inactive level at the time of sampling of the first bit of received data a Example of handshake signals in reception State of operation L URTHnTXD pin URTHnCTS pin input URTHnTIT interrupt State of the transmit data register Initialization Data transmission Data transmission Waiting for CTS Empty Full Empty Full Empty Writing to the transmit data register Writing to the...

Page 1250: ...TL1 URTHnSLIT 0 Caution In the consecutive two frame transfer the transmit data register is only accessible in 16 bit units Do not write to this register in 8 bit units D8 D9 D10 D11 D12 D13 D14 D15 SP ST ST D0 D1 D2 D3 D4 D5 D6 D7 P P SP Higher order frame D15 D14 D13 D12 D11 D10 D9 D8 SP ST ST D7 D6 D5 D4 D3 D2 D1 D0 P P SP Higher order frame Lower order frame Lower order frame Format of consecu...

Page 1251: ... Caution In the consecutive two frame transfer the transmit data register is only accessible in 16 bit units Do not write to this register in 8 bit units D1 D2 D3 D4 D4 D1 D2 D3 D4 D5 D5 D6 D2 URTHnTIT interrupt URTHnTXHL register Transmission shift register Sub buffer Note A transmission enable interrupt is generated at the end of transmission Frame transmission D1D2 D3D4 D5D6 D1 D2 D3 D4 D1 D1 D...

Page 1252: ...comparison in extension bit detection while URTHnOPT1 URTHnIDCN 1 the ID comparison match flag is set to URTHnSTR1 URTHnIDM 1 which enables data reception Data are not received if the ID does not match the settings for ID comparison Moreover bits for which the corresponding URTHnOPT2 URTHnMID 7 0 bit is 1 are not included in ID comparison i e these bits are masked URTHnSTR1 URTHnIDM is cleared whe...

Page 1253: ... the level of the extension bit matches the detection condition so a status interrupt URTHnTIS is generated Note 5 Extension bit detection and ID comparison are enabled URTHnOPT1 URTHnIDCN 1 during the transfer of DATA4 and the level of the extension bit does not match the detection condition so neither a reception interrupt URTHnTIR nor a status interrupt URTHnTIS is generated Note 6 Extension bi...

Page 1254: ... baud rate information and the slave receives it and corrects the baud rate error Therefore communications are possible when the baud rate error of the slave is 14 or less For an outline of LIN transmission and reception refer to Figure 22 5 LIN Transmission in Outline and Figure 22 6 LIN Reception in Outline Figure 22 5 LIN Transmission in Outline Note 1 The interval between each field is control...

Page 1255: ...e BF reception mode Note 3 An interrupt is generated as follows in accord with the setting of the BF reception mode selection bit URTHnCTL1 URTHnSLBM on the normal completion of BF reception a reception interrupt URTHnTIR is generated if URTHnCTL1 URTHnSLBM is set to 0 and a status interrupt URTHnTIS is generated and the BF reception success flag URTHnSTR1 URTHnBSF is set if URTHnCTL1 URTHnSLBM is...

Page 1256: ...BF Transmission Setting both the URTHnPW and URTHnTXE bits in URTHnCTL0 to 1 places the interface in the transmission enabled state after which BF transmission is started by setting the BF transmission trigger URTHnTRG URTHnBTT to 1 Thereafter URTHnSTR0 URTHnSSBT is set to 1 and the low level is output over a width of 13 to 20 bits as specified by URTHnCTL1 URTHnBLG 2 0 A transmission interrupt UR...

Page 1257: ...lid BF reception the response depends on the value of the BF reception mode selection bit A reception interrupt URTHnTIR is generated if URTHnCTL1 URTHnSLBM 0 A status interrupt URTHnTIS is generated and the BF reception success flag URTHnSTR1 URTHnBSF is set if URTHnCTL1 URTHnSLBM 1 The URTHnSTR0 URTHnSSBR bit is automatically cleared and BF reception ends Figure 22 8 Normal BF Reception Detectio...

Page 1258: ...igure 22 9 Error in BF Reception Detection as Stop Bits within 10 5 Bits at the Low Level The URTHnSTR1 URTHnBSF bit indicates the state of successful reception of the BF Note URTHnSTR0 URTHnSSBR is set to 1 by setting URTHnTRG URTHnBRT to 1 and is cleared by normal BF reception 2 10 5 URTnTIR URTHnBSF URTHnSTR1 10 9 8 7 6 5 4 3 1 ...

Page 1259: ... not checked for consistency while transmission is suspended Consistency between the levels of the transmitted data and of the input data is checked even if reception is disabled during transmission In this case the receive completion interrupt request signal URTHnTIR does not occur and status bits of URTHnSTR1 URTHnBSF URTHnFE and URTHnOVE are not set either but when a consistency error occurs th...

Page 1260: ...are stopped immediately even during transmission processing Concurrent BF and data transmission When a BF transmit request and a data transmit request have both been set BF transmission takes priority Data consistency check On detection of a data consistency error further data are not transmitted until URTHnSTC URTHnCLDC 1 URTHnCTL0 URTHnPW 0 or URTHnCTL0 URTHnTXE 0 is written After an error is de...

Page 1261: ...he data register while data transmission is in progress Caution If a value is written to the URTHnTX register before the URTHnTIT is generated previously set data for transmission are overwritten by the new data To initialize the transmission unit by setting URTHnTXE 0 or URTHnPWR 0 confirm that no transmission is ongoing i e that URTHnSTR0 URTHnSSBT URTHnSST 0 Initialization while transmission is...

Page 1262: ...nsmission Operation Timing Transmission End Data 1 Data 1 Data 2 Data 2 Data 1 Data 3 Data 2 URTHnTXD signal URTHnTX Transmission shift register URTHnTIT URTHnSTR0 URTHnSST Start Start Parity Stop Start Stop Parity Data n 1 Data n 1 Data n 1 Data n FF Data n Data n URTHnTXD signal URTHnTX Start Stop Parity Reception shift register Start Stop Parity Stop Parity URTHnTIT URTHnSTR0 URTHnSST URTHnCTL0...

Page 1263: ...t baud rate When the reception interrupt URTHnTIR is asserted upon reception of the stop bit the data stored in the reception shift register are written to the receive data register URTHnRX Reception stop When URTHnCTL0 URTHnPW or URTHnCTL0 URTHnRXE is set to 0 reception operations are stopped immediately even during reception processing Reception errors If an overrun error occurs URTHnSTR1 URTHnO...

Page 1264: ... the URTHnCTL0 URTHnPW or URTHnCTL0 URTHnRXE bit to 0 If the URTHnCTL0 URTHnPW or URTHnCTL0 URTHnRXE bit is cleared to 0 before the URTHnTIR is generated the value read from the URTHnRX register cannot be guaranteed Caution 4 If processing to indicate completion of reception generation of the URTHnTIR interrupt and clearing of the URTHnCTL0 URTHnPW or URTHnCTL0 URTHnRXE bit to 0 occur simultaneous...

Page 1265: ...t in the status clear register URTHnSTC Note Even in case of a parity or framing error data are transferred from the reception shift register to the receive data register URTHnRX Consequently the data from URTHnRX must be read Otherwise an overrun error URTHnSTR1 URTHnOVE 1 will occur when reception of the next data is completed In case of an overrun error data in the reception shift register are ...

Page 1266: ...ta including the parity bit is counted An odd result produces a parity error 2 Odd parity During transmission In the opposite way to even parity the parity bit is controlled so that the number of bits having the value 1 among the data is odd The values of the parity bit are as follows Odd number of bits having the value 1 among those for transmission 0 Even number of bits having the value 1 among ...

Page 1267: ...r output clock PRSCLK as the sampling clock When the same sampling value is read twice the signal of each pin is validated as the input data Therefore data not exceeding the width of 2 prescaler output clocks is judged to be noise and thus eliminated The noise filter leads to a delay of 4 cycles of the clock signal output by the prescaler PRSCLK from capture of each serial bit until it is forwarde...

Page 1268: ...LK 2URTHnPRS 2 0 PRSCLK is further divided by the baud rate generator by a value determined by URTHnCTL2 URTHnBRS 11 0 The baud rate generator distinguishes between the baud rate for data frames and BF receptions as listed in the table below The BF reception clock is the double of the baud rate clock BRCLK PCLK PRSCLK URTHnCTL2 URTHnPRS 2 0 URTHnCTL2 URTHnBRS 11 0 Prescaler Baud rate generator BRC...

Page 1269: ... to TAUB0 Using this function leads to activation of the detection of baud rates in LIN communications as a slave Note the following points when using this facility Use TAUB0 in an operating mode in which baud rate detection is possible Do not change the settings of the IC0REG0 register while the timer is in operation Do not use this function to connect a serial data input pin to TAUB0 for any pur...

Page 1270: ...4154 µPD70F4155 ADC Instance represented by n 1 n 0 Number of analog input pins represented by m 18 m 1 to 18 Number of channel groups represented by i 3 i 0 to 2 Register base address ADCAn_base0 1 FF81 D000H ADCAn_base1 1 FFFF DC00H Resolution 10 or 12 bits Conversion result check Available Discharge Available Hardware trigger expansion Available Channel sample and hold represented by x 6 x 1 to...

Page 1271: ...0 ADCA0TTIN005 TSG20 TS0ADTRG1 ADCA0TTIN006 Not connected ADCA0TTIN007 Not connected ADCA0TTIN008 Port ADCA0TRG0 ADCA0TTIN009 Not connected ADCA0TTIN010 Not connected ADCA0TTIN011 Not connected ADCA0TTIN012 Not connected ADCA0TTIN013 Not connected ADCA0TTIN014 Not connected ADCA0TTIN015 Not connected CG1 ADCA0TTIN100 PIC ADOPA1ADCATTIN00 ADCA0TTRG1 ADCA0TTIN101 Not connected ADCA0TTIN102 ENCA0 INT...

Page 1272: ...TIN201 Not connected ADCA0TTIN202 ENCA0 INTENCA0I1 ADCA0TTIN203 Not connected ADCA0TTIN204 TSG20 TS0ADTRG0 ADCA0TTIN205 TSG20 TS0ADTRG1 ADCA0TTIN206 Not connected ADCA0TTIN207 Not connected ADCA0TTIN208 Port ADCA0TRG2 ADCA0TTIN209 TAPA0 TAPA0TADOUT1 ADCA0TTIN210 Not connected ADCA0TTIN211 Not connected ADCA0TTIN212 Not connected ADCA0TTIN213 Not connected ADCA0TTIN214 Not connected ADCA0TTIN215 No...

Page 1273: ... A D conversions of up to 3 differently prioritized groups of channels One shot and continuous A D conversion modes channel group 0 only Autorepeat function channel repeat mode Software and hardware start trigger modes Selectable hardware trigger source from multiple input signals Configurable channels on which A D conversion end interrupt is generated at conversion completion Three types of conve...

Page 1274: ...tus ADCAnC02CR Status ADCAnC22CR Status ADCAnC23CR Status The latest A D conversion results The latest A D conversion results of CGi The latest A D conversion resluts of CHm ADCAnDGCR The A D conversion results of reference voltage ADCAnLL ADCAnUL INTADCAnTERR ADCAnIx INTADCAnT0 INTADCAnTLLT INTADCAnT1 INTADCAnT2 ADCAnCNV0 ADCAnCNV1 ADCAnCNV2 ADCAnTTRG0 ADCAnTTRG1 ADCAnTSEL0 ADCAnTTRG2 PCLK ADCAnT...

Page 1275: ...n is performed repeatedly A D conversion The A D conversion can be triggered by software or hardware A multiplexer selects the channel to be converted and the common sample and hold circuit holds the input voltage The successive approximation register SAR holds the output voltage values of the digital to analog converter DAC to be compared with the analog input voltage values as the 10 bit or 12 b...

Page 1276: ...internal sampling capacitor during A D sampling Self diagnosis functions The following 4 self diagnosis functions are provided to verify that the ADCAn works properly and to detect open analog input pins Diagnosis of the A D conversion circuit Diagnosis of the channel multiplexer Diagnosis of the analog input pins Diagnosis of the channel sample and hold circuit Available stabilization time The op...

Page 1277: ...AnRCKm and specify the lower and upper limits in ADCAnLL and ADCAnUL 4 If you want the capacitor of the sample and hold circuit to be discharged before sampling a new value enable the discharge function by setting ADCAnCTL1 ADCAnDISC to 1 5 Enable or disable the buffer amplifier by setting ADCAnCTL1 ADCAnBPC If you use the channel S H function enable the buffer amplifier function 6 Enable the A D ...

Page 1278: ...mit comparison function for A D conversion results has been enabled 11 Before you reconfigure the A D converter disable it by clearing ADCAnCTL0 ADCAnCE to 0 Note The self diagnosis functions are described in Section 23 3 11 Self Diagnosis Functions 23 3 2 Clock Usage The ADCAn clock ADCAnTCLK is derived from PCLK The division ratio is specified in ADCAnCTL1 ADCAnFR 1 0 Caution The maximum and min...

Page 1279: ...er priority CG is set Depending on the setting in ADCAnCTL1 ADCAnTRMi there are 2 options The A D conversion of CG is interrupted immediately ADCAnCTL1 ADCAnTRMi 0 After the A D conversions of all the higher priority CGs are finished the A D conversion of the interrupted channel is resumed The A D conversion of the current channel is completed before the higher priority CG is converted ADCAnCTL1 A...

Page 1280: ...il A D Conversion of Current Channel is Completed ADCAnCTL1 ADCAnTRM0 1 Status Conversion of CG0 Idle CG0 CH3 Convert Convert CG2 CH5 CG0 CH9 Sample Sample Convert Convert Sample Sample Convert Sample CG2 CH9 CG0 CH20 Conversion of CG2 Conversion of CG0 Idle CG0 CH3 CH9 CH20 CG2 CH5 CH9 Start trigger CG0 Start trigger CG2 ...

Page 1281: ... in one shot conversion mode regardless of the conversion mode settings For CG0 the A D conversion mode can be set in ADCAnCTL1 ADCAnMD0 Mode Operation Channel Group One shot conversion mode One shot conversion mode can specify following modes When channel repeat mode is not used ADCAnCTL0 ADCAnSTM 0 the scan list conversion is performed one time When channel repeat mode is used ADCAnCTL0 ADCAnSTM...

Page 1282: ...s by ADCAnCTL0 ADCAnSCTi 1 0 Figure 23 5 When channel repeat mode is used repeat two times CG0 CH3 CH9 Scan list conversion is performed one time Conversion state CG0 conversion Conversion Conversion Start Trigger CG0 CH3 CH9 First CH3 conversion First CH9 conversion Idle Idle Sampling Sampling CG0 CH3 CH9 Scan list conversion of each channel is performed two times Conversion state CG0 conversion ...

Page 1283: ...uring performing of a high priority CG conversion Figure 23 7 Operation When Start Trigger is Input Before Completion of Conversion Input High Priority Start Trigger CG0 CH3 Scan list conversion is performed one time in one shot conversion mode Conversion state CG0 conversion by first start trigger CG0 CG0 conversion by second start trigger CG0 CG0 conversion by fourth start trigger CG0 Conversion...

Page 1284: ...er is generated or another stop condition occurs see Section 23 3 6 Stopping A D Conversion Stop Trigger Figure 23 8 Continuous Conversion Mode Caution The idle state is entered after a stop trigger is generated and the sampling and conversion are not performed Note Additional start triggers for CG0 are ignored in continuous conversion mode Status 1st conversion of CG0 Idle CH3 Convert Sample Conv...

Page 1285: ...ut all the other additional start triggers of the same CGi are ignored see Figure 23 6 Operation When Start Trigger is Input Before Completion of Conversion Note 3 In continuous conversion mode additional start triggers that are generated before a stop trigger is generated are ignored 1 Software Start Trigger The A D conversion of CGi is triggered by setting ADCAnTRGi ADCAnSTTi to 1 if the A D con...

Page 1286: ...e For units to which the hardware trigger signals are connected see Table 23 2 Units to which Hardware Trigger Signals are Connected Hardware start trigger timing The A D converter starts A D conversion when a valid edge of ADCAnTTRGi is detected The following figure shows the timing of a hardware start trigger under the following conditions ADCAnTCLK clock PCLK 2 ADCAnCTL1 ADCAnFR 1 0 01B Valid e...

Page 1287: ...er The A D converter is powered off ADCAnCTL1 ADCAnGPS 0 The A D converter is disabled ADCAnCTL0 ADCAnCE 0 Caution When a hardware trigger is used set the ADCAnCTL1 ADCAnTiETS 1 0 bits to 00B the valid edge of the hardware conversion trigger is not detected before disabling the A D converter so that the start trigger is not generated ...

Page 1288: ...put voltage to the sample hold circuit The buffer amplifier time is the time over which the buffer amplifier is operating Sampling for A D conversion proceeds even while the buffer amplifier is operating The A D conversion time is the time required to obtain one digital value from an analog input voltage The channel S H hold wait time is the time after the analog input is sampled until the value h...

Page 1289: ...ling time us A D conversion time us ADCAn CTL1 ADCAn FR 1 0 ADCAn SHHWCNT ADCAn SHHWCNT 4 0 2 ADCAn DISCNT A DCAn DISCNT 3 0 ADCAn AMPCNT ADCAn AMPCNT 3 0 3 ADCAn SMCNT ADCAn ADNSMP 7 0 80 PCLK 2 1 600 0 325 0 525 0 750 0 100 01H 8H CH AH 22H 64 PCLK 2 1 813 0 344 0 531 0 938 0 125 01H 7H AH 8H 1CH 48 PCLK 1 458 0 333 0 500 0 625 0 104 00H AH FH CH 28H 40 PCLK 1 575 0 325 0 500 0 750 0 125 00H 8H ...

Page 1290: ...the update time depends on writing to ADCAnCGi always write to ADCAnIOCi before ADCAnCGi if you want to change the interrupt generation for a CG 2 Error Interrupt INTADCAnTERR The error interrupt INTADCAnTERR is generated in the following cases If the A D conversion result of a specified channel is outside the specified range with the upper lower limit comparison for A D conversion results enabled...

Page 1291: ...bits 15 to 00 They also provide additional information for example status flags allowing to check the A D conversion result see Section 23 3 10 Result Check Functions Figure 23 13 Storage of AD Conversion Results Status Conversion of CG0 Idle ADCAnLCR Status ADCAnDB0CR Status ADCAnDB1CR Status ADCAnDB2CR Status ADCAnC00CR Status ADCAnC01CR Status ADCAnC02CR Status ADCAnC m 1 CR Status ADCAnCmCR St...

Page 1292: ...e and A D Conversion Result There is a relationship between the analog input voltages that are input to the analog input pin ADCAnIm and the A D conversion result values values of the ADCAnLCR 15 00 bits ADCAnCmCR 15 00 bits and ADCAnDBiCR 15 00 bits as shown in the following equations or INT A function which returns the integer part of the value in parentheses VIAN Analog input voltage AVREFnP AV...

Page 1293: ...version result 8192 1 3 2 1 0 8192 2 8192 3 8192 4 8192 5 8192 6 8192 8187 8192 8188 8192 8189 8192 8190 8192 8191 1 VIAN AVREFnM AVREFnP AVREFnM 1023 1022 1021 A D conversion result 2048 1 3 2 1 0 2048 2 2048 3 2048 4 2048 5 2048 6 2048 2043 2048 2044 2048 2045 2048 2046 2048 2047 1 VIAN AVREFnM AVREFnP AVREFnM i When the conversion characteristics of 12 bit A D converter are applied ADCAnCTL1 AD...

Page 1294: ... interrupt The error interrupt INTADCAnTERR is generated if an A D conversion result in ADCAnLCR ADCAnDBiCR or ADCAnCmCR is overwritten before it is read For the conversion result register that the stored conversion result is not read out an error interrupt should be masked by appropriately setting ADCAnCTL0 ADCAnOEM 4 0 Do not perform the overwrite check for A D conversion result Unless an error ...

Page 1295: ...onversion result of a specified channel is below the lower limit or above the upper limit the corresponding error flag ADCAnSTR0 ADCAnRCE is set to 1 ADCAnSTR0 indicates the error status of upper lower limit comparison for the latest A D conversion result for every channel This register can be used to check which A D conversion results are outside the specified range The value of the result check ...

Page 1296: ...The figure below outlines the self diagnosis functions which are explained in detail in the following sections Figure 23 15 Outline of Self Diagnosis Functions Internal pull down resistor Internal pull down resistor Internal pull down resistor Internal pull down resistor Internal pull down resistor Multiplexer Common S H DIAGOUT0 DIAGOUT1 DIAGOUT2 ADDIAGOUT ADCAnIx ADCAnIm ADCAnDGCTL1 ADCAnCDG01 A...

Page 1297: ...r malfunction The diagnostic A D conversion is enabled by setting ADCAnCG0 ADCAnDIAG to 1 Note The diagnosis of A D conversion circuit is available for CG0 only The diagnostic A D conversion is started after the A D conversion of the last channel of CG0 is completed The A D conversion results of CG0 are stored in the normal A D conversion result register see Section 23 3 9 1 A D Conversion Result ...

Page 1298: ...SEL 2 0 bits to diagnosis voltage 5 Set ADCAnCG0 ADCAnDIAG bit to 1 Operation when writing is performed during A D conversion is shown in the figure below Figure 23 16 Writing during A D Conversion Note The value set in ADCAnDGCTL0 ADCAnPSEL 2 0 becomes valid after completion of current channel conversion Therefore set the reference voltage of the next diagnostic A D conversion by the start of the...

Page 1299: ...0 To diagnose the channel multiplexer different reference voltages can be input to the channels The diagnosis voltage of channel multiplexer diagnostic is changed as the procesure below 1 If conversion is under processing ADCAnCTL0 ADCAnCE bit 1 stop it ADCAnCTL0 ADCAnCE bit 0 2 Set ADCAnDGCTL0 ADCAnPSEL 2 0 bits to 011 B 3 Set ADCAnDGCTL0 ADCAnPSEL 2 0 bits to diagnosis voltage Table 23 5 Assignm...

Page 1300: ...pull down resistor during normal A D conversion operations Connecting an internal pull down resistor may lead to a drop in the input voltage so that obtaining correct results of A D conversion becomes impossible Diagnosis procedure reference To diagnose open circuit input pins 1 Set discharge ON buffer amplifier OFF and channel S H OFF 2 In the ADCA0PDCTL0 register only specify a single channel as...

Page 1301: ...ea on chip RAM by interrupt processing or DMA These data are used in determining the result of the diagnosis 7 On completion of A D conversion the specified number of times check the results of A D conversion for values that decline to almost 0 V and are less than 0 2 V If such values are found the analog input pin for the target channel is judged to have been disconnected 8 When multiple channels...

Page 1302: ...H selecting channel 7 Set the ADCAnDGCTL0 ADCAnPSEL 2 0 bits to 001B selecting 2 3 AVDD 1 3 AVDD and 1 2 AVDD as reference voltages DIAGOUT0 DIAGOUT1 and DIAGOUT2 respectively Set the ADCAnDGCTL1 register to 0000 000EH selecting channels 1 2 and 3 as the channels to which the internal reference voltage is applied Set the ADCAnSHCTL register to 0000 0000H disabling channel S H function Set the ADCA...

Page 1303: ...unction Set the ADCAnCTL0 ADCAnCE bit to 1 enabling the A D converter Flow of operations The software trigger starts A D conversion on CG1 channel 7 Input the conversion trigger for CG0 the software trigger during conversion on CG1 then set the ADCAnDGCTL0 ADCAnPSEL 2 0 bits to 010B selecting 1 2 AVDD 2 3 AVDD and 1 3 AVDD as reference voltages DIAGOUT0 DIAGOUT1 and DIAGOUT2 respectively Make the ...

Page 1304: ... S H circuit diagnostic is changed set ADCAnDGCTL0 ADCAnPSEL 2 0 bits to diagnosis voltage Idle Conversion of CG1 Conversion of CG0 Status CH7 CH1 CH2 CH3 Conversion Sample Conversion Sample Conversion Sample Conversion Sample DIAGOUT1 1 3AVDD DIAGOUT2 1 2AVDD DIAGOUT0 2 3AVDD CG1 Start trigger CG0 Start trigger The setting of the reference voltage is changed Hold Hold Hold 1 3AVDD 2 3AVDD 1 2AVDD...

Page 1305: ...tion is enabled using the ADCAnSHCTL ADCAnCSELx bit is held in the channel sample and hold circuit Then the scan list conversion is started according to the setting of the ADCAnCTL1 ADCAnTRMi bit Caution The sampling of channel sample and hold circuit is started by setting ADCAnCE bit to 1 Input the start trigger after waiting for the channel sample and hold sampling time tCAS after setting ADCAnC...

Page 1306: ...DCAnT1 INTADCAnT0 Convert Convert Conversion of CG0 Hold simultaneously CH1 channel S H CH2 channel S H CG0 CH11 CH12 CH13 channel S H function disabled CG1 CH1 CH2 channel S H function enabled CH2 CH12 CH1 CH3 CH3 channel S H CH4 channel S H CH1 channel S H CH2 channel S H CH4 CH2 CH11 CH12 Status Idle Conversion of CG0 Conversion of CG1 Hold Convert Sample Hold Convert Sample Hold Convert Sample...

Page 1307: ...vert Sample CH1 CH1 CH10 CH10 CH2 CH2 Start trigger CG0 Start trigger CG0 INTADCAnT0 INTADCAnT0 INTADCAnT0 INTADCAnT0 INTADCAnT0 CG0 CH1 CH2 channel S H function enabled and CH10 channel S H function disabled CH1 channel S H CH2 channel S H Status Idle Idle Conversion of CG0 Conversion of CG0 Hold Convert Convert Sample Hold Convert Sample Hold Convert Sample Convert Sample Convert Sample CH10 CH1...

Page 1308: ...ert Sample Hold Convert Sample CH1 CH2 Convert Hold Convert Sample CH1 CH2 Hold Sample Hold CG0 CH1 CH2 channel S H function enabled and CH10 channel S H function disabled CH1 channel S H CH2 channel S H Status Idle Conversion of CG0 Conversion of CG0 Conversion of CG2 CH1 CH2 CH3 CH3 CH3 CH2 CH1 CH2 CH1 Hold Hold Hold Sample Sample Sample Sample Sample Sample Sample Convert Convert Convert Conver...

Page 1309: ...CH1 selected CG1 CH1 and CH2 selected and CG2 CH3 selected CG0 CH1 CH2 and CH3 selected CG1 CH1 selected and CG2 CH2 and CH3 selected The following combination is prohibited CG0 CH1 CH2 and CH3 selected CG1 CH1 and CH2 selected and CG2 CH2 and CH3 selected 2 When changing the scan list of CGi to which the channel sample and hold function is applied during A D conversion set the scan list so that t...

Page 1310: ...d be set to 00B 23 3 13 Discharge Function If required the internal capacitor in the common sample and hold circuit can be discharged prior to every A D conversion Note When the discharge function is enabled the total conversion time is increased refer to Section 23 3 7 Resolution Sampling Time and Conversion Time Setting The discharge function is enabled by setting ADCAnCTL1 DCAnDISC to 1 Figure ...

Page 1311: ...plifier Function is Enabled Caution In the channel with the channel S H function enabled the conversion is performed with the buffer amplifier function automatically being disabled 23 3 15 Stabilization Control The A D converter needs time to stabilize operation at power on of the A D converter ADCAnCTL1 ADCAnGPS 1 Although a start trigger is acceptable even during the stabilization time A D conve...

Page 1312: ...bilization counter ADCAnCNT ADCAn_base0 114H A D converter sampling count register ADCAnSMCNT ADCAn_base0 12CH A D converter channel S H wait count register ADCAnSHHWCNT ADCAn_base0 130H A D converter buffer amplifier count register ADCAnAMPCNT ADCAn_base0 134H A D converter discharge count register ADCAnDISCNT ADCAn_base0 138H Conversion status registers A D converter overwrite error flag registe...

Page 1313: ...ck error flag ADCAnSTR0 ADCAn_base1 24H ADCAnSTR0 flag clear register ADCAnSTC0 ADCAn_base1 30H Diagnosis function control registers A D converter self diagnosis function control register 0 ADCAnDGCTL0 ADCAn_base1 DCH A D converter self diagnosis function control register 1 ADCAnDGCTL1 ADCAn_base0 11CH A D converter internal pull down resistance control register 0 ADCAnPDCTL0 ADCAn_base0 120H Chan...

Page 1314: ...DCAn OEM4 Specifies whether the error interrupt INTADCAnTERR is generated when an A D conversion result in ADCAnLCR is overwritten before it is read 0 Generates the error interrupt INTADCAnTERR when an A D conversion result is overwritten 1 Does not generate the error interrupt INTADCAnTERR For details refer to Section 23 3 10 1 Overwrite Check for A D Conversion Results 11 to 9 ADCAn OEM 3 1 Spec...

Page 1315: ...cted 2 Wait for one cycle 3 ADCAnCTL0 ADCAnCE 0 AD conversion stopped When the enable disable is switched the value retained to conversion result registers ADCAnDGCR ADCAnLCR ADCAnCmCR and ADCAnDBiCR are initialized 6 ADCAnSTM This bit specifies the mode of repetition for one shot conversion 0 Channel repetition mode is not used 1 Channel repetition mode is used Conversion is repeated on each chan...

Page 1316: ...unction 31 to 26 ADCAn TiETS 1 0 Specifies the valid edge of the hardware trigger signal ADCAnTTRGi ADCAn TiETS1 ADCAn TiETS0 Valid Edge 0 0 No edge detection trigger is not accepted 0 1 Rising edge 1 0 Falling edge 1 1 Rising and falling edges 24 ADCAn CRAC Specifies the alignment of the results of A D conversion and diagnosis conversion 0 Right aligned 1 Left aligned 21 ADCAn MD1 Specifies the A...

Page 1317: ...nversion of a higher priority CG is triggered The settings in ADCAnTRM1 and ADCAnTRM0 apply to CG1 and CG0 respectively The setting of CG2 is always 0 0 Halts the current A D conversion of CGi immediately and starts the A D conversion of the higher priority CG immediately halts the A D conversion due to a higher priority trigger holds the current conversion status so that the conversion can be res...

Page 1318: ...ly performing A D conversion the value is transferred upon completion of the scan list conversion of the current CGi Address ADCAn_base1 i 4H Initial value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ADCAn DIAG 0 0 0 0 0 0 0 ADCAnCGiS 23 16 R W R R R R R R R R W R W R W R W R W R W R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADCAnCGiS 15 0...

Page 1319: ...6 25 24 23 22 21 20 19 18 17 16 ADCAn CG0 IDG 0 0 0 0 0 0 0 ADCAnCGiI 23 16 R W R R R R R R R R W R W R W R W R W R W R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADCAnCGiI 15 00 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Table 23 10 ADCAnIOCi Register Contents Bit Position Bit Name Function 31 ADCAn CG0IDG Specifies whether the interrupt INTADCAnTi is generated on completion...

Page 1320: ... A D converter is disabled ADCAnCTL0 ADCAnCE 0 Address ADCAn_base0 114H Initial value 00H This register is initialized by any reset Note The value of stabilization counter should be set so that the stabilization time is 10 ms or more 7 6 5 4 3 2 1 0 ADCAnCNT 7 0 R W R W R W R W R W R W R W R W Table 23 11 ADCAnCNT Register Contents Bit Position Bit Name Function 7 to 0 ADCAnCNT 7 0 Specifies the s...

Page 1321: ...itial value 0000H This register is initialized by any reset Note For units to which the hardware trigger signals are connected refer to Table 23 2 Units to which Hardware Trigger Signals are Connected 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADCAnTiSEL 15 00 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Table 23 12 ADCAnTSELi Register Contents Bit Position Bit Name Function 15 to 0 ...

Page 1322: ...f it is disabled setting this register is ignored Access This register can be read written in 8 bit units It can only be written when the A D converter is disabled ADCAnCTL0 ADCAnCE 0 Address ADCAn_base0 130H Initial value 0AH This register is initialized by any reset 7 6 5 4 3 2 1 0 ADCAnADNSMP 7 0 R W R W R W R W R W R W R W R W Table 23 13 ADCAnSMCNT Register Contents Bit Position Bit Name Func...

Page 1323: ...nction is enabled If it is disabled setting this register is ignored Access This register can be read written in 8 bit units It can only be written when the A D converter is disabled ADCAnCTL0 ADCAnCE 0 Address ADCAn_base0 138H Initial value 0FH This register is initialized by any reset 7 6 5 4 3 2 1 0 0 0 0 0 ADCAnAMPCNT 3 0 R R R R R W R W R W R W Table 23 15 ADCAnAMPCNT Register Contents Bit Po...

Page 1324: ...version result register for channel m ADCAnCmCR ADCAnCmER1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 ADCAnOWE 23 16 R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADCAnOWE 15 00 R R R R R R R R R R R R R R R R Table 23 17 ADCAnSTR1 Register Contents Bit Position Bit Name Function 23 to 0 ADCAn OWE 23 00 Indicates whether the A D conversion result of cha...

Page 1325: ...W W W W W W W W W W W W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADCAnOWEC 15 00 W W W W W W W W W W W W W W W W Table 23 18 ADCAnSTC1 Register Contents Bit Position Bit Name Function 23 to 0 ADCAnOWEC 23 00 Clears the A D converter overwrite error flag ADCAnSTR1 ADCAnOWEm bit 0 No effect writing 0 to a bit does not affect the corresponding A D converter overwrite error flag i e the ADCAnSTR1 ADCAnOW...

Page 1326: ...CAnST 2 0 R R R R R R R R R R R R R R R R Table 23 19 ADCAnSTR2 Register Contents Bit Position Bit Name Function 10 to 8 ADCAnRQ 2 0 Indicates whether the A D conversion request for CGi is pending 0 A D conversion request for CGi is not pending 1 A D conversion request for CGi is pending 2 to 0 ADCAnST 2 0 Indicates whether A D conversion of CGi is currently performed 0 A D conversion is not curre...

Page 1327: ...0 W W W W W W W W Table 23 20 ADCAnSTC2 Register Contents Bit Position Bit Name Function 7 ADCAn LERC1 Clears the overwrite flag ADCAnLCR ADCAnLER1 bit 0 No effect writing 0 to this bit does not affect the flag 1 Clears ADCAnLCR ADCAnLER1 6 ADCAn LERC0 Clears the result check error flag ADCAnLCR ADCAnLER0 bit 0 No effect writing 0 to this bit does not affect the flag 1 Clears ADCAnLCR ADCAnLER0 5 ...

Page 1328: ...ritten in 8 bit units It is always read as 00H Address ADCAn_base1 A4H i 4H Initial value 00H This register is initialized by any reset For details refer to Section 23 3 5 Starting A D Conversion Start Triggers 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 ADCAn STTi W W W W W W W W Table 23 21 ADCAnTRGi Register Contents Bit Position Bit Name Function 0 ADCAnSTTi Starts the A D conversion of CGi 0 No effect writ...

Page 1329: ...e 23 22 ADCAnLCR Register Contents 1 2 Bit Position Bit Name Function 25 24 ADCAn LCG 1 0 Indicates the CG to which the conversion result in ADCAnLCR 15 00 belongs ADCAn LCG1 ADCAn LCG0 Channel Group 0 0 CG0 0 1 CG1 1 0 CG2 1 1 None 23 ADCAn LER1 Indicates the overwrite error status 0 The conversion result has not been overwritten 1 The conversion result has been overwritten This error flag is cle...

Page 1330: ...ult in ADCAnLCR 15 00 belongs 00001 m CHm 15 to 0 ADCAn LCR 15 00 Indicates the result of the A D conversion The resolution and alignment depend on ADCAnCTL1 ADCAnCTYP and ADCAnCTL1 ADCAnCRAC as follows ADCAn CTL1 ADCAn CTYP ADCAn CTL1 ADCAn CRAC Resolution and Alignment Bit Position of Conversion Result Value 0 0 12 bit resolution right aligned ADCAnLCR 11 00 0 1 12 bit resolution left aligned AD...

Page 1331: ...s of the individual bits are identical to those of the corresponding bits in ADCAnLCR except that this register indicates the latest A D conversion result of a specified channel rather than the latest results of all the channels refer to Table 23 22 ADCAnLCR Register Contents Note 2 After reset ADCAnCmCG 1 0 are set to 11B Note 3 When ADCAnCTL1 ADCAnRCL 0 the A D conversion result in ADCAnCmCR 15 ...

Page 1332: ...n result is within the specified range 1 The conversion result is out of the specified range This error flag reflects the value of ADCAnSTR0 ADCAnRCEm and is cleared when ADCAnSTC0 ADCAnRCECm is set to 1 21 ADCAn CmUR Indicates the update status of the A D conversion result 0 The A D conversion result has been read from ADCAnCmCR the result has not been updated 1 The A D conversion result has not ...

Page 1333: ...2 21 20 19 18 17 16 0 0 0 0 0 0 ADCAn DBiCG 1 0 ADCAn DBiER1 ADCAn DBiER0 ADCAn DBiUR ADCAnDBiCN 4 0 R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADCAnDBiCR 15 00 R R R R R R R R R R R R R R R R Table 23 24 ADCAnDBiCR Register Contents 1 2 Bit Position Bit Name Function 25 24 ADCAn DBiCG 1 0 Indicates the CG to which the conversion result in ADCAnDBiCR 15 00 belongs ADCAn ...

Page 1334: ... been updated 1 The A D conversion result has not been read from ADCAnDBiCR the result has been updated This bit is cleared after the conversion result is read 20 to 16 ADCAn DBiCN 4 0 Indicates the number of the channel to which the conversion result in ADCAnDBiCR 15 00 belongs 00001 m CHm 15 to 0 ADCAn DBiCR 15 00 Indicates the result of the A D conversion The resolution and alignment depend on ...

Page 1335: ...ad when ADCAnCTL1 ADCAnRCL 1 Note 2 The result of the diagnostic A D conversion of an internal reference voltage is stored in ADCAnDGCR not in ADCAnLCR ADCAnCmCR refer to Section 23 4 5 5 ADCAnDGCR A D Converter Diagnosis Conversion Result Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADCAnDBiCRL 15 00 R R R R R R R R R R R R R R R R Table 23 25 ADCAnDBiCRL Register Contents Bit Position Bit Name...

Page 1336: ...st channel of CG0 is completed Access This register can be read in 16 bit units Address ADCAn_base1 9CH Initial value 0000H This register is initialized by any reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADCAnDGCR 15 00 R R R R R R R R R R R R R R R R Table 23 26 ADCAnDGCR Register Contents Bit Position Bit Name Function 15 to 0 ADCAn DGCR 15 00 Indicates the result of the diagnostic A D conversio...

Page 1337: ...d for the A D conversions of every CG 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 ADCAnRCK 23 16 R R R R R R R R R W R W R W R W R W R W R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADCAnRCK 15 00 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Table 23 27 ADCAnCTL2 Register Contents Bit Position Bit Name Function 23 to 00 ADCAn RCK 23 00 Enables or disables th...

Page 1338: ...Check Functions Access This register can be read written in 16 bit units It can only be written when the A D converter is disabled ADCAnCTL0 ADCAnCE 0 Address ADCAn_base1 20H Initial value 0000H This register is initialized by any reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADCAnUL 11 00 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R R R R Table 23 28 ADCAnUL Register Contents Bit Posit...

Page 1339: ...The error flag in the A D converter conversion result register for channel m ADCAnCmCR ADCAnCmER0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 ADCAnRCE 23 16 R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADCAnRCE 15 00 R R R R R R R R R R R R R R R R Table 23 30 ADCAnSTR0 Register Contents Bit Position Bit Name Function 23 to 0 ADCAn RCE 23 00 Indicates w...

Page 1340: ...7 16 0 0 0 0 0 0 0 0 ADCAnRCEC 23 16 W W W W W W W W W W W W W W W W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADCAnRCEC 15 00 W W W W W W W W W W W W W W W W Table 23 31 ADCAnSTC0 Register Contents Bit Position Bit Name Function 23 to 0 ADCAnRCEC 23 00 Clears the A D converter result upper lower limit comparison error flag ADCAnSTR0 ADCAnRCEm bit 0 No function 1 Clears ADCAnSTR0 ADCAnRCEm Note The bi...

Page 1341: ...15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCAnPSEL 2 0 R R R R R R R R R R R R R R W R W R W Table 23 32 ADCAnDGCTL0 Register Contents Bit Position Bit Name Function 2 to 0 ADCAn PSEL 2 0 Specifies the reference voltages ADCAn PSEL2 ADCAn PSEL1 ADCAn PSEL0 ADDIAGOUT Signal DIAGOUT2 Signal DIAGOUT1 Signal DIAGOUT0 Signal 0 0 0 AVSS 2 3 AVDD 1 2 AVDD 1 3 AVDD 0 0 1 1 3 AVDD 1 ...

Page 1342: ...16 0 0 0 0 0 0 0 0 ADCAnCDG 23 16 R R R R R R R R R W R W R W R W R W R W R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADCAnCDG 15 00 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Table 23 33 ADCAnDGCTL1 Register Contents Bit Position Bit Name Function 23 to 0 ADCAn CDG 23 00 Specifies the input voltage 0 Uses the analog input voltage ADCAnIm 1 Uses the following reference volta...

Page 1343: ...ny reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 ADCAnPDNA 23 16 R R R R R R R R R W R W R W R W R W R W R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADCAnPDNA 15 00 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Table 23 34 ADCAnPDCTL0 Register Contents Bit Position Bit Name Function 23 to 0 ADCAn PDNA 23 00 Specifies whether an internal pull down resisto...

Page 1344: ...CAnCTL0 ADCAnCE 1 Access This register can be read written in 8 bit units Address ADCAn_base0 118H Initial value 00H This register is initialized by any reset 7 6 5 4 3 2 1 0 0 ADCAnCSEL 6 1 0 R R W R W R W R W R W R W R Table 23 35 ADCAnSHCTL Register Contents Bit Position Bit Name Function 6 to 1 ADCAn CSEL 6 1 Enables or disables the channel s sample and hold function 0 The channel s sample and...

Page 1345: ...n the specified voltage range In order to avoid input of the voltage equal to or above AVREFnP or equal to or below AVREFnM the input voltage is recommended to be clamped with a diode with a 0 3 V or less VF If the voltage equal to or above AVREFnP or equal to or below AVREFnM is input the conversion result value of the pertinent channel is undefined and cannot be guaranteed In addition it may aff...

Page 1346: ...analog ground digital ground and an electrolytic capacitor at a point in the source of the power supply but wire them in isolation from each other on the board 3 Analog Reference Voltage Input Pins AVREFnP AVREFnM Insert a bypass capacitor between the leads of the AVREFnP pin and the AVREFnM pin as close as possible to the leads It is recommended to use approximately 0 1 F reference value multilay...

Page 1347: ...o be used for A D conversion since a single A D converter is used the hysteretic characteristics may be presented in which the conversion result is influenced by the value of the channel having been used immediately before and the different conversion results may be obtained even for the same potentials To obtain the more accurate conversion result perform A D conversion two consecutive times usin...

Page 1348: ...R01UH0336EJ0102 Rev 1 02 Page 1348 of 1538 Jul 17 2014 V850E2 PG4 L Section 23 A D Converter degrade the A D conversion accuracy In such a case connect capacitors C1 and C2 to the AVDDn and AVREFnP pins ...

Page 1349: ... R2 kΩ Max Typ Max Typ Max Typ Max Typ Max Pins supporting channel S H Channel S H used 15 0 64 0 77 1 07 1 28 0 17 0 20 6 30 14 30 Channel S H not used Buffer not used 6 39 7 82 10 00 12 00 0 74 1 39 0 05 0 06 Buffer used 1 14 1 38 1 00 1 20 0 74 1 39 0 05 0 06 Pins not supporting channel S H Buffer not used 5 24 6 44 10 00 12 00 0 23 0 27 0 05 0 06 Buffer used 0 52 0 64 1 00 1 20 0 23 0 27 0 05 ...

Page 1350: ...to full scale can be represented in units of FSR full scale range FSR is the range of the convertible analog input voltage represented in percentage It is given by the following equation regardless of the resolution 1 FSR maximum convertible analog input voltage minimum convertible analog input voltage 100 AVREFP AVREFM 100 When the resolution is 10 bits 1 LSB is expressed as follows 1 LSB 1 210 1...

Page 1351: ... measured value and a theoretical value It shows the sum of the zero scale error full scale error linearity error and the error derived from the combination of these errors The quantization error is not included in the overall error in the characteristics table Figure 23 23 Overall Error 1 1 0 0 AVREFP AVREFM Digital output Ideal line Overall error Analog input ...

Page 1352: ...tal value The quantization error is unavoidable because analog input voltages within 1 2 LSB are converted to the same digital code This error is not included in the overall error zero scale error full scale error integral linearity error or differential linearity error in the characteristics table Figure 23 24 Quantization Error 1 1 0 0 AVREFP AVREFM 1 2 LSB 1 2 LSB Digital output Analog input Qu...

Page 1353: ...measured value and a theoretical value 1 2 LSB of the analog input voltage when the digital output changes from 0 000 to 0 001 Figure 23 25 Zero Scale Error 111 000 Ideal line Analog input AVREFP AVREFM Zero scale error AVREFM x 001 100 010 011 AVREFM 2x AVREFM 3x AVREFM x Note x Voltage corresponding to 1 LSB x AVREFP AVREFM x 1 LSB Digital output lower 3 bits ...

Page 1354: ...een a measured value and a theoretical value full scale 3 2 LSB of the analog input voltage when the digital output changes from 1 110 to 1 111 Figure 23 26 Full Scale Error 111 000 AVREFP Full scale error 100 010 011 AVREFM AVREFP x AVREFP 2x AVREFP 3x Note x Voltage corresponding to 1 LSB x AVREFP AVREFM x 1 LSB Digital output lower 3 bits Analog input ...

Page 1355: ...nput voltage width for outputting a certain code is 1 LSB The differential linearity error is the difference between a measured value and a theoretical value of the voltage width for outputting a certain code Figure 23 27 Differential Linearity Error 1 1 0 0 AVREFP AVREFM Digital output Analog input Ideal width of 1LSB Differential nonlinearity ...

Page 1356: ... Integral Linearity Error 8 Conversion Time The conversion time is the time required to obtain the digital output after the analog input voltage is applied The conversion time in the characteristics table includes the sampling time 9 Sampling Time The sampling time is the duration while the analog switch is on to allow the analog voltage to be sampled by the common sample and hold circuit 10 A D C...

Page 1357: ...er is represented by affix n n 0 1 For example OSTMn represents OSTM0 Meaning of m The channel number of the timer TAUB0 is represented by affix m m 00 to 15 Meaning of x Arbitrary value set for registers to be used Meaning of y The registers to be used are identified by affix y y 200 201 202 203 210 211 212 213 30 31 50 51 Register addresses Refer to Section 24 3 Peripheral Interconnection Regist...

Page 1358: ...n A D conversion trigger selection function High accuracy triangle wave PWM output function with dead time Trigger and pulse width measurement function Encoder capture trigger selection function Two phase encoder function control method 1 Two phase encoder function control method 2 Three phase encoder function CAN time stamp function TSG20 TAUB0 dead time reduction function TAUB input selection fu...

Page 1359: ...PIC0SSER0 FFFF DB10H Simultaneous start control register 2 PIC0SSER2 FFFF DB18H Hi Z output control register 0 PIC0HIZCEN0 FF81 C080H Hi Z output control register 2 PIC0HIZCEN2 FF81 C088H A D converter trigger output control register 400 PIC0ADTEN400 FF81 C090H A D converter trigger output control register 401 PIC0ADTEN401 FF81 C094H A D converter trigger output control register 402 PIC0ADTEN402 F...

Page 1360: ... Encoder Control Function Control Method 1 24 4 7 Two Phase Encoder Control Function Control Method 2 24 4 8 Three Phase Encoder Control Function 24 4 9 CAN Time Stamp Function 24 4 10 TSG20 and TAUB0 Dead Time Reduction Function 24 4 11 TAUB Input Selection Table 24 3 Registers for Various Functions 2 2 Section No Function Name Register Name PIC0REGy 200 201 202 203 30 31 50 24 4 1 Simultaneous S...

Page 1361: ...ions 1 Control Register EN PIC0EN Access This register can be read written in 8 bit units Address FFFF DB00H Initial value 00H This register is initialized by any reset 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 PIC0EN0 R R R R R R R R W Table 24 4 PIC0EN Contents Bit Position Bit Name Function 0 PIC0EN0 Enables or disables the PIC functions 0 Disables the PIC functions 1 Enables the PIC functions ...

Page 1362: ...4 Connection Functions 24 4 1 Simultaneous Start Trigger Function 24 4 1 1 Functional Overview Allows any combination of the timers TAUB0 TAUJ0 TSG20 TPBA0 OSTMn and ENCA0 to be started simultaneously 24 4 1 2 Configuration Configuration Timer Function Timer Timer configuration TAUB0 TAUJ0 TSG20 TPBA0 OSTMn ENCA0 ...

Page 1363: ...nnection PIC Figure 24 1 Block Diagram 1 0 0 0 0 0 0 0 PIC0SSER TAUB0TSST TAUB0TSST1 TAUB0TSST14 TAUB0TSST15 TAUJ0TSST0 TAUJ0TSST3 TSG20TSST0 TPBA0SST OST0TSST0 OST1TSST0 ENCA0TSST TAUB0 TAUJ0 TSG20 TPBA0 OSTM0 OSTM1 ENCA0 PIC0SSER2 PIC0SST 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 0 1 0 0 1 0 0 0 1 0 1 0 ...

Page 1364: ...nitialized by any reset 15 14 13 12 11 10 9 8 PIC0SS ER015 PIC0SS ER014 PIC0SS ER013 PIC0SS ER012 PIC0SS ER011 PIC0SS ER010 PIC0SS ER009 PIC0SS ER008 R W R W R W R W R W R W R W R W 7 6 5 4 3 2 1 0 PIC0SS ER007 PIC0SS ER006 PIC0SS ER005 PIC0SS ER004 PIC0SS ER003 PIC0SS ER002 PIC0SS ER001 PIC0SS ER000 R W R W R W R W R W R W R W R W Table 24 5 PIC0SSER0 Contents Bit Position Bit Name Function m PIC...

Page 1365: ...s the simultaneous start trigger for OSTM0 0 Disables the simultaneous start trigger for OSTM0 1 Enables the simultaneous start trigger for OSTM0 10 PIC0SSER210 Enables the simultaneous start trigger for TPBA0 0 Disables the simultaneous start trigger for TPBA0 1 Enables the simultaneous start trigger for TPBA0 8 PIC0SSER208 Enables the simultaneous start trigger for TSG20 0 Disables the simultane...

Page 1366: ...or 1 bit units Address FFFF DB04H Initial value 00H This register is initialized by any reset SYNCTRG is always read as 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 SYNCTRG W W W W W W W W Table 24 7 PIC0SST Contents Bit Position Bit Name Function 0 SYNCTRG Generates a start trigger for the timers for which simultaneous start is enabled 0 Invalid 1 Generates a simultaneous start trigger Outputs a pulse of 1 PC...

Page 1367: ...r each of the timers TAUB0 TAUJ0 TSG20 TPBA0 OSTMn and ENCA0 register setting is included For details on initial setting of TAUB0 TAUJ0 TSG20 TPBA0 OSTMn and ENCA0 see the section of each timer 2 Enabling Simultaneous Start Enable simultaneous start of the target timers by setting the corresponding bits in PIC0SSER0 and PIC0SSER2 to 1 3 Start Trigger Output Set the SYNCTRG bit in PIC0SST0 to 1 to ...

Page 1368: ...ction refer to the section of each timer 24 4 1 6 Register Setting for Various Functions Refer to Section 24 4 1 3 Registers START Initial setting Set register and operating mode for each timer Timers TAUB0m TAUJ0 TSG20 TPBA0 OSTMn ENC0 Start Enable simultaneous start set PIC0SSER0 PIC0SSER2 Set start trigger write 1 to the SYNCTRG bit Timers are simultaneously started Simultaneous start for other...

Page 1369: ...e input as the ADC hardware trigger signal for the pertinent channel group Similarly the internal trigger signals selected by ADCA0TSEL1 and ADCA0TSEL2 from TAUB0 ENCA0 TSG20 and TAPA0 are ORed with the external trigger signal from the pin to generate the ADC hardware trigger signal for the pertinent channel groups The PIC provides the function to allow TAUB0INTm internal trigger signal from each ...

Page 1370: ...rconnection PIC 24 4 2 2 Configuration Figure 24 3 Block Diagram i 0 j 0 to 2 1 0 OR bit 0 bit 2 bit 4 bit 5 bit 8 OR ADCATTRGj TAUB0 PIC0ADTEN40j ADCA0TSELi TAUB0INT0 TAUB0INT1 TAUB0INT15 ENCAT0INT1 TS0ADTRG0 TS0ADTRG1 ADCA0TRGi pin ENCA0 TSG20 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 1 0 ...

Page 1371: ...ection PIC Figure 24 4 Block Diagram i 1 or 2 j 0 to 2 1 0 OR bit 0 bit 2 bit 4 bit 5 OR ADCATTRGj TAUB0 PIC0ADTEN40j ADCA0TSELi TAUB0INT0 TAUB0INT1 TAUB0INT15 ENCAT0INT1 TS0ADTRG0 TS0ADTRG1 ENCA0 TSG20 1 0 1 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 1 0 0 1 0 bit 8 bit 9 TAPA0TADOUTi 1 ADCA0TRGi pin TAPA0 ...

Page 1372: ...zed by any reset 15 14 13 12 11 10 9 8 PIC0 ADTEN 40j15 PIC0 ADTEN 40j14 PIC0 ADTEN 40j13 PIC0 ADTEN 40j12 PIC0 ADTEN 40j11 PIC0 ADTEN 40j10 PIC0 ADTEN 40j09 PIC0 ADTEN 40j08 R W R W R W R W R W R W R W R W 7 6 5 4 3 2 1 0 PIC0 ADTEN 40j07 PIC0 ADTEN 40j06 PIC0 ADTEN 40j05 PIC0 ADTEN 40j04 PIC0 ADTEN 40j03 PIC0 ADTEN 40j02 PIC0 ADTEN 40j01 PIC0 ADTEN 40j00 R W R W R W R W R W R W R W R W Table 24 ...

Page 1373: ...s the ADTRG0i pin as a trigger source of ADC channel group i 0 Does not select the ADTRG0i pin as a trigger source 1 Selects the ADTRG0i pin as a trigger source 5 ADCA0TiSEL05 Selects TS0ADTRG1 as a trigger source of ADC channel group i 0 Does not select TS0ADTRG1 as a trigger source 1 Selects TS0ADTRG1 as a trigger source 4 ADCA0TiSEL04 Selects TS0ADTRG0 as a trigger source of ADC channel group i...

Page 1374: ...ADCA0TiSEL05 Selects TS0ADTRG1 as a trigger source of ADC channel group i 0 Does not select TS0ADTRG1 as a trigger source 1 Selects TS0ADTRG1 as a trigger source 4 ADCA0TiSEL04 Selects TS0ADTRG0 as a trigger source of ADC channel group i 0 Does not select TS0ADTRG0 as a trigger source 1 Selects TS0ADTRG0 as a trigger source 2 ADCA0TiSEL02 Selects ENCAT0INT1 as a trigger source of ADC channel group...

Page 1375: ...gister 40j PIC0ADTEN40j j 0 to 2 to 1 to allow the interrupt trigger signal from each channel of TAUB0 to be selected as a trigger of ADC channel group i NoteSet the registers while the AD converter is stopped ADCA0CE 0 3 Setting A D Converter Trigger Selection Control Register i ADCA0TSELi By setting the bit corresponding to each trigger to 1 the trigger signals are ORed and the result can be use...

Page 1376: ...n Flow Figure 24 5 Operation Flow i 0 to 2 j 0 to 2 24 4 2 6 Register Setting Examples for Various Functions Refer to Section 24 4 1 3 Registers START Initial setting Set the register and operating mode of each timer Timers TAUB0 ENCA0 TSG20 TAPA0 Start Set the PIC0ADTEN40j registers Set the ADCA0TSELi registers Timer start END ...

Page 1377: ...NTm Setting functions of TAUB0 channels Note M master channel S slave channel Configuration Timer Function TAUB TAPA Timer configuration TAUB0 TAPA0 CH Function Name M S CDR Set Value Description 02 PWM output function CH02 is master for CH04 to CH09 M Period 04 S Duty U phase setting 05 S Dead time U phase 06 S Duty V phase setting 07 S Dead time V phase 08 S Duty W phase setting 09 S Dead time W...

Page 1378: ...20306 PIC0REG20305 PIC0REG20304 FN01 1 0 0 1 PIC0REG20310 PIC0REG20309 PIC0REG20308 VO1 VO2 FN02 1 0 0 1 PIC0REG20314 PIC0REG20313 PIC0REG20312 FN03 1 0 0 1 PIC0REG20317 PIC0REG20316 PIC0REG20315 WO1 WO2 FN04 1 0 0 1 PIC0REG20322 PIC0REG20321 PIC0REG20320 FN05 TIN10 TOUT10 TOUT11 TIN12 TOUT12 TOUT13 TIN14 TOUT14 TOUT15 0 1 0 0 PIC0REG20220 PIC0REG20221 0 1 0 0 PIC0REG20224 PIC0REG20225 A B A B A B...

Page 1379: ... to 0 by other timer connection functions In that case apply the bit definition of the corresponding PIC connection function 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 R R R R R R R R 23 22 21 20 19 18 17 16 0 0 0 0 0 PIC0RE G20018 0 0 R R R R R R W R R 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 R R R R R R R R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R R R R R R R R Table 24 11 PIC0REG200 Contents Bit Position Bi...

Page 1380: ...R R R R R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R R R R R R R R Table 24 12 PIC0REG201 Contents 1 2 Bit Position Bit Name Function 27 26 PIC0REG20127 PIC0REG20126 Selects the A input signal of FN05 according to the setting of the TOL bit of TAUB0CH09 PIC0REG20127 PIC0REG20126 Input Signal 1 0 Output from the combinational circuit When TOL of TAUB0CH09 is 0 1 1 Inverted output from the combinational circ...

Page 1381: ...nput Signal 1 0 Output from the combinational circuit When TOL of TAUB0CH06 is 0 1 1 Inverted output from the combinational circuit When TOL of TAUB0CH06 is 1 Other than the above Setting is prohibited 19 18 PIC0REG20119 PIC0REG20118 Selects the A input signal of FN01 according to the setting of the TOL bit for TAUB0CH05 PIC0REG20119 PIC0REG20118 Input Signal 1 0 Output from the combinational circ...

Page 1382: ...R W R W R R R W R W 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 R R R R R R R R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R R R R R R R R Table 24 13 PIC0REG202 Contents Bit Position Bit Name Function 25 24 PIC0REG20225 PIC0REG20224 Selects the TIN input signal of TAUB0CH14 PIC0REG20225 PIC0REG20224 Input Signal 1 0 Signal selected with PIC0REG20018 bit TOUT of TAUB0CH02 Other than the above Setting is prohibited...

Page 1383: ... 4 3 2 1 0 0 PIC0RE G20306 PIC0RE G20305 PIC0RE G20304 0 PIC0RE G20302 PIC0RE G20301 PIC0RE G20300 R R W R W R W R R W R W R W Table 24 14 PIC0REG203 Contents 1 2 Bit Position Bit Name Function 22 21 20 PIC0REG20322 PIC0REG20321 PIC0REG20320 Selects a logical operation to be performed on input signals A and B according to the setting of the TOL bit of TAUB0CH09 PIC0REG 20322 PIC0REG 20321 PIC0REG ...

Page 1384: ...he TOL bit of TAUB0CH06 PIC0REG 20310 PIC0REG 20309 PIC0REG 20308 Input Signal 1 0 0 A and B When TOL of TAUB0CH06 is 0 1 0 1 A or B When TOL of TAUB0CH06 is 1 Other than the above Setting is prohibited 6 5 4 PIC0REG20306 PIC0REG20305 PIC0REG20304 Selects a logical operation to be performed on input signals A and B according to the setting of the TOL bit of TAUB0CH05 PIC0REG 20306 PIC0REG 20305 PI...

Page 1385: ... 0 by other timer connection functions In that case apply the bit definition of the corresponding timer connection function 7 6 5 4 3 2 1 0 0 PIC0HIZ CEN06 PIC0HIZ CEN05 0 0 0 0 PIC0HIZ CEN00 R R W R W R R R R R W Table 24 15 PIC0HIZCEN0 Contents Bit Position Bit Name Function 6 PIC0HIZCEN06 Enables or disables Hi Z output control with the INTADCA0TERR interrupt signal 0 Disable 1 Enable 5 PIC0HIZ...

Page 1386: ... channel assigned only the operation of the U phase is explained below 1 Triangle Wave PWM Output Function with Dead Time CH02 CH04 and CH05 are combined to allow the triangle wave PWM with the dead time to be output from TOUT04 and TOUT05 2 One Shot Pulse Output Function CH10 and CH11 are combined to allow the pulse of the width set in CDR11 to be output as TOUT11 with a delay amount set in CDR10...

Page 1387: ...ead time of TAUB and that are modeled on the dead time pulses that are generated in the range where duty cycle is close to 100 or 0 in PWM output in HT PWM mode of TSG2 Note Setting of PIC0REG201k k 16 to 19 depends on the active level of the U or UB phase output of the triangle wave PWM generated by the triangle wave PWM output function with the dead time Table 24 16 Inputs and Outputs of Combina...

Page 1388: ...iangle Wave PWM Output Function with Dead Time of TAUB On the other hand when the duty cycle of U phase is changed to 0 in PWM output by the triangle wave PWM output function with the dead time of TAUB the UB phase pulses which can be output by TSG2 cannot be output This function uses the timer to generate the pulses to be used in the variable dead time range and uses the combinational circuit to ...

Page 1389: ...e dead time of the TAUB function The values to be set for V VB W and WB phases are the same as those for U phase although the channels and the register bits are different as shown in Figure 24 6 Block Diagram The PIC provides the connection for inserting the pulses generated by the one shot pulse output function into the PWM signal generated by the triangle wave PWM output function with the dead t...

Page 1390: ... e c f g h h i i h i Count enable CNT02 0000H 0001H 0000H 0000H 0000H CDR02 Period INT02 TOUT02 CNT04 CDR04 RDT04 INT04 CNT05 CDR05 Dead time U phase INT05 TOUT04 TOUT05 CNT10 CDR10 INT10 CNT11 CDR11 Variable dead time range pulse RDT11 TOUT11 FN00A FN01A TAUB0O10 U phase Waveform generated by AND between TAUB04 and FN00 A TAUB0O11 UB phase Waveform generated by AND between TAUB05 and FN01 A 1 2 3...

Page 1391: ...or U phase output is set in step 3 In this example the value of CDR11 is fixed to 0000H until the entry into the variable dead time range to minimize the influence on the output PWM 6 The variable dead time range pulse of the width set in CDR11 is output at the edge of TOUT02 after the elapse of the delay time set in CDR10 7 The pulse that is output in step 6 is converted to the variable dead time...

Page 1392: ...INT04 CNT05 CDR05 Dead time U phase INT05 TOUT04 TOUT05 CNT10 CDR10 INT10 CNT11 CDR11 Variable dead time range pulse RDT11 TOUT11 FN00A FN01A TAUB0O10 U phase waveform generated by AND between TAUB04 and FN00 A TAUB0O11 UB phase waveform generated by AND between TAUB05 and FN01 A Timers started simultaneously Simultaneously rewritten Carrier period a b c 0000H 0000H f g h i i 0000H h i 0000H a b c...

Page 1393: ... this example the value of CDR11 is fixed to 0000H until the entry into the variable dead time range to minimize the influence on the output PWM 5 The variable dead time range pulse of the width set in CDR11 is output at the edge of TOUT02 after the elapse of the delay time set in CDR10 6 The pulse that is output in step 5 is converted to the variable dead time range pulse for U phase FN00A or UB ...

Page 1394: ...e Giving Influence on Triangle Wave PWM Output with Dead Time 00 0 0 H h h h h c h h h h c CNT04 CDR04 CNT05 TOUT04 TOUT05 CNT11 CDR11 Variable dead time range pulse TOUT11 FN00A FN01A TAUB0O10 U phase waveform generated by AND between TAUB04 and FN00 A TAUB0O11 UB phase waveform generated by AND between TAUB05 and FN01 A 1 2 2 c 0001H 0000H 0000H 0000H 0000H 0000H ...

Page 1395: ...4 INT04 CNT05 CDR05 Dead time U phase INT05 TOUT04 TOUT05 CNT10 CDR10 INT10 CNT11 CDR11 Variable dead time range pulse RDT11 TOUT11 FN00A FN01A TAUB0O10 U phase waveform generated by OR between TAUB04 and FN00 A TAUB0O11 UB phase waveform generated by OR between TAUB05 and FN01 A Timers started simultaneously Simultaneously rewritten Carrier period a b c d e d e g f h h i i 0000H h i 0000H a b c d...

Page 1396: ...ave PWM U Phase Duty Cycle 0 UB Phase Duty Cycle 100 Output Example with Dead Time When TOL4 0 Active High and TOL5 0 Active High Note that however the PWM outputs from Accordingly TOUT04 and TOUT05 are active low 2 Accordingly the combinational circuit setting PIC0REG20116 PIC0REG20117 and PIC0REG20118 PIC0REG20119 should be made so that the active low output is selected the same level as the PWM...

Page 1397: ...RDT04 INT04 CNT05 CDR05 Dead time U phase INT05 TOUT04 TOUT05 CNT10 CDR10 INT10 CNT11 CDR11 Variable dead time range pulse RDT11 TOUT11 FN00A FN01A TAUB0O10 U phase waveform generated by OR between TAUB04 and FN00 A TAUB0O11 UB phase waveform generated by OR between TAUB05 and FN01 A Timers started simultaneously Simultaneously rewritten Carrier period a b c 0000H 0000H g f h h i i h i a b c 0000H...

Page 1398: ...l circuit setting PIC0REG20116 PIC0REG20117 and PIC0REG20118 PIC0REG20119 should be made so that the active low output is selected the same level as the PWM outputs With this setting variable dead time range pulses for active low are output as FN00A for U phase and FN01A for UB phase 3 Similarly the logical operation circuit setting PIC0REG20302 to PIC0REG20300 and PIC0REG20306 to PIC0REG20304 sho...

Page 1399: ...08 setting TAUB0CDRm register xxxxH Dead time width TAUB0CMORm register xx00 0110 0000 1001b TAUB0CMURm register 0000 0000b Slave CH 3 Dead time CH05 CH07 CH09 setting TAUB0CDRm register xxxxH Delay width TAUB0CMORm register xx00 1001 0000 1000b TAUB0CMURm register 0000 0010b TAUB0TOE register 0000 0000 0000 x0xxb TAUB0TO register 1x1x 1x00 0000 x0xxb 1 TAUB0TOM register 0000 0011 1111 x0xxb TAUB0...

Page 1400: ... that corresponding bit in TAUB0RSF is 0 TAUB0CDRm can be rewritten at any time After rewriting the register set corresponding bit in TAUB0RDT to 1 Register setting for CH for triangle wave PWM output function with dead time Make sure that corresponding bit in TAUB0RSF is 0 TAUB0CDRm can be rewritten at any time After rewriting the register set corresponding bit in TAUB0RDT to 1 Set initial values...

Page 1401: ...CKS operating clock select bits and the MD0 bit can be set arbitrarily the other control bits are fixed to the values specified above For details refer to Section 13 Timer Array Unit B TAUB Set the MD0 bit to 1 to perform this PIC function Table 24 18 TAUB0 Setting Active High Registers related to TAUB0 CH02 Master CH 1 for triangle wave PWM output function with dead time Function Register Bit Pos...

Page 1402: ... 13 Timer Array Unit B TAUB Registers related to TAUB0 CH04 CH06 and CH08 triangle wave PWM output function with dead time Slave CH2 1 m 4 6 and 8 Function Register Bit Position Bit Name Set Value Note TAUB0 TAUB0 CMORm 15 14 CKS1 CKS0 Don t care 2 The operating clock is set 13 12 CCS1 CCS0 0 0 11 MAS 0 10 to 8 STS2 STS1 STS0 1 1 1 7 6 COS1 COS0 0 0 5 0 4 MD4 1 3 MD3 0 2 MD2 0 1 MD1 1 0 MD0 0 TAUB...

Page 1403: ...MD0 bit to 0 for this function Registers related to TAUB0 CH10 CH12 and CH14 One shot pulse output function Master CH 1 m 10 12 and 14 Function Register Bit Position Bit Name Set Value Note TAUB0 TAUB0 CMORm 15 14 CKS1 CKS0 Don t care 2 The operating clock is set 13 12 CCS1 CCS0 0 0 11 MAS 1 10 to 8 STS2 STS1 STS0 0 0 1 7 6 COS1 COS0 0 0 5 0 4 MD4 0 3 MD3 1 2 MD2 0 1 MD1 0 0 MD0 0 A start trigger ...

Page 1404: ...ion is started 1 0 TOE01 TOE00 Don t care TAUB0TO 15 TO15 1 1 High level is output from the TOUT15 pin 14 TO14 Don t care 13 TO13 1 1 High level is output from the TOUT13 pin 12 TO12 Don t care 11 TO11 1 1 High level is output from the TOUT11 pin 10 TO10 Don t care 9 to 4 TO09 to TO04 0 1 Low level is output from the TOUT09 to TOUT04 pins 3 TO03 Don t care 2 TO02 0 Low level is output from the TOU...

Page 1405: ...e low 10 TOL10 Don t care 9 to 4 TOL09 to TOL04 0 1 Positive logic output active high 3 TOL03 Don t care 2 TOL02 0 Positive logic output active high 1 0 TOL01 TOL00 Don t care TAUB0TDE 15 to 10 TDE15 to TDE10 0 Dead time control is disabled 9 to 4 TDE09 to TDE04 1 Dead time control is abled 3 TDE03 Don t care 2 TDE02 0 Dead time control is disabled 1 0 TDE01 TDE00 Don t care TAUB0TDL 15 to 10 TDL1...

Page 1406: ... RDS02 0 Simultaneous rewrite control through another upper CH is disabled 1 0 RDS01 RDS00 Don t care TAUB0RDM 15 to 10 RDM15 to RDM10 0 Simultaneous rewrite control is performed at the start of Master CH 9 to 4 RDM09 to RDM04 1 Simultaneous rewrite control is performed at the start of Master CH that operates at the triangle wave period 3 RDM03 Don t care 2 RDM02 1 Simultaneous rewrite control is ...

Page 1407: ...om the combinational circuit PIC0REG202 25 24 PIC0REG20225 PIC0REG20224 1 0 The input selected with PIC0REG20018 bit is selected 21 20 PIC0REG20221 PIC0REG20220 1 0 The input selected with PIC0REG20018 bit is selected 17 16 PIC0REG20217 PIC0REG20216 1 0 The input selected with PIC0REG20018 bit is selected PIC0REG203 22 to 20 PIC0REG20322 PIC0REG20321 PIC0REG20320 1 0 0 Negative W phase active high...

Page 1408: ...INm TOUTm TAUB0TTOUTm or TAUJ0TTOUTm CDRm TAUB0CDRm or TAUJ0CDRm CNTm TAUB0CNTm or TAUJ0CNTm Setting functions of TAUJ TAUB0 channels Note M master channel S slave channel Configuration Timer Function ENCA TAUB TAUJ Timer configuration ENCA0 TAUB0 TAUJ0 TAU CH Function Name M S Target Trigger for Pulse Width Measurement TAUJ0 00 TINm input pulse interval measurement function S ENCAT0IEC 01 TINm in...

Page 1409: ...1 CH00 TAUJ0 TIN00 CH01 TIN01 CH00 CH02 TAUB0 TIN00 TIN02 ENCA0E0 internal input ENCA0E1 internal input ENCA0EC internal input ENCA0 ENCA0E1 ENCA0EC ENCAT0EQ0 ENCAT0EQ1 ENCAT0IEC DT 1 0 1 0 DT 0 0 0 1 0 1 0 1 0 1 0 0 DT ENCA0E0 PIC0REG3113 PIC0REG3112 PIC0REG3111 PIC0REG3107 PIC0REG3106 PIC0REG3108 PIC0REG3109 PIC0REG3110 PIC0REG3101 PIC0REG3100 ...

Page 1410: ...be read written in 32 bit units Address FF81 C0E8H Initial value 0000 0000H This register is initialized by any reset Note Set 0 to bits 18 and 4 to 2 in the PIC0REG30 register 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 R R R R R R R R 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 R R R R R R W R R 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 R R R R R R R R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R R R R W R W R W R R ...

Page 1411: ... W R W R R R R R W R W Table 24 20 PIC0REG31 Contents 1 2 Bit Position Bit Name Function 13 12 PIC0REG3113 PIC0REG3112 Selects the TIN signal input of TAUB0CH02 PIC0REG3113 PIC0REG3112 Input Signal 0 0 TIN pin input TAUB0CH02 is not used for trigger width measurement 0 1 DT output signal from ENCAT0EQ0 Other than the above Setting is prohibited 11 PIC0REG3111 Selects the TIN signal input of TAUB0C...

Page 1412: ...REG3107 PIC0REG3106 Input Signal 0 0 0 TIN pin input TAUB0CH00 and TAUB0CH01 are not used for trigger width measurement 0 0 1 DT output signal from ENCAT0EQ1 Other than the above Setting is prohibited 1 PIC0REG3101 Selects the TIN signal input of TAUJ0CH01 0 TIN pin input TAUJ0CH01 is not used for trigger width measurement 1 DT output signal from ENCAT0IEC 0 PIC0REG3100 Selects the TIN signal inpu...

Page 1413: ...gister can be read written in 8 bit units It is always read as 0 Address FFFF DB24H Initial value 00H This register is initialized by any reset 7 6 5 4 3 2 1 0 0 0 0 0 0 PIC0INI 0102 PIC0INI 0101 PIC0INI 0100 R R R R R R W R W R W Table 24 21 PIC0INI01 Contents Bit Position Bit Name Function 2 to 0 PIC0INI010 2 0 Initialize the DT circuit 0 Disabled 1 Initialized ...

Page 1414: ...ut Pulse Interval Measurement Function When the valid TINm edge of TAUB0 or TAUJ0 is detected the CNTm value is captured into CDRn and the CNTm is cleared Caution Set the both edges rising and falling edges of TINm to be detected as valid for this function For details of the TAUB0 and TAUJ0 functions see the corresponding sections 2 DT Circuit The DT circuit is used to convert the interrupt trigge...

Page 1415: ...NCA0 is converted to the level sensitive toggle signal by the DT circuit and is output to TINm of TAUB0 and TAUJ0 3 By setting the both edges of TINm of TAUB0 and TAUJ0 as valid the CNTm value is captured into CDRn on the TINm toggle timing and cleared to 0000H This operation is repeated 4 When an overflow occurs the count value FFFFH FFFFFFFFH for TAUJ is captured but the count value is not captu...

Page 1416: ... with the PIC register bits according to the interrupt trigger signal to be measured Table 24 22 Combinations of Interrupt Trigger Signals and Measurement Timers Encoder Timer Interrupt Trigger Signal Measurement Timer Channel PIC Register Bit ENCA0 ENCAT0IEC TAUJ0 CH00 PIC0REG3100 TAUJ0 CH01 PIC0REG3101 ENCAT0EQ0 TAUB0 CH00 PIC0REG3109 PIC0REG3110 TAUB0 CH02 PIC0REG3112 PIC0REG3113 ENCAT0EQ1 TAUB...

Page 1417: ...used Encoder Timer Interrupt Trigger Signal Measurement Timer Channel ENCA0 ENCAT0IEC TAUJ0 CH00 TAUJ0 CH01 ENCAT0EQ0 TAUB0 CH00 TAUB0 CH02 ENCAT0EQ1 TAUB0 CH01 START 1 Initial setting PIC PIC0REG30 register 0000 0000H PIC0REG31 register 0000 1C43H 1 ENCAk TAUJ0 ENCAkCTL register xxxxH compare function used ENCAkIOC0 register xxxxH don t care ENCAkIOC1 register xxxxH don t care ENCAkCCR0 register ...

Page 1418: ...register 0000 0001b ENCA0CCR0 and ENCA0CCR1 can be accessed at any time ENCA0TT register 0000 0001b TAUJ0TT register xxxx xxxx xxxx 1111b 1 TAUB0TT register xxxx xxxx xxxx x111b 1 Setting of registers common to functions TAUB0TOE register xxxx xxxx xxxx x000b TAUB0TO register xxxx xxxx xxxx x000b TAUB0TOM register xxxx xxxx xxxx x000b TAUB0TOC register xxxx xxxx xxxx x000b TAUB0TOL register xxxx x...

Page 1419: ...R0 function 7 ENCA0CTS Don t care Selects trigger of capture operation of ENCA0CCR1 6 5 0 Fixed to 0 4 ENCA0LDE Don t care Enables or disables reload operation when underflow is generated 3 ENCA0ECM1 Don t care Enables or disables clearing of the counter on compare match of ENCA0CCR1 2 ENCA0ECM0 Don t care Enables or disables clearing of the counter on compare match of ENCA0CCR0 1 0 ENCA0UDS1 ENCA...

Page 1420: ...trol bits have fixed values as specified above For details refer to Section 14 Timer Array Unit J TAUJ For TAUJ common registers TOE TO TOM TOC TOL TDE TDM TDL TRE TRO TRC TME RDE RDS RDM and RDC only set the bits corresponding to the used channels to 0 Table 24 24 TAUJ0 Setting k 0 1 TAUJ0 TINm input pulse interval measurement function Function Register Bit Position Bit Name Set Value Note TAUJ0 ...

Page 1421: ...ote TAUB0 TAUB0 CMORm 15 14 CKS1 CKS0 Don t care Sets the operating clock 13 12 CCS1 CCS0 0 0 11 MAS 1 10 to 8 STS2 STS1 STS0 0 0 0 7 6 COS1 COS0 1 1 5 0 Fixed to 0 4 MD4 0 3 MD3 0 2 MD2 1 1 MD1 0 0 MD0 Don t care TAUB0 CMURm 1 0 TIS1 TIS0 1 1 Table 24 26 PIC Setting Function Register Bit Position Bit Name Set Value Note PIC PIC0REG 31 13 12 PIC0REG3113 PIC0REG3112 0 1 Selects DT output signal fro...

Page 1422: ...INTm ENCA0 ENCA0E0 internal input ENCA0E1 internal input ENCA0EC internal input ENCA0I1 internal input ADCA0TRG2 ADCA0TRG1 ADCA0TRG0 1 0 PIC0REG3004 1 0 PIC0REG3003 1 0 PIC0REG3002 INTTAUB0I0 INTTAUB0I15 1 0 PIC0ENCSEL4003 1 0 PIC0ENCSEL4002 1 0 PIC0ENCSEL4001 1 0 PIC0ENCSEL4000 1 0 PIC0ENCSEL4007 1 0 PIC0REG3018 Low level 1 0 PIC0REG3004 1 0 PIC0REG3004 1 0 PIC0REG3003 1 0 PIC0REG3003 1 0 PIC0REG...

Page 1423: ...21 20 19 18 17 16 0 0 0 0 0 PIC0RE G3018 0 0 R R R R R R W R R 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 R R R R R R R R 7 6 5 4 3 2 1 0 0 0 0 PIC0RE G3004 PIC0RE G3003 PIC0RE G3002 0 0 R R R R W R W R W R R Table 24 27 PIC0REG30 Contents Bit Position Bit Name Function 18 PIC0REG3018 Selects the signal to supply the values of the PIC0REG30 4 2 bits 0 Low level input signal 1 The signal selected by the...

Page 1424: ...AUB0Im signal selected by the PIC0ENCSEL400 3 0 bits 0 Disables the output of the TAUB0TINTm signal 1 Enables the output of the TAUB0TINTm signal 3 2 1 0 PIC0ENCSEL4003 PIC0ENCSEL4002 PIC0ENCSEL4001 PIC0ENCSEL4000 Selects the TAUB0TINTm signal as the capture trigger for ENCA0 PIC0ENCSEL400 Input Signal bit3 bit2 bit1 bit0 0 0 0 0 Selects INTTAUB0I0 0 0 0 1 Selects INTTAUB0I1 0 0 1 0 Selects INTTAU...

Page 1425: ...ion 24 4 2 ADC Trigger Selection Function If selected the correct operation cannot be performed because the following loop occurs ADCA0TRG1 generation ENCA0 capture operation ENCAT0EQ1 generation by capture operation ADCA0TRG1 generation The following shows a timing chart of the encoder capture trigger selection function using the ADCAnTRG1 as a trigger Figure 24 22 Operation Example of Encoder Ca...

Page 1426: ...re with TAUB0TINTm trigger 1 TAUB0CNTm TAUB0CNTm 1 and ENCA0 start count operation at the same time by a simultaneous start trigger 2 When TAUB0TINTm TAUB0 CHm interrupt request signal is selected as ENCA0I1 ENCA0 capture trigger 1 signal ENCA0 caption counter value to a capture register by TAUB0TINTm input 3 If the input is not TAUB0TINTm but TAUB0TINTm 1 TAUB0 CHm interrupt request signal the ca...

Page 1427: ...on of ENCA0 encoder timer based on the ADCA0TRG1 signal Change the setting indicated with the symbol depending on the encoder timer to be captured Figure 24 24 Setting Flow START Initial setting Start PIC PIC0REG30 register 00XX X0XXH PIC0ENCSEL400 register X000 XXXXb ENCAkCTL register 0000 001x 000x 0xxxb ENCAkIOC0 register 0000 01xxb ENCAkIOC1 register xxxx xxxxb ENCA0TS register 0000 0001b ENCA...

Page 1428: ...egister ENCA0IOC1 register Change the settings appropriate according to the connection path They must be set with no capture trigger of ENCA0 TAUB0 CH0 is set as interval timer function Change the used CH or timer function appropriate Note 1 Note 2 ENCA0 0000 001X 000X 0XXXb 0000 01XXb XXXX XXXXb TAUB0TOE register TAUB0TO register TAUB0TOM register TAUB0TOC register TAUB0TOL register TAUB0TDE regi...

Page 1429: ...e 24 26 Setting Flow for Encoder Capture Operation by INTTAUB0Im 2 2 1 END START PIC PIC0SSER0 register PIC0SSER2 register Enabling simultaneous start XXXX XXXX XXXX XXX1b 1 X1XX XXXX XXXX XXXXb 1 PIC0SST register Timers simultaneous start 0000 0001b Note 1 Change the settings appropriate according to the used timer ...

Page 1430: ...0 Don t care Selects the ENCA0CCR0 function 7 ENCA0CTS 0 1 Selects ENCA0l1 input as trigger of capture operation 6 5 0 Fixed to 0 4 ENCA0LDE Don t care Enables or disables reload operation when underflow is generated 3 ENCA0ECM1 Don t care Enables or disables clearing of the counter on compare match of ENCA0CCR1 2 ENCA0ECM0 Don t care Enables or disables clearing of the counter on compare match of...

Page 1431: ...selected by the PIC0ENCSEL400 3 0 bits 3 to 0 PIC0ENCSEL4003 PIC0ENCSEL4002 PIC0ENCSEL4001 PIC0ENCSEL4000 Don t care Selects the TAUB0TINTm signal as the capture trigger for ENCA0 Table 24 31 PIC Setting Using INTTAUB0Im Register Bit Position Bit Name Set Value Note PIC0REG30 18 PIC0REG3018 0 Selects INTTAUB0Im interrupt request signal of TAUB0 channel m 4 3 2 PIC0REG3004 PIC0REG3003 PIC0REG3002 0...

Page 1432: ... input ENCA0E1 internal input ENCA0TEQ1 ENCA0 ENCA0E0 ENCA0E1 0 TS0OPCI0 INTTSG20IER TSG20O1 TSG20 ADCA0 INTADCA0TERR SGA ERROROUT TAPA2 Hi Z control PIC0REG3000 0 PIC0REG3001 0 PIC0REG505 0 1 PIC0HIZCEN23 0 1 PIC0HIZCEN20 0 1 PIC0HIZCEN26 0 1 PIC0HIZCEN25 0 PIC0REG506 ESO2 TSG20O2 TSG20O3 TSG20O4 TSG20O5 TSG20O6 TSG20O0 TS0TO1 TS0TO2 TS0TO3 TS0TO4 TS0TO5 TS0TO6 TS0UDC TS0DIAG TSG20O7 0 0 PIC0REG3...

Page 1433: ...rol the two phase encoder Access This register can be read written in 32 bit units Address FF81 C0E8H Initial value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 R R R R R R R R 23 22 21 20 19 18 17 16 0 PIC0RE G3022 0 0 0 0 PIC0RE G3017 PIC0RE G3016 R R W R R R R R W R W 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 R R R R R R R R 7 6 5 4 3 2 1 0 0 0 0 0 0 ...

Page 1434: ...e PIC0REG3000 bit ENCA0E0 internal input and the PIC0REG3001 bit ENCA0E1 internal input 1 Setting is prohibited 17 16 PIC0REG3017 PIC0REG3016 Selects the input of the ENCA0 timer internal input of the ENCA0E0 and ENCA0E1 PIC0REG3017 PIC0REG3016 Input Signal 0 0 Input of the ENCA0E0 and ENCA0E1 ENCA0 timer Other than the above Setting prohibted 1 PIC0REG3001 Selects the signal of the ENCA0E1 intern...

Page 1435: ...ction functions In that case apply the bit definition of the corresponding timer connection function 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 PIC0RE G508 R R R R R R R R W 7 6 5 4 3 2 1 0 0 PIC0RE G506 PIC0RE G505 0 0 0 0 0 R R W R W R R R R R Table 24 33 PIC0REG50 Contents Bit Position Bit Name Function 8 PIC0REG508 Selects the target for input of the TSG20TSTOPC0 signal for the TSG20 timer 0 Inputs E...

Page 1436: ...it definition of the corresponding timer connection function 7 6 5 4 3 2 1 0 0 PIC0HIZ CEN26 PIC0HIZ CEN25 0 PIC0HIZ CEN23 0 0 PIC0HIZ CEN20 R R W R W R R W R R R W Table 24 34 PIC0HIZCEN2 Contents Bit Position Bit Name Function 6 PIC0HIZCEN26 Enables or disables Hi Z output control with the INTADCA0TERR interrupt signal 0 Disable 1 Enable 5 PIC0HIZCEN25 Enables or disables Hi Z output control wit...

Page 1437: ...terrupt It is necessary to match the initial output pattern of timer TSG20 to the set value of the compare register ENCA0CCR1 of the ENCA0 timer before start because clear by Z phase input is not performed Switching between normal and reverse rotations of output patterns should be set with the TS0PSC bit in TS0OPT0 Figure 24 28 Operation Example of Control Method 1 at Up Count Note Write access wi...

Page 1438: ... CPU Offset Offset Offset Offset Offset Offset Offset Offset Offset ENCAnE0 pin ENCAnE1 pin INTENCAnI1 interrupt TSnOPCI0 signal TSG2nO1 to TSG2nO6 pins 0º 300º 240º 180º 120º 60º 0º 300º 240º 16 bit counter ENCAnCCR0 register ENCAnCCR1 register INT INT INT INT INT INT INT Pattern 6 Pattern 5 Pattern 4 Pattern 3 Pattern 2 Pattern 1 Pattern 6 Pattern 5 Pattern 4 CPU CPU CPU CPU CPU CPU CPU CPU INT ...

Page 1439: ...Xb ENCA0IOC1 register 0000 00XXb ENCA0CCR0 register XXXXH ENCA0CCR1 register XXXXH ENCA0CNT register XXXXH ENCA0TS register 0000 0001b TS0TRG0 register 0000 0001b TS0CTL0 register 000X 0011b TS0CTL3 register 0000 00XXb TS0CTL4 register 0000 0XXXH TS0IOC0 register 00H TS0IOC2 register 0XXX XXX0 0000 0000b TS0IOC0 register 7EH TS0OPT0 register 0011 1XX0b TS0OPT1 register 0000 0XXXb TS0CMP 0 register...

Page 1440: ...NCA0CCR1 Rewrite Flow during Operation Figure 24 32 Operation Stop Flow END INTENCA0I1 interrupt processing Compute the next output pattern switching timing on interrupt generation Set switching timing in ENCA0CCR1 Stop processing Operation stop setting TSG20 ENCA0 END TS0TRG1 register 0000 0001b ENCA0TT register 0000 0001b ...

Page 1441: ... operation when underflow is generated 3 ENCA0ECM1 0 Enables or disables clearing of the counter on compare match of ENCA0CCR1 2 ENCA0ECM0 1 Enables or disables clearing of the counter on compare match of ENCA0CCR0 1 0 ENCA0UDS1 ENCA0UDS0 Don t care Selects the counter up down control by ENCA0E0 ENCA0E1 ENCA0IOC1 7 ENCA0SCE 0 Enables the special encoder clear 6 ENCA0ZCL 0 Selects the clear level o...

Page 1442: ...0TO3 bits in TS0IOC2 2 TS0TOE2 0 1 Enables or disables rewriting of the TS0OL2 and TS0TO2 bits in TS0IOC2 1 TS0TOE1 0 1 Enables or disables rewriting of the TS0OL1 and TS0TO1 bits in TS0IOC2 TS0IOC2 14 TS0OL6 Don t care Selects an active level of the TSG20O6 output 13 TS0OL5 Don t care Selects an active level of the TSG20O5 output 12 TS0OL4 Don t care Selects an active level of the TSG20O4 output ...

Page 1443: ...ition Bit Name Set Value Note PIC PIC0REG30 22 PIC0REG3022 See the block diagram Selects the ENCA0E0 ENCA0E1 ENCA0EC pin input 17 16 PIC0REG3017 PIC0REG3016 See the block diagram Selects the ENCA0E0 ENCA0E1 pin input 1 PIC0REG3001 See the block diagram Selects the ENCA0E1 pin input 0 PIC0REG3000 See the block diagram Selects the ENCA0E0 pin input PIC0REG50 8 PIC0REG508 See the block diagram Select...

Page 1444: ... ENCA0 TSG20 TAPA2 ENCA0E0 internal input ENCA0E1 internal input ENCA0TEQ1 ENCA0 ENCA0E0 ENCA0E1 0 TS0OPCI0 INTTSG20IER TSG20O1 TSG20 ADCA0 INTADCA0TERR SGA ERROROUT TAPA2 Hi Z control PIC0REG3000 0 PIC0REG3001 0 PIC0REG505 0 1 PIC0HIZCEN23 0 1 PIC0HIZCEN20 0 1 PIC0HIZCEN26 0 1 PIC0HIZCEN25 0 PIC0REG506 ESO2 TSG20O2 TSG20O3 TSG20O4 TSG20O5 TSG20O6 TSG20O0 TS0TO1 TS0TO2 TS0TO3 TS0TO4 TS0TO5 TS0TO6 ...

Page 1445: ...PIC0RE G3017 PIC0RE G3016 R R W R R R R R W R W 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 R R R R R R R R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 PIC0RE G3001 PIC0RE G3000 R R R R R R R W R W Table 24 38 PIC0REG30 Contents Bit Position Bit Name Function 22 PIC0REG3022 Selects the input pin of the ENCA0 timer internal input of the ENCA0E0 and ENCA0E1 0 A signal selected by the PIC0REG3000 bit ENCA0E0 internal inpu...

Page 1446: ...ction functions In that case apply the bit definition of the corresponding timer connection function 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 PIC0RE G508 R R R R R R R R W 7 6 5 4 3 2 1 0 0 PIC0RE G506 PIC0RE G505 0 0 0 0 0 R R W R W R R R R R Table 24 39 PIC0REG50 Contents Bit Position Bit Name Function 8 PIC0REG508 Selects the target for input of the TSG20TSTOPC0 signal for the TSG20 timer 0 Inputs E...

Page 1447: ...it definition of the corresponding timer connection function 7 6 5 4 3 2 1 0 0 PIC0HIZ CEN26 PIC0HIZ CEN25 0 PIC0HIZ CEN23 0 0 PIC0HIZ CEN20 R R W R W R R W R R R W Table 24 40 PIC0HIZCEN2 Contents Bit Position Bit Name Function 6 PIC0HIZCEN26 Enables or disables Hi Z output control with the INTADCA0TERR interrupt signal 0 Disable 1 Enable 5 PIC0HIZCEN25 Enables or disables Hi Z output control wit...

Page 1448: ...upt unlike in control method 1 The ENCA0CCR1 value can be rewritten with the INTENCA0I1 interrupt It is necessary to match the initial output pattern of TSG20 to the set value of ENCA0CCR0 before start because clear by encoder clear input is not performed Switching between normal and reverse rotations of output patterns should be set with the TS0PSC bit in TS0OPT0 Figure 24 34 Operation Example of...

Page 1449: ...pt INTENCAnI1 interrupt TSnOPCI0 signal TSG2nO1 to TSG2nO6 pins 0º 60º 120º 180º 240º 300º 0º 16 bit counter ENCAnCCR0 register Pattern 1 Pattern 2 Pattern 3 Pattern 4 Pattern 5 Pattern 6 Pattern 6 Retard Retard Retard Retard Retard Retard ENCAnCCR1 register ENCAnE0 pin ENCAnE1 pin INTENCAnI0 interrupt INTENCAnI1 interrupt TSnOPCI0 signal TSG2nO1 to TSG2nO6 pins 0º 0º 60º 120º 180º 240º 300º 300º ...

Page 1450: ...Xb ENCA0IOC1 register 0000 00XXb ENCA0CCR0 register XXXXH ENCA0CCR1 register XXXXH ENCA0CNT register XXXXH ENCA0TS register 0000 0001b TS0TRG0 register 0000 0001b TS0CTL0 register 000X 0011b TS0CTL3 register 0000 00XXb TS0CTL4 register 0000 0XXXH TS0IOC0 register 00H TS0IOC2 register 0XXX XXX0 0000 0000b TS0IOC0 register 7EH TS0OPT0 register 0011 1XX0b TS0OPT1 register 0000 0XXXb TS0CMP0 register ...

Page 1451: ...t output pattern switching timing on interrupt generation Set switching timing in ENCA0CCR1 END Start of retard processing Enable INTENCA0I1 interrupt INTENCA0I1 interrupt processing first time INTENCA0I1 interrupt processing second time Disable INTENCA0I1 interrupt END END INTENCA0I1 interrupt processing second time Mask the TSOPCI0 signal connection set the TS0STE bit in TS0OPT0 to 0 Compute the...

Page 1452: ...les or disables reload operation when underflow is generated 3 ENCA0ECM1 0 Enables or disables clearing of the counter on compare match of ENCA0CCR1 2 ENCA0ECM0 1 Enables or disables clearing of the counter on compare match of ENCA0CCR0 1 0 ENCA0UDS1 ENCA0UDS0 Don t care Selects the counter up down control by ENCA0E0 ENCA0E1 ENCA0IOC1 7 ENCA0SCE 0 Enables the special encoder clear 6 ENCA0ZCL 0 Sel...

Page 1453: ...O3 bits in TS0IOC2 2 TS0TOE2 0 1 Enables or disables rewriting of the TS0OL2 and TS0TO2 bits in TS0IOC2 1 TS0TOE1 0 1 Enables or disables rewriting of the TS0OL1 and TS0TO1 bits in TS0IOC2 TS0IOC2 14 TS0OL6 Don t care Selects an active level of the TSG20O6 output 13 TS0OL5 Don t care Selects an active level of the TSG20O5 output 12 TS0OL4 Don t care Selects an active level of the TSG20O4 output 11...

Page 1454: ...ition Bit Name Set Value Note PIC PIC0REG30 22 PIC0REG3022 See the block diagram Selects the ENCA0E0 ENCA0E1 ENCA0EC pin input 17 16 PIC0REG3017 PIC0REG3016 See the block diagram Selects the ENCA0E0 ENCA0E1 pin input 1 PIC0REG3001 See the block diagram Selects the ENCA0E1 pin input 0 PIC0REG3000 See the block diagram Selects the ENCA0E0 pin input PIC0REG50 8 PIC0REG508 See the block diagram Select...

Page 1455: ...signal input to the TSG20PTSI0 to TSG20PTSI2 pins to the ENCA0 timer to perform count operation 24 4 8 2 Configuration Figure 24 41 Block Diagram of Timer Configuration 1 Configuration Timer Function ENCA TSG2 Timer configuration ENCA0 TSG20 TSG20PTSI0 TS0PUD TS0PEC TSG20 TSG20PTSI0 ENCA0 0 PIC0REG500 1 PIC0REG3000 1 PIC0REG3001 TSG20PTSI1 TSG20PTSI1 TSG20PTSI2 TSG20PTSI2 ENCA0E0 internal input EN...

Page 1456: ...nnection functions In that case apply the bit definition of the corresponding timer connection function 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 R R R R R R R R 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 R R R R R R R R 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 R R R R R R R R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 PIC0RE G3001 PIC0RE G3000 R R R R R R R W R W Table 24 44 PIC0REG30 Contents Bit Position Bit Name Fun...

Page 1457: ... C0F8H Initial value 00H This register is initialized by any reset Caution The bit might be defined to 0 by other timer connection functions In that case apply the bit definition of the corresponding timer connection function 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 R R R R R R R R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 PIC0RE G500 R R R R R R R R W Table 24 45 PIC0REG50 Contents Bit Position Bit Name Functio...

Page 1458: ...4 Peripheral Interconnection PIC 24 4 8 4 Example of Operation Figure 24 42 Operation Example of Three Phase Encoder Function TSG20PTSI2 pin TSG20PTSI1 pin TSG20PTSI0 pin TS0PEC signal output ENCA0E0 signal input TS0PUD signal output ENCA0E1 signal input ENCA0CNT 16 bit counter ...

Page 1459: ...ing Three Phase Encoder Function Caution If noise is generated on the TSG20PTSI2 to TSG20PTSI0 pins the 16 bit counter ENCA0CNT erroneously counts the noise edges 15 16 17 18 19 20 21 Normal rotation TSG20PTSI2 TSG20PTSI1 TSG20PTSI0 TS0PEC output ENCA0E0 input TS0PUD output ENCA0E1 input 16 bit counter Reverse rotation 22 23 24 25 26 27 28 29 30 29 28 27 26 25 24 23 22 ...

Page 1460: ...CA0CCR0 register XXXXH ENCA0CCR1 register XXXXH ENCA0CNT register XXXXH TS0CTL0 register 0000 0011b TS0CTL3 register 0000 00XXb TS0CTL4 register 0000 0XXXH TS0IOC1 register 0001 0000b TS0IOC0 register 00H TS0IOC2 register 0XXX XXX0 0000 0000b TS0IOC0 register 7EH TS0OPT0 register 0010 XXX0b TS0OPT1 register 0000 0XXXb TS0CMP0 register XXXXH TS0CMP1W 1 2 register XXXX XXXXH TS0CMP5W 5 6 register XX...

Page 1461: ...A0CCR1 4 ENCA0LDE 0 Enables or disables reload operation when underflow is generated 3 ENCA0ECM1 0 Enables or disables clearing of the counter on compare match of ENCA0CCR1 2 ENCA0ECM0 0 Enables or disables clearing of the counter on compare match of ENCA0CCR0 1 0 ENCA0UDS1 ENCA0UDS0 0 0 Selects the counter up down control by ENCA0E0 ENCA0E1 ENCA0IOC1 7 ENCA0SCE 0 Enables the special encoder clear...

Page 1462: ...lects an active level of the TSG20O6 output 13 TS0OL5 Don t care Selects an active level of the TSG20O5 output 12 TS0OL4 Don t care Selects an active level of the TSG20O4 output 11 TS0OL3 Don t care Selects an active level of the TSG20O3 output 10 TS0OL2 Don t care Selects an active level of the TSG20O2 output 9 TS0OL1 Don t care Selects an active level of the TSG20O1 output TS0OPT0 6 TS0SOC Don t...

Page 1463: ...tion Bit Name Set Value Note PIC PIC0REG30 1 PIC0REG3001 See the block diagram Outputs the TS0PUD signal of TSG20 and selects the ENCA0E1 input of ENCA0 timer 0 PIC0REG3000 See the block diagram Selects the TS0PEC signal of TSG20 and selects the ENCA0E0 input of ENCA0 timer PIC0REG50 0 PIC0REG500 See the block diagram Selects TSG20PTSI0 to TSG20PTSI2 pin input ...

Page 1464: ...ue according to the TSOUT signal that is output from the CAN controller on reception of a data frame The CPU reads the captured value and obtains the time when the capture event occurred in other words the time stamp of the message received via the CAN bus 24 4 9 2 Configuration Figure 24 46 Block Diagram of CAN Time Stamp Function Configuration Timer Function CAN TAUB Configuration 1 CAN0 TAUB0 C...

Page 1465: ...signal toggle operation is disabled by setting FCNnCMTSCTL FCNnCMTSTSGE to 0 Caution 3 CAN time stamping and baud rate detection for slave operation in LIN communications cannot be used simultaneously When CAN time stamping is to run do not input the signal for the UARTH function as the timer input signal for channels 8 and 9 of TAUB0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 PIC0REG 3125 PIC0REG 3124 R...

Page 1466: ...are selected as the input trigger signals for channels 4 5 and 6 of TAUB0 and adjustment of the timing of the output signals from TSG20 and TAUB0 is selectable Note The unit number of the individual macro units is represented by the suffix n n 0 1 24 4 10 2 Configuration The configuration of this function is described below Table 24 50 Configuration of Timer Configuration Timer Function TSG2 TAUB ...

Page 1467: ... Diagram of TSG20 and TAUB0 Dead Time Reduction Function TAUB0 TSG20INT0 TSG20INT2 TSG20INT6 TSG20INT10 TSG20 PIC0REG5012 0 1 PIC0REG20028 1 TO P2U TO P2UB TO P2V TO P2VB TO P2W TO P2WB TSG20T01 TSG20T02 TSG20T03 TSG20T04 TSG20T05 TSG20T06 PIC0REG5013 0 PIC0REG5014 1 TAUB0TIN4 TAUB0TIN5 TAUB0TIN6 TAUB0TOUT4 TAUB0TOUT5 TAUB0TOUT6 ...

Page 1468: ...ed to 0 by other timer connection functions In that case apply the bit definition of the corresponding PIC connection function 15 14 13 12 11 10 9 8 0 PIC0REG 5014 0 PIC0REG 5012 0 0 0 0 R R W R R W R R R R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R R R R R R R R Table 24 51 PIC0REG50 Contents Bit Position Bit Name Function 14 PIC0REG5014 Select the TOP2U UB TOP2V VB and TOP2W WB output signals Be sure to ...

Page 1469: ...00H This register is initialized by any reset Caution1 Be sure to set the PIC0REG2028 bit to 1 when using the TSG20 and TAUB0 dead time reduction function Caution 2 The bit might be defined to 0 by other timer connection functions In that case apply the bit definition of the corresponding PIC connection function 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 R R R R R R R R 23 22 21 20 19 18 17 16 0 0 0 ...

Page 1470: ...e 0 interrupt signal TSG20INT0 as the timer start trigger signal for input to the TAUB0 channels TAUB0TIN4 5 6 For the connection of the combination see Table 24 50 The following is an overview of the connection and example of operation Figure 24 48 Overview of TSG20 Compare 0 Interrupt and TAUB0 Connection TSG20 TSG20TO1 TSG20TO2 TSG20TO3 TSG20TO4 TSG20TO5 TSG20TO6 TSG20INT0 TAUB0 TAUB0TIN4 TAUB0...

Page 1471: ... io n s T S 0 C M P 2 T S 0 C M P 0 C o u n t e r v a lu e s e t i n T A U B 0 s e t t in g o f D T C 0 T h e o p e r a t in g c lo c k s o f T S G 2 0 a n d T A U B 0 a r e s y n c h r o n iz e d w i t h t h e in t e r n a l c lo c k P C L K E x a m p le o f o p e r a t io n T S G 2 0 s e t t in g T S 0 C M P 0 9 1 0 c y c le s T S 0 C M P 2 T S 0 C M P 0 9 T S 0 D T C 0 3 T S 0 D T C 1 3 T A U B...

Page 1472: ...G20INT2 6 10 as the timer start trigger signal for input to the TAUB0 channels TAUB0TIN4 5 6 For the connection of the combination see Table 24 50 The following is an overview of the connection and example of operation Figure 24 50 Overview of TSG20 Compare 0 Interrupt and TAUB0 Connection TSG20 TSG20TO1 TSG20TO2 TSG20TO3 TSG20TO4 TSG20TO5 TSG20TO6 TSG20INT2 TSG20INT6 TSG20INT10 TAUB0 TAUB0TIN4 TA...

Page 1473: ...8 7 0 9 2 1 4 3 6 5 8 7 0 9 2 1 I n t e r n a l c lo c k T S G 2 0 c o u n t e r T S G 2 0 T O 1 T S G 2 0 T O 2 T A U B 0 c o u n t e r T A U B 0 T O U T 4 U p h a s e A N D w a v e U B p h a s e A N D w a v e O p e r a t io n w h e n t h e s e t t in g o f T S 0 C M P 1 is 6 T S G 2 0 I N T 2 P O R T o u t p u t U P O R T o u t p t u U B T S G 2 0 T A U B 0 P I C A N D C o n d it io n s C o u n ...

Page 1474: ...x10b TS0CMP0 register Don t care TS0CMP1W register Don t care TS0CMP5W register Don t care TS0CMP9W register Don t care TS0DTC0W register Don t care TS0DTC1W register Don t care TAUB0 timer start TAUB0TS xxxx xxxx x111 xxxxb TSG20 timer start PICB PIC0REG200 register xxx1 xxxx xxxx xxxx xxxx xxxx xxxx xxxxb PIC0REG50 register x100 xxxx xxxx xxxxb or x101 xxxx xxxx xxxxb END Update the setting of T...

Page 1475: ... TS0CMP0 Don t care Comparison register Set the PWM cycle TS0CMP1W Don t care Comparison register Set the value for comparison When the compare 0 interrupt is to be used set TS0CMP2 TS0CMP0 TS0CMP1W Don t care Comparison register Set the value for comparison When the compare 0 interrupt is to be used set TS0CMP6 TS0CMP0 TS0CMP1W Don t care Comparison register Set the value for comparison When the ...

Page 1476: ...STS2 STS0 0 0 1 Select the valid edge of the TAUB0TI4 5 and 6 input signals that is to act as an external start trigger 7 6 COS1 COS0 0 0 Not used 4 0 MD4 MD0 1 0 1 0 0 Select the pulse one count mode Disable the start trigger during operation TAUB0CMUR6 TAUB0CMUR5 TAUB0CMUR4 1 0 TIS1 TIS0 0 1 Select the detection of rising edges TAUB0TOE 6 4 TAUB0TOE06 TAUB0TOE04 1 1 1 Channels 4 5 and 6 Enable t...

Page 1477: ... the TSG20 output comparison interrupt signal as the signal for input to the TAUB0TIN4 5 and 6 input pins the signal selected by bit 12 in PIC0REG50 Table 24 55 PICB Settings for the TSG20 Compare 2 6 and 10 Interrupts and TAUB0 Operation Function Register Bit Position Bit Name Set Value Note PIC PIC0REG50 14 PIC0REG5014 1 Select the logical AND of the TAUB0TOUT4 5 and 6 signals for resetting the ...

Page 1478: ... of this function is described below Figure 24 53 Block Diagram of TAUB Input Selection Table 24 56 Configuration of Timer Configuration Timer Function TAUB Timer configuration TAUB0 Configuration and Pin Functions of Each Timer TAUB Input pin TAUB0 external input TAUB0I6 TAUB0I7 TAUB0I8 TAUB0I9 TAUB0I10 TAUB0I11 Port TAUB0TIN6 TAUB0TIN7 PIC0REG20002 0 Port Port TAUB0I6 TAUB0I7 TAUB0I8 TAUB0I9 TAU...

Page 1479: ...onding PIC connection function 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 R R R R R R R R 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 R R R R R R R R 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 R R R R R R R R 7 6 5 4 3 2 1 0 0 0 PIC0RE G20005 PIC0RE G20004 PIC0RE G20003 PIC0RE G20002 0 0 R R R W R W R W R W R R Table 24 57 PIC0REG200 Contents Bit Position Bit Name Function 5 PIC0REG20005 Select the TAUB0 CH09...

Page 1480: ... 23 22 21 20 19 18 17 16 0 0 0 0 PIC0RE G20219 PIC0RE G20218 PIC0RE G20217 PIC0RE G20216 R R R R R W R W R W R W 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 R R R R R R R R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R R R R R R R R Table 24 58 PIC0REG202 Contents 1 2 Bit Position Bit Name Function 30 PIC0REG20230 Select the TAUB0 CH11 input signal PIC0REG20230 Input Signal 0 Select the signal TAUB0I11 set by bits ...

Page 1481: ...REG20228 Input Signal 0 Select the signal TAUB0I7 set by bit 3 in PIC0REG200 1 Select the signal TAUB0I6 set by bit 2 in PIC0REG200 19 18 PIC0REG20219 PIC0REG20218 Select the TAUB0 CH11 input signal PIC0REG20019 PIC0REG20018 Input Signal 0 0 TAUB0I11 Other than the above Setting is prohibited 17 16 PIC0REG20217 PIC0REG20216 Select the TAUB0 CH10 input signal PIC0REG20017 PIC0REG20016 Input Signal ...

Page 1482: ...7 connection 1 TAUB0I6 connected 0 No connection TAUB0I7 Disable the signal connection to TAUB0TIN6 Set PIC0REG20228 to select the TAUB0TIN7 connection 1 TAUB0I7 connected 0 No connection TAUB0I8 TAUB0I9 TAUB0I8 Connect the TAUB0I8 signal to TAUB0I8TAUB0TIN8 Set PIC0REG20229 to select the TAUB0TIN9 connection 1 TAUB0I8 connected 0 No connection TAUB0I9 Disable the signal connection to TAUB0TIN8 Se...

Page 1483: ...ate with the host via the on chip debugging emulator by using the following interface Nexus debugging interface DCUTRST DCUTCK DCUTMS DCUTDI DCUTDO and DCUTRDY signals LPD interface single pin debugging interface LPDIO signal 2 Debugging Monitor The basic debugging functions below can be used by running a monitor program in a memory space for debugging while the user created program is suspended D...

Page 1484: ...l obtained by dividing the CPU clock frequency by eight 10 Masking The following signal can be masked RESET internal resets 11 Selecting if Peripheral I O Modules Run or Stop during Breaks Whether peripheral I O modules run or stop is selectable Peripheral I O modules always stop operating during a break Watchdog timer WDTA0 Selecting whether modules run or stop during a break Timers TSG2n TAUBn T...

Page 1485: ...t OCD For details of how to set the ID code see the user s manual for the software tools you are using 14 Trigger Events The trigger events detect an event with four step sequential execution on the execution address the access address the access data and the range comparison of large and small sizes ...

Page 1486: ...exus Debugging Interface Figure 25 1 Pins Used for Connection with the On Chip Debugging Emulator On chip debugging emulator DCUTRST DCUTCK DCUTMS DCUTDI DCUTDO DCUTRDY RESET EVSS EVDD DCUEVTO FLMD0 DCUTRST DCUTCK DCUTMS DCUTDI DCUTDO DCUTRDY RESET GND VDD FLMD0 Microcontroller Note Connect the DCUEVTO pin if the on chip debugging emulator supports this signal ...

Page 1487: ...y resetting the debugging functions of the microcontroller DCUTCK Clock signal used in debugging DCUTMS Signal to select the mode of data transfer DCUTDI Input data signal for the microcontroller DCUTDO Output data signal from the microcontroller DCUTRDY Synchronization signal for data transfer RESET Reset signal for the microcontroller this is connected so that the microcontroller is placed in th...

Page 1488: ...nnection with the on Chip Debugging Emulator LPD I F In Single pin debugging the DCUTRST pin must always be pulled down externally LPD I F Single pin debugging interface DCUTRST DCUTCK DCUTMS DCUTDI LPDI0 DCUTDO DCUTRDY RESET EVSS EVDD DCUEVTO FLMDO RESET GND VDD LPDI0 Microcontroller Table 25 2 Pins Used for Connection with the on Chip Debugging Emulator LPD I F Pin Name Function LPDIO Dedicated ...

Page 1489: ...e Nexus debugging interface and single pin debugging interface but does not support changing the debugging interface during on chip debugging To change the debugging interface set the RESET and DCUTRST pins to the low level and then turn the power supply off and on 5 Terminating operation in on chip debugging mode under any of the following conditions causes operation to become undefined After ter...

Page 1490: ... required to execute self diagnosis and then generate a self diagnostic BIST reset so that the transition to the state of running the user created program is possible 10 A reset during the self diagnosis BIST in debugging mode cannot be masked by the settings of the debugger 11 In debugging mode a reset cannot be performed during the period where the HEAPCLK is stopped during the flash reset seque...

Page 1491: ...T pin while the FLMD0 pin is at the high level used for self programming etc in the on chip debugging mode Re apply the high level on the RESET pin while the FLMD0 pin is at the low level 5 Starting communications by placing the low level on the LPDIO pin during BIST stops communications with the tool Only start communications with the microcomputer after BIST has been executed 6 If a reset RESET ...

Page 1492: ...gnosis BIST in debugging mode cannot be masked by the settings of the debugger 12 In debugging mode a reset cannot be performed during the period where the HEAPCLK is stopped during the flash reset sequence PLL lockup time and OSC stabilization time Execute a reset operation during the period other than that where the HEAPCLK is stopped ...

Page 1493: ...e 26 1 List of Pins Used for the Power Supply Pin Name Function Pin Number EVDD Power supply for flash memory and external pins 25 59 60 98 VDD Power supply for internal regulators and POF LVI CREG 7 Main 8 36 65 96 OSCVDD Power supply for the oscillator 15 AVDD Power supply for the AD converter 76 REGC0 Pin for connecting the capacitor for the internal regulator for CREG 5 REGC1 Pin for connectin...

Page 1494: ...arameter That is the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded The ratings and conditions shown below for DC characteristics and AC characteristics are within the range for normal operation and quality assurance Ite...

Page 1495: ...VSS0 0 V Item Symbol Conditions MIN TYP MAX Unit Input capacitance CI fC 1 MHz 0 V for non measured pins and excluding analog pins selected for use with S H channels or AD converter channels 15 pF I O capacitance CIO 15 pF Output capacitance CO 15 pF Internal Operation Clock Frequency Operating Ambient Temperature Ta Power Supply Voltage fxx 48 MHz Ta 40 to 125 C VDD EVDD OSCVDD 3 0 to 5 5 V AVDD0...

Page 1496: ...nd X2 terminals Do not pass other signal conductors through the broken line part in the above figure Do not route the wiring near signal lines through which a high fluctuating current flows Always make the ground point of the oscillator capacitor the same potential as OSCVSS Do not ground the capacitor to a ground pattern through which a high current flows Do not fetch signals from the oscillator ...

Page 1497: ...ection 27 Electrical Characteristics 27 4 2 Characteristics of Internal Oscillation Circuit Ta 40 to 125 C VDD EVDD OSCVDD 3 0 to 5 5 V AVDD0 4 2 to 5 5 V VSS EVSS OSCVSS AVSS0 0 V Item Symbol Conditions MIN TYP MAX Unit Internal oscillation frequency fROSC 7 2 8 8 8 MHz ...

Page 1498: ...0 3 V VIH2 FLMD1 pin JP0_1 JP0_3 JP0_5 0 8 EVDD EVDD 0 3 V VIH3 6 7 DCUTDI DCUTMS DCUTCK DCUTRST 2 2 EVDD 0 3 V VIH4 6 8 DCUTDI DCUTMS DCUTCK DCUTRST 2 0 EVDD 0 3 V VIH5 RESET pin 0 8 EVDD EVDD 0 3 V Low level input voltage VIL1 Port pins FLMD0 pin 0 3 0 3 EVDD V VIL2 FLMD1 pin JP0_1 JP0_3 JP0_5 0 3 0 2 EVDD V VIL3 6 DCUTDI DCUTMS DCUTCK 0 3 0 8 V VIL4 RESET pin DCUTRST 0 3 0 6 V Hysteresis width ...

Page 1499: ...s not being performed at the target pins Note 2 The current flowing through the pull up pull down resistors is not included Note 3 Port pins JP0_1 to JP0_3 and JP0_5 Note 4 Port pins JP0_1 to JP0_3 and JP0_5 FLMD1 pin DCUTRST pin and RESET pin Item Symbol Condition MIN TYP MAX Unit High level input leakage current ILIH1 VIAN AVDD0 Analog pins 1 0 3 μA VI EVDD LPDIO pin 40 μA VI EVDD Pins other tha...

Page 1500: ...total current flowing through these pins and output currents does not exceed 50 mA Item Symbol Conditions MIN TYP MAX Unit Power supply current 1 Normal operating conditions IDD Internal power supply current VDD fxx 48 MHz PCLK 1 1HEAPCLK 55 115 mA PCLK 1 2HEAPCLK 47 100 mA fxx 64 MHz PCLK 1 1HEAPCLK 72 150 mA PCLK 1 2HEAPCLK 63 130 mA fxx 80 MHz PCLK 1 1HEAPCLK 90 185 mA PCLK 1 2HEAPCLK 79 160 mA...

Page 1501: ... of 1538 Jul 17 2014 V850E2 PG4 L Section 27 Electrical Characteristics Note MAX is the maximum value over temperature voltage range and manufacturing condition The current when executing BIST is the average current when executing BIST ...

Page 1502: ...t Conditions Input waveform for AC testing AC test output measurement points Load conditions Caution If the load capacitance exceeds 35 pF due to the circuit configuration bring the load capacitance of the device to 35 pF or less by inserting a buffer or by some other means 90 10 90 10 EVDD EVSS 90 10 90 10 EVDD EVSS DUT Device under test CL 35pF ...

Page 1503: ... Ta 40 to 125 C VDD EVDD OSCVDD 3 0 to 5 5 V AVDD0 4 2 to 5 5 V VSS EVSS OSCVSS AVSS0 0 V Item Symbol Conditions MIN MAX Unit CLKOUT output cycle time tCYK 0 05 512 μs CLKOUT high level width tWKH tCYK 2 15 ns CLKOUT low level width tWKL tCYK 2 15 ns CLKOUT rise time tKR 15 ns CLKOUT fall time tKF 15 ns CLKOUT tKF tWKH tWKL tCYK tKR ...

Page 1504: ...nal reset RESET whenever the power supply voltage falls below the operating voltage Caution3 The voltage should be applied to AVREF0P after power is supplied to AVDD0 or at the same time AVREF0P AVDD0 Caution4 The power to AVREF0P should be shut down before the power to AVDD0 is shut down or at the same time AVREF0P AVDD0 Item Symbol Conditions MIN MAX Unit Voltage slope VDD tRAA 0 V to 3 V 0 5 V ...

Page 1505: ...e 1505 of 1538 Jul 17 2014 V850E2 PG4 L Section 27 Electrical Characteristics VDD EVDD OSCVDD 3 0V 4 5V tRAA tRAI tFAI tFRA tFRI tFIA tRIA tRAR tRIR tRMR0 1 tFRM0 1 3 0V 4 5V 3 0V 4 5V VIL VIH VIH VIL 3 0V 4 5V AVDD0 RESET FLMD1 0 ...

Page 1506: ...riate condenser to be connected with REGC0 and REGC1 after fully evaluating Item Symbol Conditions MIN TYP MAX Unit Input voltage VDD 3 0 5 5 V Output voltage CREG VRO0 1 35 1 5 1 65 V Output voltage main VRO1 1 35 1 5 1 65 V REGC0 capacity REGC0 3 29 4 7 6 11 μF REGC1 capacity REGC1 0 07 0 1 0 13 μF Output voltage stabilization time CREG RAVS0 1 ms Output voltage stabilization time main RAVS1 200...

Page 1507: ... V AVDD0 4 2 to 5 5 V VSS EVSS OSCVSS AVSS0 0 V Caution The above values are for pulse widths that ensure detection of an effective edge An effective edge may also be detected even if the input pulse width is less than the above specification Item Symbol Conditions MIN MAX Unit RESET input low level width tWRSL Other than power supply turning on 500 ns tW R S L RESET ...

Page 1508: ...4 5 Caution The above values are for pulse widths that ensure detection of an effective edge An effective edge may also be detected even if the input pulse width is less than the above specification Note n 0 to 9 Item Symbol Conditions MIN MAX Unit NMI input high level width tWNIH Digital filter 1 ns NMI input low level width tWNIL Digital filter 1 ns INTPn input high level width tWITH Digital fil...

Page 1509: ...OSCVSS AVSS0 0 V Caution The above values are for pulse widths that ensure detection of an effective edge An effective edge may also be detected even if the input pulse width is less than the above specification Note n 0 or 2 Item Symbol Conditions MIN MAX Unit ESOn input high level width tWESOH Analog filter 500 ns ESOn input low level width tWESOL Analog filter 500 ns ESOn tW E S O H tW E S O L ...

Page 1510: ...S AVSS0 0 V Caution The above values are for pulse widths that ensure detection of an effective edge An effective edge may also be detected even if the input pulse width is less than the above specification Note n 0 to 2 Item Symbol Conditions MIN MAX Unit ADCA0TRGn input high level width tWADTH Analog filter 500 ns ADCA0TRGn input low level width tWADTL Analog filter 500 ns ADCA0TRGn tW A D T H t...

Page 1511: ...2 3 4 5 Caution The above values are for pulse widths that ensure detection of an effective edge An effective edge may also be detected even if the input pulse width is less than the above specification Item Symbol Conditions MIN MAX Unit TI input high level width tTIH TAUB0I0 15 TAUJ0I0 3 TSG20PTSI0 2 ENCA0E0 1 ENCA0EC 1 ns TI input low level width tTIL TAUB0I0 15 TAUJ0I0 3 TSG20PTSI0 2 ENCA0E0 1...

Page 1512: ...S AVSS0 0 V Note 1 When PCLK 32 MHz is selected 1000 PCLK cycles 4 ns Note tPCLK PCLK cycles n 0 1 Item Symbol Conditions MIN MAX Unit CSIGnSC cycle time 1 tKCYM Output 125 ns CSIGnSC high low level width tKWHM tKWLM Output tKCYM 2 20 ns CSIGnSI setup time to CSIGnSC tSSIM 30 ns CSIGnSI hold time to CSIGnSC tHSIM 10 ns CSIGnSO output delay time to CSIGnSC tDSOM 10 ns CSIG1RYI setup time to CSIG1SC...

Page 1513: ...teristics CSIGnSC CSIGnSI CSIGnSO Master mode CSIGnCTL1 CSIGnCKR CSIGnCFG0 CSIGnDAP 0 0 or 1 1 Master mode CSIGnCTL1 CSIGnCKR CSIGnCFG0 CSIGnDAP 1 0 or 0 1 Note n 0 1 CSIGnSC CSIGnSO CSIGnSI tKC YM tKW LM tK WHM tSS IM tHS IM tDSO M CSIGnSC CSIGnSO CSIGnSI tKC YM tKW HM tK WLM tSS IM tHS IM tDSO M ...

Page 1514: ... Page 1514 of 1538 Jul 17 2014 V850E2 PG4 L Section 27 Electrical Characteristics CSIGnSC CSIGnRYI Master mode CSIGnCTL1 CSIGnCKR 0 Master mode CSIGnCTL1 CSIGnCKR 1 Note n 0 1 CSIGnSC tS RY I CSIGnRYI CSIGnSC tS RY I CSIGnRYI ...

Page 1515: ...S0 0 V Note 1 When PCLK 48 MHz is selected 1000 PCLK cycles 6 ns Note tPCLK PCLK cycles n 0 1 Item Symbol Conditions MIN MAX Unit CSIGnSC cycle time 1 tKCYS Input 150 ns CSIGnSC high low level width tKWHS tKWLS Input tKCYS 2 20 ns CSIGnSI setup time to CSIGnSC tSSIS 15 ns CSIGnSI hold time to CSIGnSC tHSIS tPCLK 10 ns CSIGnSO output delay time to CSIGnSC tDSOS 30 ns CSIG1RYO output delay tSRYO 30 ...

Page 1516: ...cteristics CSIGnSC CSIGnSI CSIGnSO Slave mode CSIGnCTL1 CSIGnCKR CSIGnCFG0 CSIGnDAP 0 0 or 1 1 Slave mode CSIGnCTL1 CSIGnCKR CSIGnCFG0 CSIGnDAP 1 0 or 0 1 Note n 0 1 CSIGnSC CSIGnSO CSIGnSI tKC YS tKW LS tK WHS tSS IS tHS IS tDSO S CSIGnSC CSIGnSO CSIGnSI tKC YS tKW HS tK WLS tSS IS tHS IS tDSOS ...

Page 1517: ...38 Jul 17 2014 V850E2 PG4 L Section 27 Electrical Characteristics CSIGnSC CSIGnRYO CSIGnCTL1 CSIGnCKR CSIGnCFG0 CSIGnDAP 0 0 or 1 1 CSIGnCTL1 CSIGnCKR CSIGnCFG0 CSIGnDAP 0 1 or 1 0 Note n 0 1 CSIGnSC tS RY O CSIGnRYO CSIGnSC tS RY O CSIGnRYO ...

Page 1518: ... n 0 1 T Prescaler cycle time BRS Setting of URTHnCTL2 URTHnBRS 11 0 Item Symbol Conditions MIN MAX Unit UARTHn transfer rate 2 Mbps URTHnCTS setup time to URTHnTXD tASCTS Input URTHnCTS without noise filter 3T 30 ns URTHnCTS with noise filter 5T 30 ns URTHnRTS output delay time to URTHnRXD tASRTS Output URTHnRXD without noise filter 3BRS 2 T 30 ns URTHnRXD with noise filter 3BRS 4 T 30 ns URTHnTX...

Page 1519: ... Output 500 500 ns URTHnSC high level width tKWHM1 Output tKCYM1 2 20 tKCYM1 2 20 ns URTHnSC low level width tKWLM1 Output tKCYM1 2 20 tKCYM1 2 20 ns URTHnRXD setup time to URTHnSC tSRXDM1 Input T 30 3T 30 ns URTHnRXD hold time to URTHnSC tHRXDM1 Input 0 2T ns URTHnTXD output delay time to URTHnSC tDTXDM1 Output 10 10 ns URTHnTXD output hold time to URTHnSC tHTXDM1 Output tKCYM1 2 10 tKCYM1 2 10 n...

Page 1520: ...e tKCYS1 Input 500 500 ns URTHnSC high level width tKWHS1 Input 4T 20 4T 20 ns URTHnSC low level width tKWLS1 Input 4T 20 4T 20 ns URTHnRXD setup time to URTHnSC tSRXDS1 Input 10 10 ns URTHnRXD hold time to URTHnSC tHRXDS1 Input 2T 10 2T 10 ns URTHnTXD output delay time to URTHnSC tDTXDS1 Output 30 30 ns URTHnTXD output hold time to URTHnSC tHTXDS1 Output tKWHS1 10 tKWHS1 10 ns URTHnCTS setup time...

Page 1521: ...th tKWHS1 Input 4T 20 4T 20 ns URTHnSC low level width tKWLS1 Input 4T 20 4T 20 ns URTHnRXD setup time to URTHnSC tSRXDS1 Input 2T 10 2T 10 ns URTHnRXD hold time to URTHnSC tHRXDS1 Input 10 4T 10 ns URTHnTXD output delay time to URTHnSC tDTXDS1 Output 30 30 ns URTHnTXD output hold time to URTHnSC tHTXDS1 Output tKWHS1 10 tKWHS1 10 ns URTHnCTS setup time to URTHnTXD tSCTSS1 Input URTHnCTS without n...

Page 1522: ...7 2014 V850E2 PG4 L Section 27 Electrical Characteristics Note n 0 1 URTHnSC URTHnTXD URTHnRXD URTHnCTS URTHnRTS tKCYM1 tKCYS1 tKWLM1 tKWLS1 tKWHM1 tKWHS1 tDTXDM1 tDTXDS1 tHTXDM1 tHTXDS1 tSRXDM1 tSRXDS1 tHRXDM1 tHRXDS1 tSCTSM1 tSCTSS1 tDRTSM1 tDRTSS1 ...

Page 1523: ... cycle time tKCYM2 Output 500 500 ns URTHnSC high level width tKWHM2 Output tKCYM2 2 20 tKCYM2 2 20 ns URTHnSC low level width tKWLM2 Output tKCYM2 2 20 tKCYM2 2 20 ns URTHnRXD setup time to URTHnSC tSRXDM2 Input T 30 3T 30 ns URTHnRXD hold time to URTHnSC tHRXDM2 Input 0 2T ns URTHnTXD output delay time to URTHnSC tDTXDM2 Output 10 10 ns URTHnTXD output hold time to URTHnSC tHTXDM2 Output tKCYM2 ...

Page 1524: ...2 Rev 1 02 Page 1524 of 1538 Jul 17 2014 V850E2 PG4 L Section 27 Electrical Characteristics Note n 0 1 URTHnSC URTHnTXD URTHnRXD URTHnCTS URTHnRTS tKCYM2 tKWLM2 tKWHM2 tDTXDM2 tHTXDM2 tSRXDM2 tHRXDM2 tSCTSM2 tDRTSM2 ...

Page 1525: ...nal transmission delay tOUTPUT internal reception delay tINPUT Note 2 CAN base clock frequency fCAN Note n 0 1 Item Symbol Conditions MIN MAX Unit CAN transfer rate 1 Mbps CAN internal delay time 1 tnode 87 5 ns CAN base clock FCNnTX pin Transmit data tOUTPUT FCNnRX pin Received data tgate 2 tINPUT tgate tcycle tcycle Device CAN controller Internal reception delay FCNnTX pin FCNnRX pin Schematic v...

Page 1526: ...nit DCUTCK cycle time tTCKW 40 0 ns DCUTDI setup time to DCUTCK tTDIS tTCKW 2 8 5 ns DCUTMS setup time to DCUTCK tTMSS tTCKW 2 8 5 ns DCUTDI hold time to DCUTCK tTDIH 2 0 ns DCUTMS hold time to DCUTCK tTMSH 2 0 ns DCUTDO output delay time to DCUTCK tTDOD 20 0 ns DCUTRDY output delay time to DCUTCK tRDYD 20 0 ns DCUTRST low level width tTRSTWL 1000 ns DCUTCK DCUTDI DCUTMS DCUTDO DCUTRDY DCUTRST tTC...

Page 1527: ...ace Ta 40 to 125 C VDD EVDD OSCVDD 4 0 to 5 5 V AVDD0 4 2 to 5 5 V VSS EVSS OSCVSS AVSS0 0 V Item Symbol Conditions MIN MAX Unit Transfer rate tTCKW at 48 MHz operation 4 Mbps at 64 MHz operation 5 3 Mbps at 80 MHz operation 6 7 Mbps Rise time tR 0 4 V 2 0 V transition time 3 ns Fall time tF 2 0 V 0 4 V transition time 3 ns ...

Page 1528: ...curacy 1 TOE 2 0 LSB Conversion time tCONV 2 μs Zero scale error 1 ZSE 2 0 LSB Full scale error 1 FSE 2 0 LSB Sampling time tAS 2 clocks Analog input voltage VIAN AVREF0M AVREF0P V Differential non linearity error 1 DNL 2 0 LSB Integral non linearity error 1 INL 2 0 LSB AVREF0P input current AIREF1 0 7 1 5 mA AVDD0 current AIDD ADCA0GPS 1 ADCA0BPC 0 ADCA0DIAG 0 8 7 mA ADCA0GPS 1 ADCA0BPC 0 ADCA0DI...

Page 1529: ...old time tCHOLD 10 μs Zero scale error 1 ZSE 2 5 LSB Full scale error 1 FSE 3 0 LSB Sampling time tAS 2 clocks Channel S H sampling time tCAS 0 4 μs Analog input voltage VIAN 0 25 AVREF0P 0 25 V Differential non linearity error 1 DNL 2 5 LSB Integral non linearity error 1 INL 2 5 LSB AVREF0P input current AIREF1 0 7 1 5 mA AVDD0 current AIDD ADCA0GPS 1 ADCA0BPC 0 ADCA0DIAG 0 12 7 mA ADCA0GPS 1 ADC...

Page 1530: ... LSB AVDD0 4 2 to 5 5 V 6 0 LSB Full scale error 1 FSE AVDD0 4 5 to 5 5 V 5 0 LSB AVDD0 4 2 to 5 5 V 6 0 LSB Sampling time tAS 2 clocks Analog input voltage VIAN AVREF0M AVREF0P V Differential non linearity error 1 DNL AVDD0 4 5 to 5 5 V 3 5 LSB AVDD0 4 2 to 5 5 V 7 0 LSB Integral non linearity error 1 INL AVDD0 4 5 to 5 5 V 3 5 LSB AVDD0 4 2 to 5 5 V 7 0 LSB AVREF0P input current AIREF1 0 7 1 5 m...

Page 1531: ...VDD0 4 2 to 5 5 V 9 0 LSB Full scale error 1 FSE AVDD0 4 5 to 5 5 V 8 0 LSB AVDD0 4 2 to 5 5 V 9 0 LSB Sampling time tAS 2 clocks Channel S H sampling time tCAS 0 4 μs Analog input voltage VIAN 0 25 AVREF0P 0 25 V Differential non linearity error 1 DNL AVDD0 4 5 to 5 5 V 5 0 LSB AVDD0 4 2 to 5 5 V 6 0 LSB Integral non linearity error 1 INL AVDD0 4 5 to 5 5 V 5 0 LSB AVDD0 4 2 to 5 5 V 6 0 LSB AVRE...

Page 1532: ...d an electrolytic capacitor at a point in the source of the supply but wire the power supplies in isolation from each other on the board Insert a chip inductor at the point of entry for the analog power supply voltage In addition earth the analog ground digital ground and an electrolytic capacitor at a point in the source of the power supply but wire them in isolation from each other on the board ...

Page 1533: ...SCVSS AVSS0 0 V Note 1 Time period when the VDD voltage is equal to or less than the minimum value of the detected voltage Item Symbol Conditions MIN TYP MAX Unit Detected voltage VPOF 2 65 2 8 2 9 V Detection delay time Td_pof 2 0 ms Minimum detection width tPOFW 1 0 2 ms Voltage slope PVS1 At power on 0 18 V ms 1 8 V us PVS2 In normal operation 1 8 V s 1 8 V us VDD VPOF MAX VPOF TYP VPOF MIN tPO...

Page 1534: ...e Note 3 Time until LVI is detected in accord with the specification after enabling of the LVI function Item Symbol Conditions MIN TYP MAX Unit Detected voltage VLVI0 LVICNT LVICNT 1 0 01B 4 5 4 6 4 7 V VLVI1 LVICNT LVICNT 1 0 10B 4 2 4 3 4 4 V VLVI2 LVICNT LVICNT 1 0 11B 3 3 1 3 2 V Response time 1 tLD After EVDD reaches VLVI0 VLVI1 MAX After EVDD falls VLVI0 VLVI1 MIN 2 ms Minimum detection widt...

Page 1535: ...ting to a delivered product either erasing writing or writing alone is considered as a time of rewriting Example P writing E erasing Delivered product P E P E P 3 times Delivered product E P E P E P 3 times Note 2 Storage temperature Ta Tj 95 C Item Symbol Conditions MIN TYP MAX Unit Operating frequency fCPU 80 MHz Number of times rewritable per block 1 CERWR Code Flash Data are retained for 20 ye...

Page 1536: ...etup time to VDD tDP 1 ms RESET release to FLMD0 tPR tOSC Td_pof 0 5 tDP ms RESET FLMD0 set time tRP 1 ms FLMD0 pulse end time tRPE 11 ms FLMD0 high low level width tPW 10 100 μs FLMD0 rise time tR 20 ns FLMD0 fall time tF 20 ns Serial clock input frequency tSCCY 9 8 5000 KHz High level width tWHSC 85 50000 ns Low level width tWLSC 85 50000 ns FPDR setup time to FPCK tPLHSC 75 ns FPDR hold time to...

Page 1537: ...R01UH0336EJ0102 Rev 1 02 Page 1537 of 1538 Jul 17 2014 V850E2 PG4 L Section 27 Electrical Characteristics tSCCY FPCK FPDT FPDR tWLSC tDSC tPLHSC tPHLSC tWHSC ...

Page 1538: ...al Characteristics 27 6 19 Self Diagnosis BIST Execution Time Ta 40 to 125 C VDD EVDD OSCVDD 3 0 to 5 5 V AVDD0 4 2 to 5 5 V VSS EVSS OSCVSS AVSS0 0 V Item Symbol Condition 1 Condition 2 MIN TYP MAX Unit Self diagnosis BIST execution time fxx 48 MHz 69 ms fxx 64 MHz 52 ms fxx 80 MHz 41 ms ...

Page 1539: ...er than Port Pins 1 2 Section 3 CPU System Function p 115 116 Modification of Table 3 2 PPU Protected Areas and Modules Section 4 Interrupt Functions p 143 Modification of notes 1 and 2 for Table 4 2 List of Interrupt Sources p 144 Correction of address in 4 3 Interrupt Controller Control Registers p 167 Modification of description in 4 3 11 INTSTR0B Error Interrupt Source Storage Register p 169 C...

Page 1540: ...90 Correction of description of WDTA trigger in 12 4 2 1 WDTA Enable Register Section 13 Timer Array Unit B TAUB p 392 Correction of Table 13 2 Register Base Address TAUBn_base p 590 Correction of description in 13 21 2 1 TAUBnTPS p 594 Correction of address in 13 21 3 1 TAUBnCDRm p 603 604 612 Correction of description in Tables 13 129 13 130 13 132 and 13 144 Section 14 Timer Array Unit J TAUJ p...

Page 1541: ...fication of description in Table 22 24 URTHnETX Register Contents p 1233 Addition of Table 22 26 Accesses according to Transmission Modes p 1234 Modification of description in Table 22 27 IC0REG0 Register Contents Section 23 A D Converter p 1267 Addition of Figure 23 1 ADCAn Block Diagram p 1270 Modification of description in 23 3 1 Basic Operation p 1279 Addition of caution to 23 3 6 Stopping A D...

Page 1542: ...ion 1 00 Mar 29 2013 Section 1 Introduction pp 25 26 Correction of 1 3 List of Functions p 34 Correction of 1 7 1 Internal Block Diagram Section 2 Port Functions p 62 Modification of steps 2 to 4 in 4 Sequence for Writing to a Protected Port Register p 74 Correction of FLMD0 pin handling p 79 Deletion of JP0_0 p 108 Addition of DNFAnENL to Table 2 53 The List of Registers for the Digital Noise Can...

Page 1543: ...n of signal names p 427 Modification of Note in 13 10 TAUBnTTOUTm Output and INTTAUBnIm Generation when Counter Starts or Restarts p 429 Addition of Caution to 13 11 TAUBnTTINm Edge Detection Deletion of a figure Forced Restart Operation p 455 462 469 507 Modification of initial channel settings in Table 13 31 Table 13 36 Table 13 40 and Table 13 66 p 457 Correction of Figure 13 33 TAUBnCMORm TAUB...

Page 1544: ...on of title Table 14 43 Control Bit Settings in Synchronous Channel Output Mode 1 Section 15 TSG2 TSG20 p 735 Correction of bit 4 in Table 15 14 TSnIOC1 Register Contents 1 2 p 777 Correction of register names in Table 15 40 Active Width Setting in SP PWM Mode p 788 Correction of INTTSG2nI11 in Table 15 44 List of Interrupts in Each Mode 3 5 p 896 Correction of signal names in Figure 15 79 and Fig...

Page 1545: ...nMmCTL Read p 1097 Deletion of description in 20 6 2 3 Redefining Message Buffer during Transmission p 1098 Modification of Figure 20 4 Setting Transmission Request to Transmit Message Buffer after Redefinition p 1101 Modification of Figure 20 6 Reception Timing pp 1102 1103 Modification of 20 7 3 Receive History List Function p 1104 Modification of 20 7 4 Mask Function p 1111 Modification of Note...

Page 1546: ... ADCAn Registers 1 2 p 1312 Correction of bits 9 to 8 in Table 23 8 ADCAnCTL1 Register Contents 2 2 p 1325 Deletion of Note for Table 23 22 ADCAnLCR Register Contents p 1329 Addition of Note 1 for Table 23 24 ADCAnDBiCR Register Contents p 1330 Correction of Note 2 for Table 23 25 ADCAnDBiCRL Register Contents p 1341 Correction of pin names in 23 5 4 2 b c p 1342 Modification of Note in Figure 23 ...

Page 1547: ...n of 25 2 2 LPD I F p 1480 1483 Addition and correction of description to 25 3 Notes on On Chip Debugging Section 27 Electrical Specification Throughout Correction of value of AVDD0 p 1485 Modification of 27 1 Absolute Maximum Ratings pp 1489 1491 Modification of 27 5 DC Characteristics p 1496 Correction of pin name in timing chart p 1497 Modification of 27 6 4 Regulator Characteristics p 1502 Mod...

Page 1548: ...e 13 8 Simultaneous Rewrite Methods and Trigger Timing corrected 411 Table 13 9 Simultaneous Rewrite and Trigger Timing added Note 417 13 7 4 2 Simultaneous rewrite at the peak of a triangular cycle of master channel method B and Figure 13 6 Simultaneous Rewrite at the Peak of a Triangular Cycle of Master Channel corrected the titles 419 Figure 13 7 Simultaneous Rewrite When INTTAUBnIm Is Generate...

Page 1549: ... One Shot Pulse Output Function corrected 559 Figure 13 79 Block Diagram of Triangle PWM Output Function corrected 571 Figure 13 83 Block Diagram of Triangle PWM Output Function with Dead Time corrected 573 Figure 13 84 General Timing Diagram of Triangle PWM Output Function with Dead Time corrected 575 Table 13 111 Simultaneous Rewrite for Master Channels of Triangle PWM Output Function with Dead ...

Page 1550: ...top and Restart corrected 704 Table 14 51 TAUJnCNTm Read Values after Counter Is Re enabled corrected 708 Table 14 52 Description of TAUJnCMORm Register 4 4 corrected 710 Table 14 54 Description of TAUJnCSRm Register corrected 717 Table 14 66 Description of TAUJnRDT Register added description Section 15 TSG2 TSG20 722 to 723 Table 15 6 TSG2n Registers corrected 734 Table 15 12 TSnCTL6 Register Con...

Page 1551: ...4 Settings for the ENCAnCCR1 Register corrected Section 19 Timer Option Module TAPA 1018 Table 19 6 Contents of the PIC0HIZCEN0 Register changed Caution 2 1019 Table 19 7 Contents of the PIC0HIZCEN2 Register changed Caution 2 1024 Table 19 10 Contents of the TAPAnCTL0 Register corrected 1035 Figure 19 2 Operation of TAPAnTHZOUT0 when TAPAnDCM 1 TAPAnDCP 1 and TAPAnDCN 0 corrected 1036 19 4 2 4 Ope...

Page 1552: ... 23 3 11 3 Diagnosis of Analog Input Pins changed Note 1 1304 23 3 11 4 Diagnosis of Channel Sample and Hold Circuit Step 2 corrected 1311 Figure 23 20 A D Conversion Timing when Buffer Amplifier Function is Enabled corrected 1314 23 4 2 1 ADCAnCTL0 Access added description 1315 Table 23 7 ADCAnCTL0 Register Contents 2 2 added description 1316 23 4 2 2 ADCAnCTL1 Access added description 1320 23 4 ...

Page 1553: ... Setting Flow for Encoder Capture Operation by INTTAUB0Im added 1431 Table 24 31 PIC Setting Using INTTAUB0Im added Section 27 Electrical Characteristics 1495 27 2 Capacity changed 1505 27 6 3 Timing in Turning the Power Supply On and Off changed figure 1515 27 6 10 b Slave Mode changed 1536 to 1537 27 6 18 FLMD0 Pulse Timing Characteristics changed 1 02 Jul 18 2014 Section 27 Electrical Character...

Page 1554: ...V850E2 PG4 L User s Manual Hardware Publication Date Rev 0 01 Mar 29 2012 Rev 1 02 Jul 17 2014 Published by Renesas Electronics Corporation Colophon ...

Page 1555: ...td Unit 301 Tower A Central Towers 555 Langao Road Putuo District Shanghai P R China 200333 Tel 86 21 2226 0888 Fax 86 21 2226 0999 Renesas Electronics Hong Kong Limited Unit 1601 1613 16 F Tower 2 Grand Century Place 193 Prince Edward Road West Mongkok Kowloon Hong Kong Tel 852 2265 6688 Fax 852 2886 9022 9044 Renesas Electronics Taiwan Co Ltd 13F No 363 Fu Shing North Road Taipei 10543 Taiwan Te...

Page 1556: ...V850E2 PG4 L R01UH0336EJ0102 Back Cover ...

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