2-70
The following diagram shows the output phases. (The phases are the same for both absolute and incre-
mental encoders.)
Forward Rotation Side
Phase A
Phase B
Phase Z
Phase A
Phase B
Phase Z
Reverse Rotation Side
Note
Phase Z is synchronous with phase A, but the pulse width may be less than for phase A.
D
Alarm Code Outputs 1 to 3 (37: ALO1; 38: AL02; 39: ALO3)
When a Servo Driver error is detected, the contents of the error are output in 3-bit code. The alarm code
output ground common is CN1 pin 1 (GND). For details, refer to
5-2 Alarms
.
D
Alarm Output (31: ALM)
Alarm Output Ground (32: ALMCOM)
When the Servo Driver detects an error, outputs are turned OFF. At that time, an alarm code is output
according to the contents of the error. This output is OFF at the time of powering up, and turns ON when
the initial processing is completed.
D
Positioning Completed Output 1 (25: INP1)
Positioning Completed Output 1 Common (26: INP1COM)
Positioning Completed Output 2 (Not Allocated: INP2)
The INP1 signal turns ON when the number of accumulated pulses in the deviation counter is less than
Pn500 (positioning completed range 1). The INP2 signal turns ON when the number of pulses is less
than Pn504 (positioning completed range 2). These signals are always OFF when the control mode is
any mode other than the position control mode.
Note 1.
These are the default allocations. The INP1 signal is allocated by Pn50E.0, and the INP2 sig-
nal is allocated by Pn510.0.
Note 2.
With the default allocations, INP1 (enabled for position control) and VCMP (enabled for speed
control) are allocated to CN1 pins 25 and 26.
D
Speed Conformity Output (25: VCMP)
Speed Conformity Output Common (26: VCMPCOM)
The VCMP signal turns ON when the difference between the speed command and the Servomotor rota-
tion speed is equal to or less than the value set for Pn503 (speed conformity signal output width). For
example, if the speed command is for 3,000 r/min and the set value is for 50 r/min, it turns ON when the
rotation speed is between 2,950 and 3,050 r/min. This signal is always OFF when the control mode is
any mode other than the speed control mode.
Note 1.
These are the default allocations. The VCMP signal is allocated by Pn50E.1.
Note 2.
With the default allocations, INP1 (enabled for position control) and VCMP (enabled for speed
control) are allocated to CN1 pins 25 and 26.
Standard Models and Specifications
Chapter 2
AUDIN - 7 bis rue de Tinqueux - 51100 Reims - France - Tel : 03.26.04.20.21 - Fax : 03.26.04.28.20 - Web : http: www.audin.fr - Email : [email protected]
