LSI LSI53C896, Technical Manual

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IX-8 Index
normal/fast memory ( 128 Kbytes) (Cont.)
single byte access read cycle 6-46
single byte access write cycle 6-48
O
opcode 5-10 , 5-15 , 5-23 , 5-27
fetch burst capability 2-25
operating conditions 6-2
operating register/SCRIPTS RAM read
32-bits 6-18
64-bits 6-19
operating register/SCRIPTS RAM write
32-bits 6-20
64-bits 6-21
operator 5-23
output
current as a function of output voltage 6-11
output signals 6-5 , 6-7
P
PAR 3-6
PAR64 3-7
parallel ROM interface 2-56
parallel ROM support 2-57
parity 2-29 , 3-6
error 3-9
(PAR) 4-81
options 2-27
parity64 3-7
PCI
addressing 2-3
bus commands and encoding types 2-5
bus commands and functions supported 2-4
cache line size register 2-9
cache mode 2-11
command register 2-9
commands 2-4
configuration info enable (PCICIE) 4-56
configuration register read 6-16
configuration register write 6-17
configuration registers 4-1
configuration space 2-3
external memory interface timing diagrams 6-14
functional description 2-2
I/O space 2-3
interface signals 3-5
master transaction 2-12
master transfer 2-12
memory space 2-4
performance 1-7
target disconnect 2-10
target retry 2-10
PERR/ 3-9
phase mismatch
handling in SCRIPTS 2-20
jump address 1 (PMJAD1) 4-111
jump address 2 (PMJAD2) 4-111
jump registers 4-111
physical dword address and data 3-6
PME
clock (PMEC) 4-17
enable (PEN) 4-18
status (PST) 4-17
support (PMES) 4-16
polling 2-43
power
and ground signals 3-21
management 2-59
capabilities 4-16
control/status 4-17
state (PWS[1:0]) 4-18
state D0 2-60
state D1 2-61
state D2 2-61
state D3 2-61
prefetch
enable (PFEN) 4-73
flush 2-25
flush (PFF) 4-73
SCRIPTS instructions 2-24
pull-ups, internal, conditions 3-4
R
RAM, see also SCRIPTS RAM 2-21
RBIAS 3-21
read
line 2-11 , 2-12
line function 2-8
modify-write cycles 5-24
multiple 2-9 , 2-11 , 2-12
multiple with read line enabled 2-9
write instructions 5-23
write system memory from SCRIPTS 5-35
read/write
instructions 5-23 , 5-25
system memory from SCRIPTS 5-35
received
master abort (from master) (RMA) 4-5
target abort (from master) (RTA) 4-5
register
address 5-39
address - A[6:0] 5-23
register map A-1
registers 2-43
relative 5-20
relative addressing mode 5-19 , 5-30
remaining byte count (RBC) 4-112
REQ/ 2-11 , 3-8
REQ/ - GNT/ 2-2
REQ64/ 3-7
request 3-8
request 64 3-7
reselect 2-20
during reselection 2-40
instruction 5-15
reselected (RSL) 2-46 , 4-76 , 4-80
reserved command 2-6
reset 3-5
input 6-13
SCSI offset (ROF) 4-95
response ID one (RESPID1) 4-91
response ID zero (RESPID0) 4-91
return instruction 5-28
revision ID register 4-6
(RID) 4-6
rise and fall time test condition 6-9
ROM
interface 2-56
pin 2-57
RST/ 3-5
*