LSI LSI53C896, Technical Manual

Page: 218 / 370

4-106 Registers
enabled by setting the PCI Configuration Info Enable bit
in the
Chip Test Two (CTEST2) register. If this bit is set,
the Scratch Register B (SCRATCHB) returns bits [31:13]
of the SCRIPTS RAM PCI Base Address Register Two
(SCRIPTS RAM) in bits [31:13] of the SCRATCH B
register when read. When read, bits [12:0] of
SCRATCH B will always return zeros in this mode. Writes
to the SCRATCH B register are unaffected. Resetting the
PCI Configuration Info Enable bit causes the
SCRATCH B register to return to normal operation.
Registers: 0x60–0x9F
Scratch Registers C–R (SCRATCHC–SCRATCHR)
Read/Write
These are general purpose user definable scratch pad registers. Apart
from CPU access, only register read/write, memory moves and
Load/Stores directed at a SCRATCH register will alter its contents. The
power-up values are indeterminate.
*