LSI LSI53C896, Technical Manual

Page: 161 / 370

SCSI Registers 4-49
SDP1 SCSI SDP1 Parity Signal 0
This bit represents the present state of the SCSI SDP1/
parity signal. It is unlatched and may change as it is read.
Registers: 0x10–0x13
Data Structure Address (DSA)
Read/Write
DSA Data Structure Address [31:0]
This 32-bit register contains the base address used for all
table indirect calculations. The DSA register is usually
loaded prior to starting an I/O, but it is possible for a
SCRIPTS Memory Move to load the DSA during the I/O.
During any Memory-to-Memory Move operation, the
contents of this register is preserved. The power-up value
of this register is indeterminate.
Register: 0x14
Interrupt Status Zero (ISTAT0)
Read/Write
This is the only register that is accessible by the host CPU while a
LSI53C896 SCSI function is executing SCRIPTS (without interfering in
the operation of the function). It is used to poll for interrupts if hardware
interrupts are disabled. Read this register after servicing an interrupt to
check for stacked interrupts.
ABRT Aborted 7
Setting this bit aborts the current operation under
execution by the LSI53C896 SCSI function. If this bit is
set and an interrupt is received, clear this bit before
reading the
DMA Status (DSTAT) register to prevent
further aborted interrupts from being generated. The
sequence to abort any operation is:
31 0
DSA
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
7 6 5 4 3 2 1 0
ABRT SRST SIGP SEM CON INTF SIP DIP
0 0 0 0 0 0 0 0
*