LSI LSI53C896, Technical Manual

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xii Contents
6.26 External Memory Write 6-44
6.27 Normal/Fast Memory (
≥
128 Kbytes) Single Byte
Access Read Cycle 6-46
6.28 Normal/Fast Memory (
≥
128 Kbytes) Single Byte
Access Write Cycle 6-48
6.29 Normal/Fast Memory (
≥
128 Kbytes) Multiple Byte
Access Read Cycle 6-50
6.30 Normal/Fast Memory (
≥
128 Kbytes) Multiple Byte
Access Write Cycle 6-52
6.31 Slow Memory (
≥
128 Kbytes) Read Cycle 6-54
6.32 Slow Memory (
≥
128 Kbytes) Write Cycle 6-56
6.33
≤
64 Kbytes ROM Read Cycle 6-58
6.34
≤
64 Kbytes ROM Write Cycle 6-59
6.35 Initiator Asynchronous Send 6-60
6.36 Initiator Asynchronous Receive 6-61
6.37 Target Asynchronous Send 6-61
6.38 Target Asynchronous Receive 6-62
6.39 Initiator and Target Synchronous Transfer 6-66
6.40 LSI53C896 329 BGA (Bottom View) 6-70
6.41 LSI53C896 329 BGA Mechanical Drawing 6-71
B.1 16 Kbyte Interface with 200 ns Memory B-1
B.2 64 Kbyte Interface with 150 ns Memory B-2
B.3 128, 256, 512 Kbyte or 1 Mbyte Interface with
150 ns Memory
B-3
B.4 512 Kbyte Interface with 150 ns Memory B-4
Tables
2.1 PCI Bus Commands and Encoding Types for the
LSI53C896
2-5
2.2 PCI Cache Mode Alignment 2-14
2.3 Bits Used for Parity Control and Generation 2-28
2.4 SCSI Parity Control 2-29
2.5 SCSI Parity Errors and Interrupts 2-29
2.6 HVD Signals 2-36
2.7 Parallel ROM Support 2-57
2.8 Mode A Serial EEPROM Data Format 2-59
2.9 Power States 2-60
3.1 LSI53C896 Internal Pull-ups and Pull-downs 3-4
*