SCSI Timing Diagrams
6-61
Figure 6.36 Initiator Asynchronous Receive
Figure 6.37 Target Asynchronous Send
Table 6.40
Initiator Asynchronous Receive
Symbol
Parameter
Min
Max
Units
t
1
SACK/ asserted from SREQ/ asserted
5
–
ns
t
2
SACK/ deasserted from SREQ/ deasserted
5
–
ns
t
3
Data setup to SREQ/ asserted
0
–
ns
t
4
Data hold from SACK/ asserted
0
–
ns
Valid n
Valid n + 1
n + 1
n + 1
n
n
t
1
t
2
t
3
t
4
SREQ/
SACK/
SD[15:0]/,
SDP[1:0]/
Table 6.41
Target Asynchronous Send
Symbol
Parameter
Min
Max
Units
t
1
SREQ/ deasserted from SACK/ asserted
5
–
ns
t
2
SREQ/ asserted from SACK/ deasserted
5
–
ns
t
3
Data setup to SREQ/ asserted
55
–
ns
t
4
Data hold from SACK/ asserted
20
–
ns
Valid n
Valid n + 1
n + 1
n + 1
n
n
t
1
t
2
t
3
t
4
SREQ/
SACK/
SD[15:0]/,
SDP[1:0]/
*
Summary of Contents for LSI53C896
Page 6: ...vi Preface...
Page 16: ...xvi Contents...
Page 88: ...2 62 Functional Description...
Page 112: ...3 24 Signal Descriptions...
Page 306: ...6 38 Specifications This page intentionally left blank...
Page 310: ...6 42 Specifications This page intentionally left blank...
Page 338: ...6 70 Specifications Figure 6 40 LSI53C896 329 BGA Bottom View...
Page 340: ...6 72 Specifications...
Page 346: ...A 6 Register Summary...
Page 362: ...IX 12 Index...