LSI LSI53C896, Technical Manual

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2-56 Functional Description
Move instruction is used, if the WSS bit is set at the start of a data send
command, the first byte of the data send command is assumed to be the
high-order byte and is “married” with the low-order byte stored in the
lower byte of the SODL register before the two bytes are sent across the
SCSI bus. For “N” consecutive wide data send Block Move commands,
the first through the (N
th
−
1) Block Move instructions should be Chained
Block Moves.
2.3 Parallel ROM Interface
The LSI53C896 supports up to one megabyte of external memory in
binary increments from 16 Kbytes to allow the use of expansion ROM for
add-in PCI cards. Both functions of the device share the ROM interface.
This interface is designed for low speed operations such as downloading
instruction code from ROM. It is not intended for dynamic activities such
as executing instructions.
System requirements include the LSI53C896, two or three external
8-bit address holding registers (HCT273 or HCT374), and the
appropriate memory device. The 4.7 k
Ω
pull-up resistors on the MAD bus
require HC or HCT external components to be used. If in-system Flash
ROM updates are required, a 7406 (high voltage open collector inverter),
a MTD4P05, and several passive components are also needed. The
memory size and speed is determined by pull-up resistors on the
8-bit bidirectional memory bus at power-up. The LSI53C896 senses this
bus shortly after the release of the Reset signal and configures the
Expansion ROM Base Address register and the memory cycle state
machines for the appropriate conditions.
The external memory interface works with a variety of ROM sizes and
speeds. An example set of interface drawings is in
Appendix B, “External
Memory Interface Diagram Examples.”
The LSI53C896 supports a variety of sizes and speeds of expansion
ROM, using pull-down resistors on the MAD[3:0] pins. The encoding of
pins MAD[3:1] allows the user to define how much external memory is
*