SCSI Registers
4-105
Registers: 0x58–0x59
SCSI Bus Data Lines (SBDL)
Read Only
SBDL
SCSI Bus Data Lines
[15:0]
This register contains the SCSI data bus status. Even
though the SCSI data bus is active LOW, these bits are
active HIGH. The signal status is not latched and is a true
representation of exactly what is on the data bus at the
time the register is read. This register is used when
receiving data using programmed I/O. This register can
also be used for diagnostic testing or in the low level
mode. The power-up value of this register is
indeterminate.
If the chip is in the wide mode (
, bit 3 and
, bit 2 are
set) and
is read, both byte
lanes are checked for parity regardless of phase. When
in a nondata phase, this will cause a parity error interrupt
to be generated because upper byte lane parity is invalid.
Registers: 0x5A–0x5B
Reserved
Registers: 0x5C–0x5F
Scratch Register B (SCRATCHB)
Read/Write
SCRATCHB
Scratch Register B
[31:0]
This is a general purpose user definable scratch pad
register. Apart from CPU access, only register read/write
and memory moves directed at the SCRATCH register
will alter its contents. The power-up values are
indeterminate. A special mode of this register can be
15
0
SBDL
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
31
0
SCRATCHB
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
*
Summary of Contents for LSI53C896
Page 6: ...vi Preface...
Page 16: ...xvi Contents...
Page 88: ...2 62 Functional Description...
Page 112: ...3 24 Signal Descriptions...
Page 306: ...6 38 Specifications This page intentionally left blank...
Page 310: ...6 42 Specifications This page intentionally left blank...
Page 338: ...6 70 Specifications Figure 6 40 LSI53C896 329 BGA Bottom View...
Page 340: ...6 72 Specifications...
Page 346: ...A 6 Register Summary...
Page 362: ...IX 12 Index...
