LSI LSI53C896, Technical Manual

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5-38 SCSI SCRIPTS Instruction Set
A maximum of 4 bytes may be moved with these instructions. The
register address and memory address must have the same byte
alignment, and the count set such that it does not cross Dword
boundaries. The memory address may not map back to the chip,
excluding RAM and ROM. If it does, a PCI read/write cycle occurs (the
data does not actually transfer to/from the chip), and the chip issues an
interrupt (Illegal Instruction Detected) immediately following.
The SIOM and DIOM bits in the DMA Mode (DMODE) register determine
whether the destination or source address of the instruction is in Memory
space or I/O space, as illustrated in the following table. The Load/Store
utilizes the PCI commands for I/O read and I/O write to access the I/O
space.
5.7.1 First Dword
Figure 5.15 Load/Store Instruction - First Dword
IT[2:0] Instruction Type [31:29]
These bits should be 0b111, indicating the Load/Store
instruction.
Bits A1, A0 Number of Bytes Allowed to Load/Store
00 One, two, three or four
01 One, two, or three
10 One or two
11 One
Bit Source Destination
SIOM (Load) Memory Register
DIOM (Store) Register Memory
31 29 28 27 26 25 24 23 16 15 3 2 0
DCMD Register DBC Register
IT[2:0] DSA R NF LS A[7:0] R BC
*