LSI LSI53C896, Technical Manual

Page: 47 / 370

SCSI Functional Description 2-21
Storing the appropriate information to later restart the I/O can be done
through SCRIPTS, eliminating the need for processor intervention during
an I/O disconnect/reselect sequence. Calculations are performed such
that the appropriate information is available to SCRIPTS so that an I/O
state can be properly stored for restart later.
The Phase Mismatch Jump logic powers up disabled and must be
enabled by setting the Phase Mismatch Jump Enable bit (ENPMJ, bit 7
in the
Chip Control 0 (CCNTL0) register).
Utilizing the information supplied in the Phase Mismatch Jump Address
1 (PMJAD1) and Phase Mismatch Jump Address 2 (PMJAD2) registers,
described in Chapter 4, “Registers,” allows all overhead involved in a
disconnect/reselect sequence to be handled with a modest amount of
SCRIPTS instructions.
2.2.2 Internal SCRIPTS RAM
The LSI53C896 has 8 Kbytes (2048 x 32 bits) of internal, general
purpose RAM for each SCSI function. The RAM is designed for
SCRIPTS program storage, but is not limited to this type of information.
When the chip fetches SCRIPTS instructions or Table Indirect information
from the internal RAM, these fetches remain internal to the chip and do
not use the PCI bus. Other types of access to the RAM by the chip,
except Load/Store, use the PCI bus as if they were external accesses.
The SCRIPTS RAM powers up enabled by default.
The RAM can be relocated by the PCI system BIOS anywhere in the
64-bit address space.
Base Address Register Two (SCRIPTS RAM) in
the PCI configuration space contains the base address of the internal
RAM. To simplify loading of the SCRIPTS instructions, the base address
of the RAM appears in the
Scratch Register B (SCRATCHB) register
when bit 3 of the Chip Test Two (CTEST2) register is set. The upper
32 bits of a 64-bit base address will be in the SCRIPTS Fetch Selector
(SFS) register. The RAM is byte accessible from the PCI bus and is
visible to any bus mastering device on the bus. External accesses to the
RAM (by the CPU) follow the same timing sequence as a standard slave
register access, except that the required target wait-states drop from
5 to 3.
*