LSI LSI53C896, Technical Manual

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LSI53C896 PCI to Dual Channel Ultra2 SCSI Multifunction Controller 4-1
Chapter 4
Registers
This section contains descriptions of all LSI53C896 registers. The term
“set” is used to refer to bits that are programmed to a binary one.
Similarly, the term “cleared” is used to refer to bits that are programmed
to a binary zero. Write any bits marked as reserved to zero; mask all
information read from them. Reserved bit functions may change at any
time. Unless otherwise indicated, all bits in the registers are active HIGH,
that is, the feature is enabled by setting the bit. The bottom row of every
register diagram shows the default register values, which are enabled
after the chip is powered on or reset.
This chapter contains the following sections:
•
Section 4.1, “PCI Configuration Registers”
•
Section 4.2, “SCSI Registers”
•
Section 4.3, “64-Bit SCRIPTS Selectors”
•
Section 4.4, “Phase Mismatch Jump Registers”
4.1 PCI Configuration Registers
The PCI Configuration registers are accessed by performing a
configuration read/write to the device with its IDSEL pin asserted and the
appropriate value in AD[10:8] during the address phase of the
transaction. SCSI Function A is identified by a binary value of 0b000, and
SCSI Function B by a value of 0b001. Each SCSI function contains the
same register set with identical default values, except the
Interrupt Pin
register.
Table 4.1 shows the PCI configuration registers implemented in the
LSI53C896.
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