LSI LSI53C896, Technical Manual

Page: 213 / 370

SCSI Registers 4-101
Registers: 0x54–0x55
SCSI Output Data Latch (SODL)
Read/Write
SODL SCSI Output Data Latch [15:0]
This register is used primarily for diagnostic testing or
programmed I/O operation. Data written to this register is
asserted onto the SCSI data bus by setting the Assert
Data Bus bit in the
SCSI Control One (SCNTL1) register.
This register is used to send data using programmed I/O.
Data flows through this register when sending data in any
mode. It is also used to write to the synchronous data
FIFO when testing the chip. The power-up value of this
register is indeterminate.
Register: 0x56
Chip Control 0 (CCNTL0)
Read/Write
ENPMJ Enable Phase Mismatch Jump 7
Upon setting this bit, any phase mismatches do not
interrupt but force a jump to an alternate location to
handle the phase mismatch. Prior to actually taking the
jump, the appropriate remaining byte counts and
addresses will be calculated such that they can be easily
stored to the appropriate memory location with the
SCRIPTS Store instruction.
In the case of a SCSI send, any data in the part will be
automatically cleared after being accounted for. In the
case of a SCSI receive, all data will be flushed out of the
part and accounted for prior to taking the jump. This
feature does not cover, however, the byte that may
appear in
SCSI Wide Residue (SWIDE) . This byte must
be flushed manually.
15 0
SODL
x x x x x x x x x x x x x x x x
7 6 5 4 3 2 1 0
ENPMJ PMJCTL ENNDJ DISFC R DILS DPR
0 0 0 0 x x 0 0
*