LSI LSI53C896, Technical Manual

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PCI Configuration Registers 4-3
Registers: 0x02–0x03
Device ID
Read Only
DID Device ID [15:0]
This 16-bit register identifies the particular device. The
LSI53C896 Device ID is 0x000B.
Registers: 0x04–0x05
Command
Read/Write
The Command register provides coarse control over a device’s ability to
generate and respond to PCI cycles. When a zero is written to this
register, the LSI53C896 is logically disconnected from the PCI bus for all
accesses except configuration accesses.
R Reserved [15:9]
SE SERR/ Enable 8
This bit enables the SERR/ driver. SERR/ is disabled
when this bit is cleared. The default value of this bit is
zero. This bit and bit 6 must be set to report address
parity errors.
R Reserved 7
EPER Enable Parity Error Response 6
This bit allows the LSI53C896 to detect parity errors on
the PCI bus and report these errors to the system. Only
data parity checking is enabled and disabled with this bit.
The LSI53C896 always generates parity for the PCI bus.
15 0
DID
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
15 9 8 7 6 5 4 3 2 1 0
R SE R EPER R WIE R EBM EMS EIS
x x x x x x x 0 x 0 x 0 x 0 0 0
*