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PCI Configuration Registers
4-13
like the
Base Address Register Zero (I/O)
and
registers, except that
the encoding of the bits is different. The upper 21 bits
correspond to the upper 21 bits of the expansion ROM
base address.
The expansion ROM Enable bit, bit 0, is the only bit
defined in this register. This bit is used to control whether
or not the device accepts accesses to its expansion
ROM. When the bit is set, address decoding is enabled,
and a device is used with or without an expansion ROM
depending on the system configuration. To access the
external memory interface, also set the Memory Space
bit in the
register.
The host system detects the size of the external memory
by first writing the
register
with all ones and then reading back the register. The
SCSI functions of the LSI53C896 respond with zeros in
all don’t care locations. The ones in the remaining bits
represent the binary version of the external memory size.
For example, to indicate an external memory size of
32 Kbytes, this register, when written with ones and read
back, returns ones in the upper 17 bits.
The size of the external memory is set through MAD[3:1].
Please see
Section 3.7, “MAD Bus Programming,”
for the
possible size encodings available.
Register: 0x34
Capabilities Pointer
Read Only
CP
Capabilities Pointer
[7:0]
This register indicates that the first extended capability
register is located at offset 0x40 in the PCI Configuration.
Registers: 0x35–0x3B
Reserved
7
0
CP
0
1
0
0
0
0
0
0
*
Summary of Contents for LSI53C896
Page 6: ...vi Preface...
Page 16: ...xvi Contents...
Page 88: ...2 62 Functional Description...
Page 112: ...3 24 Signal Descriptions...
Page 306: ...6 38 Specifications This page intentionally left blank...
Page 310: ...6 42 Specifications This page intentionally left blank...
Page 338: ...6 70 Specifications Figure 6 40 LSI53C896 329 BGA Bottom View...
Page 340: ...6 72 Specifications...
Page 346: ...A 6 Register Summary...
Page 362: ...IX 12 Index...