LSI LSI53C896, Technical Manual

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SCSI Registers 4-41
MSG Assert SCSI MSG/ Signal 2
C_D Assert SCSI C_D/ Signal 1
I_O Assert SCSI I_O/ Signal 0
This register returns the SCSI control line status. A bit is set when the
corresponding SCSI control line is asserted. These bits are not latched;
they are a true representation of what is on the SCSI bus at the time the
register is read. The resulting read data is synchronized before being
presented to the PCI bus to prevent parity errors from being passed to
the system. This register is used for diagnostic testing or operation in the
low level mode.
Register: 0x0C
DMA Status (DSTAT)
Read Only
Reading this register clears any bits that are set at the time the register
is read, but does not necessarily clear the register in case additional
interrupts are pending (the LSI53C896 SCSI functions stack interrupts).
The DIP bit in the
Interrupt Status Zero (ISTAT0) register is also cleared.
It is possible to mask DMA interrupt conditions individually through the
DMA Interrupt Enable (DIEN) register.
When performing consecutive 8-bit reads of the DMA Status (DSTAT) ,
SCSI Interrupt Status Zero (SIST0) and SCSI Interrupt Status One
(SIST1) registers (in any order), insert a delay equivalent to 12 CLK
periods between the reads to ensure that the interrupts clear properly.
See
Chapter 2, “Functional Description,” for more information on
interrupts.
DFE DMA FIFO Empty 7
This status bit is set when the DMA FIFO is empty. It is
possible to use it to determine if any data resides in the
FIFO when an error occurs and an interrupt is generated.
This bit is a pure status bit and does not cause an
interrupt.
7 6 5 4 3 2 1 0
DFE MDPE BF ABRT SSI SIR R IID
1 0 0 0 0 0 x 0
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