LSI LSI53C896, Technical Manual

Page: 224 / 370

4-112 Registers
state of the PMJCTL bit this address will either be used
during an inbound (data in, status, message in) phase
mismatch (PMJCTL = 0) or when the WSR bit is set
(PMJCTL = 1). It should be loaded with an address of a
SCRIPTS routine that will handle the updating of memory
data structures of the BMOV that was executing when the
phase mismatch occurred.
Registers: 0xC8–0xCB
Remaining Byte Count (RBC)
Read/Write
RBC Remaining Byte Count (RBC) [31:0]
This register contains the byte count that remains for the
BMOV that was executing when the phase mismatch
occurred. In the case of direct or indirect BMOV
instructions, the upper byte of this register will also
contain the opcode of the BMOV that was executing. In
the case of a table indirect BMOV instruction, the upper
byte will contain the upper byte of the table indirect entry
that was fetched.
In the case of a SCSI data receive, this byte count will
reflect all data received from the SCSI bus, including any
byte in
SCSI Wide Residue (SWIDE) . There will be no
data remaining in the part that must be flushed to
memory with the exception of a possible byte in the
SWIDE register. That byte must be flushed to memory
manually in SCRIPTS.
In the case of a SCSI data send, this byte count will
reflect all data sent out onto the SCSI bus. Any data left
in the part from the phase mismatch will be ignored and
automatically cleared from the FIFOs.
31 0
RBC
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
*