LSI LSI53C896, Technical Manual

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LSI53C896 Benefits Summary 1-7
•
Performs complex bus sequences without interrupts, including
restoring data pointers.
•
Reduces ISR overhead through a unique interrupt status reporting
method.
•
Load/Store SCRIPTS instructions increase performance of data
transfers to and from the chip registers without using PCI cycles.
•
SCRIPTS support of 64-bit addressing.
•
Supports target disconnect and later reconnect with no interrupt to
the system processor.
•
Supports multithreaded I/O algorithms in SCSI SCRIPTS with fast
I/O context switching.
•
Expanded Register Move instruction supports additional arithmetic
capability.
1.5.2 PCI Performance
•
Complies with the PCI 2.1 specification.
•
64-bit or 32-bit 33 MHz PCI interface.
– Dual Address Cycle (DAC) can be generated for all SCRIPTS.
– True PCI Multifunction Device - presents one electrical load to
the PCI Bus.
•
Bursts 2/4, 4/8, 8/16, 16/32, 32/64, or 64/128 Qword/Dword transfers
across the PCI bus.
•
Supports 64-bit or 32-bit word data bursts with variable burst lengths.
•
Prefetches up to 8 Dwords of SCRIPTS instructions.
•
Bursts SCRIPTS opcode fetches across the PCI bus.
•
Performs zero wait-state bus master data bursts up to 264 Mbytes/s
(@ 33 MHz).
•
Supports PCI Cache Line Size register.
•
Supports PCI Write and Invalidate, Read Line, and Read Multiple
commands.
•
Complies with PCI Bus Power Management Specification
Revision 1.1.
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