LSI LSI53C896, Technical Manual

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PCI Configuration Registers 4-7
Registers: 0x09–0x0B
Class Code
Read Only
CC Class Code [23:0]
This 24-bit register is used to identify the generic function
of the device. The upper byte of this register is a base
class code, the middle byte is a subclass code, and the
lower byte identifies a specific register-level programming
interface. The value of this register is 0x010000, which
identifies a SCSI controller.
Register: 0x0C
Cache Line Size
Read/Write
CLS Cache Line Size [7:0]
This register specifies the system cache line size in units
of 32-bit words. The value in this register is used by the
device to determine whether to use Write and Invalidate
or Write commands for performing write cycles, and
whether to use Read, Read Line, or Read Multiple
commands for performing read cycles as a bus master.
Devices participating in the caching protocol use this field
to know when to retry burst accesses at cache line
boundaries. These devices can ignore the PCI cache
support lines (SDONE and SB0/) when this register is set
to 0. If this register is programmed to a number which is
not a power of 2, the device will not use PCI performance
commands to perform data transfers.
23 0
CC
0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7 0
CLS
0 0 0 0 0 0 0 0
*