LSI LSI53C896, Technical Manual

Page: 38 / 370

2-12 Functional Description
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The programmed burst size (in Dwords) must be equal to or greater
than the cache line size register. The
DMA Mode (DMODE) register
bits [7:6] and the Chip Test Five (CTEST5) register bit 2 are the burst
length bits.
•
The part must be doing a PCI Master transfer. The following PCI
Master transactions do not utilize the PCI cache logic and thus no
PCI cache commands will be issued during these types of cycles: a
nonprefetch SCRIPTS fetch, a Load/Store data transfer, a data flush
operation. All other types of PCI Master transactions will utilize the
PCI cache logic.
The above four conditions must be met for the cache logic to control the
type of PCI cache command that is issued, along with any alignment that
may be necessary during write operations. If these conditions are not
met for any given PCI Master transaction, a Memory Read or Memory
Write will be issued and no cache write alignment will be done.
2.1.4.2 Issuing Cache Commands
In order to issue each type of PCI cache command, the corresponding
enable bit must be set (2 bits in the case of Memory Write and
Invalidate).
•
To issue Memory Read Line commands, set the Memory Read Line
enable bit in the
DMA Mode (DMODE) register.
•
To issue Memory Read Multiple commands, set the Read Multiple
enable bit in the
DMA Mode (DMODE) register.
•
To issue Memory Write and Invalidate commands, set the Write and
Invalidate enables in both the
Chip Test Three (CTEST3) and the
PCI configuration Command registers.
If the corresponding cache command that is to be issued is not enabled
then the cache logic will fall back to the next command enabled, i.e., if
Memory Read Multiple is not enabled and Memory Read Lines are, read
lines will be issued in place of read multiples. If no cache commands are
enabled, cache write alignment will still occur but no cache commands
will be issued, only memory reads and memory writes will be issued.
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