LSI LSI53C896, Technical Manual

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SCSI Registers 4-69
Request (REQ/) is also asserted during start-of-transfer
and end-of-transfer cleanup and alignment, even if less
than a full burst of transfers is performed. The LSI53C896
SCSI function inserts a “fairness delay” of four CLKs
between burst transfers (as set in BL[2:0]) during normal
operation. The fairness delay is not inserted during PCI
retry cycles. This gives the CPU and other bus master
devices the opportunity to access the PCI bus between
bursts.
The LSI53C896 will only support burst thresholds of up
to 16 Dwords in the small FIFO mode. Setting the burst
threshold to higher than 16 Dwords in the small FIFO
mode will yield unexpected results in burst lengths. The
big FIFO mode can be activated by setting bit 5 of the
Chip Test Five (CTEST5) register.
SIOM Source I/O-Memory Enable 5
This bit is defined as an I/O Memory Enable bit for the
source address of a Memory Move or Block Move
Command. If this bit is set, then the source address is in
I/O space; and if cleared, then the source address is in
memory space.
This function is useful for register-to-memory operations
using the Memory Move instruction when a LSI53C896
SCSI function is I/O mapped. Bits 4 and 5 of the
Chip
Test Two (CTEST2) register are used to determine the
configuration status of the LSI53C896 SCSI function.
BL2
(CTEST5 bit 2) BL1 BL0
Burst Length
Transfers Dwords
0 0 0 2 4
0 0 1 4 8
0 1 0 8 16
0 1 1 16 32
1
1 0 0 32 64
1
1 0 1 64 128
1
1 1 0 64 128
1
1 1 1 Reserved Reserved
1. The 944 Byte FIFO must be enabled for these burst sizes.
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