LSI LSI53C896, Technical Manual

Page: 168 / 370

4-56 Registers
Register: 0x1A
Chip Test Two (CTEST2)
Read Only (bit 3 write)
DDIR Data Transfer Direction 7
This status bit indicates which direction data is being
transferred. When this bit is set, the data is transferred
from the SCSI bus to the host bus. When this bit is clear,
the data is transferred from the host bus to the SCSI bus.
SIGP Signal Process 6
This bit is a copy of the SIGP bit in the Interrupt Status
Zero (ISTAT0) register (bit 5). The SIGP bit is used to
signal a running SCRIPTS instruction. When this register
is read, the SIGP bit in the ISTAT0 register is cleared.
CIO Configured as I/O 5
This bit is defined as the Configuration I/O Enable Status
bit. This read only bit indicates if the chip is currently
enabled as I/O space.
CM Configured as Memory 4
This bit is defined as the configuration memory enable
status bit. This read only bit indicates if the chip is
currently enabled as memory space.
Note: Bits 4 and 5 may be set if the chip is mapped in both I/O
and memory space. Also, bits 4 and 5 may be set if the chip
is dual-mapped.
PCICIE PCI Configuration Info Enable 3
This bit controls the shadowing of the PCI Base Address
Register Two (SCRIPTS RAM) , PCI Base Address
Register One (MEMORY), PCI Device ID , and PCI
Revision ID (Rev ID) into the Scratch Register A
(SCRATCHA) , Memory Move Read Selector (MMRS) ,
Scratch Register B (SCRATCHB) , Memory Move Write
Selector (MMWS) , and SCRIPTS Fetch Selector (SFS)
registers.
7 6 5 4 3 2 1 0
DDIR SIGP CIO CM PCICIE TEOP DREQ DACK
0 0 x x 0 0 0 1
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